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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 1si685898pft.320.2018.02.20.09.49.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Feb 2018 09:49:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VGDVKwhr; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0024C20954CC9; Tue, 20 Feb 2018 09:43:58 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7070020954CBD for ; Tue, 20 Feb 2018 09:43:57 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id u15so16846215wrg.3 for ; Tue, 20 Feb 2018 09:49:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=1I+0r5d4l8j8ioIkrSsE5MYxlElcTzMgxuDAIAl/10Q=; b=VGDVKwhrLR2POMzMwGtl9sKwMkwaFfF5FOdrm5Pek4e9QkDja1AIU0J54fp07bXGw7 4+GTH7atvTC8HfpRf1ux22oXg5tbZLVPD0EjMdLyHvmhP23/bJSritJLmRYpNY1bO6C3 6/MbTIz9PZxGQNaY9ETz2hlFXNoQjkwza4hAM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=1I+0r5d4l8j8ioIkrSsE5MYxlElcTzMgxuDAIAl/10Q=; b=CWPkk9Ixp063oh4l7DpSv4dKQeXs0wES4y9btLso0frzZBB1J/1CNF4b0KU2BTTfkI MxYUeYShkINJSSZVrEDmZugetS8h5QWtn16C0v+nYoZ6FxIj/B/OW8TZl5gD8PMLFKTa 4Kvuf+JrbWMoavupSELyvwB/gpEVz1mG5O/8XUg8KUkPYdiZhoxa+2di02rxVqaveXQH LwAcWF/4LBKel/Vnrzcgcm75HSy5NBVfzMdrrA7/fXrcpMCe7UiU6t3cC/88jwviNFPI JIn7j1evZtldLu8g6cLwoFbnCRltGzl7qmgn2xhLDRdgFqLmw4CRauspBUiajS0NDQoM VrHg== X-Gm-Message-State: APf1xPC8PC+Ebul37pLj9pAK6+qgCN4sSdvhHBEDsV0WxVDlbAKULHaF IZD3CmUh3DKm+2uKGg3blaotRKl4GSA= X-Received: by 10.223.191.10 with SMTP id p10mr446770wrh.160.1519148993876; Tue, 20 Feb 2018 09:49:53 -0800 (PST) Received: from localhost.localdomain ([105.149.187.179]) by smtp.gmail.com with ESMTPSA id u63sm18282208wrc.26.2018.02.20.09.49.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Feb 2018 09:49:52 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 20 Feb 2018 17:49:37 +0000 Message-Id: <20180220174944.525-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v2 0/7] Add Secure96 mezzanine support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Almost a complete rewrite of the v1. I omitted the patches that add SPI and I2C DT nodes to the SynQuacer DTS. I did include the v2 of the Atmel AtSha204a driver, since the latter patches depend on it. This version implements a complete split between the generic 96boards LS connector support and its associated plumbing (defining which I2C, SPI and GPIO controllers are connected) on the one hand, and support for the Secure96 mezzanine board in particular on the other. More specifically, all Secure96 PCDs were dropped, and the only platform specific configuration that remains is including the Secure96 driver and the driver for its peripherals to the build. Patch #1 is v2 of the AtSha204a driver, with Leif's review comments addressed. Patch #2 introduces the mezzanine protocol, which abstracts away from any particular mezzanine implementation. Patch #3 introduces the generic I2C plumbing for any mezzanine that exposes I2C peripherals. Patch #4 implements the protocol that asserts the presence of a 96boards LS connector and the type of mezzanine connected to it. Patch #5 adds the Secure96 driver, which incorporates the DT overlay, and a description of the I2C peripheral. Patch #6 adds a generic driver for configuring the type of mezzanine, and to interface with it at end of DXE time to install the appropriate DT overlay. Patch #7 wires everything up for the DeveloperBox platform. Ard Biesheuvel (7): Silicon/Atmel: add support for AtSha204a RNG Platform/NinetySixBoards: introduce package and mezzanine protocol Platform/NinetySixBoards: introduce I2C driver Platform/NinetySixBoards: introduce LsConnector protocol Platform/NinetySixBoards: add a driver for the Secure96 mezzanine board Platform/NinetySixBoards: add core driver for LS connector and config Platform/Socionext/DeveloperBox: add 96boards mezzanine support Platform/NinetySixBoards/Include/Guid/FormSet.h | 23 ++ Platform/NinetySixBoards/Include/Protocol/LsConnector.h | 35 +++ Platform/NinetySixBoards/Include/Protocol/Mezzanine.h | 71 +++++ Platform/NinetySixBoards/NinetySixBoards.dec | 73 +++++ Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.c | 221 ++++++++++++++ Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.h | 32 ++ Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.inf | 57 ++++ Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsHii.uni | 27 ++ Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsHii.vfr | 51 ++++ Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe.c | 202 +++++++++++++ Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe.inf | 51 ++++ Platform/NinetySixBoards/Secure96Dxe/Secure96.dts | 76 +++++ Platform/NinetySixBoards/Secure96Dxe/Secure96.h | 26 ++ Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.c | 211 +++++++++++++ Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.inf | 67 +++++ Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 34 +++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 10 + Silicon/Atmel/AtSha204a/AtSha204a.dec | 22 ++ Silicon/Atmel/AtSha204a/AtSha204aDriver.c | 309 ++++++++++++++++++++ Silicon/Atmel/AtSha204a/AtSha204aDriver.h | 81 +++++ Silicon/Atmel/AtSha204a/AtSha204aDxe.inf | 52 ++++ Silicon/Atmel/AtSha204a/ComponentName.c | 186 ++++++++++++ Silicon/Atmel/AtSha204a/DriverBinding.c | 242 +++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 9 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 + 25 files changed, 2170 insertions(+) create mode 100644 Platform/NinetySixBoards/Include/Guid/FormSet.h create mode 100644 Platform/NinetySixBoards/Include/Protocol/LsConnector.h create mode 100644 Platform/NinetySixBoards/Include/Protocol/Mezzanine.h create mode 100644 Platform/NinetySixBoards/NinetySixBoards.dec create mode 100644 Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.c create mode 100644 Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.h create mode 100644 Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.inf create mode 100644 Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsHii.uni create mode 100644 Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsHii.vfr create mode 100644 Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe.c create mode 100644 Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe.inf create mode 100644 Platform/NinetySixBoards/Secure96Dxe/Secure96.dts create mode 100644 Platform/NinetySixBoards/Secure96Dxe/Secure96.h create mode 100644 Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.c create mode 100644 Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.inf create mode 100644 Silicon/Atmel/AtSha204a/AtSha204a.dec create mode 100644 Silicon/Atmel/AtSha204a/AtSha204aDriver.c create mode 100644 Silicon/Atmel/AtSha204a/AtSha204aDriver.h create mode 100644 Silicon/Atmel/AtSha204a/AtSha204aDxe.inf create mode 100644 Silicon/Atmel/AtSha204a/ComponentName.c create mode 100644 Silicon/Atmel/AtSha204a/DriverBinding.c -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel