From patchwork Thu Mar 24 10:37:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 64316 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp549906lbc; Thu, 24 Mar 2016 03:38:29 -0700 (PDT) X-Received: by 10.98.44.73 with SMTP id s70mr11623960pfs.2.1458815901929; Thu, 24 Mar 2016 03:38:21 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id h88si11418591pfd.74.2016.03.24.03.38.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Mar 2016 03:38:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E4B171A1F3B; Thu, 24 Mar 2016 03:38:26 -0700 (PDT) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3EA351A1F45 for ; Thu, 24 Mar 2016 03:38:25 -0700 (PDT) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id A138564363; Thu, 24 Mar 2016 10:37:59 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-47.phx2.redhat.com [10.3.113.47]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u2OAbRfg032425; Thu, 24 Mar 2016 06:37:58 -0400 From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 24 Mar 2016 11:37:08 +0100 Message-Id: <1458815844-24793-20-git-send-email-lersek@redhat.com> In-Reply-To: <1458815844-24793-1-git-send-email-lersek@redhat.com> References: <1458815844-24793-1-git-send-email-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Thu, 24 Mar 2016 10:37:59 +0000 (UTC) Subject: [edk2] [PATCH 19/35] QuarkSocPkg: IntelQNCLib: remove set but unused variables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This patch also removes a few PCI config space accesses, but that shouldn't be a problem. Cc: Michael D Kinney Cc: Kelly Steele Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c index 5cb0fb855460..4b6f7ba773d4 100644 --- a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c +++ b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c @@ -403,9 +403,6 @@ PcieSetAspmAuto ( UINT32 EndpointPcieCapOffset; UINT16 RootPortAspm; UINT16 EndPointAspm; - UINT16 EndPointVendorId; - UINT16 EndPointDeviceId; - UINT8 EndPointRevId; UINT16 AspmVal; UINT32 PortLxLat; UINT32 EndPointLxLat; @@ -438,14 +435,10 @@ PcieSetAspmAuto ( EndPointAspm = (QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, (EndpointPcieCapOffset + PCIE_LINK_CAP_OFFSET)) & B_QNC_PCIE_LCAP_APMS_MASK) >> V_QNC_PCIE_LCAP_APMS_OFFSET; // - // Mask APMC with values from lookup table. + // TODO: Mask APMC with values from lookup table. // RevID of 0xFF applies to all steppings. // - EndPointVendorId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 0); - EndPointDeviceId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 2); - EndPointRevId = QNCMmPci8 (0, EndpointBus, EndpointDevice, EndpointFunction, 8); - // TODO: Mask with latency/acceptable latency comparison results. AspmVal = RootPortAspm; @@ -585,7 +578,6 @@ QNCRootPortInit ( { UINT64 RPBase; UINT64 EndPointBase; - UINT64 LpcBase; UINT16 AspmVal; UINT16 SlotStatus; UINTN Index; @@ -593,7 +585,6 @@ QNCRootPortInit ( UINT32 DwordReg; RPBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + ((PCI_DEVICE_NUMBER_PCIE_ROOTPORT) << 3) + ((PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex) << 0)) << 12); - LpcBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + (31 << 3) + (0 << 0)) << 12); CapOffset = PcieFindCapId (PCI_BUS_NUMBER_QNC, (UINT8)(PCI_DEVICE_NUMBER_PCIE_ROOTPORT), (UINT8)(PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex), PCIE_CAPID); if (CapOffset == 0) { @@ -906,7 +897,6 @@ PciExpressInit ( { UINT64 PciExpressBar; UINT32 QNCRootComplexBar; - UINT32 QNCGpioBase; UINT32 QNCPmioBase; UINT32 QNCGpeBase; UINTN RpEnableMask; @@ -917,7 +907,6 @@ PciExpressInit ( // Get BAR registers // QNCRootComplexBar = QNC_RCRB_BASE; - QNCGpioBase = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK; QNCPmioBase = LpcPciCfg32 (R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; QNCGpeBase = LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK; RpEnableMask = 0; // assume all root ports are disabled