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[198.145.21.10]) by mx.google.com with ESMTPS id q195si5422906pfq.247.2016.04.06.09.16.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Apr 2016 09:16:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 042AE1A1FE6; Wed, 6 Apr 2016 09:15:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4BBE11A1FE6 for ; Wed, 6 Apr 2016 09:15:57 -0700 (PDT) Received: by mail-wm0-x232.google.com with SMTP id f198so80676920wme.0 for ; Wed, 06 Apr 2016 09:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bs5k53fAdIkMbWBGCBGD1rOtBhZMzPTXYTUkdNvyIuk=; b=Wet0OhN1h488ZkC3cOlxvrKGfetagoeJH61NznQYPncpJPw9mqKKJEpedx1zWwvzrx aP+88KaXd7KzPy2YYqmS2cWdVe6hgFq7SapNAFEaPXH9rVX5FIZ9DEwkANfzGCyXjZ0n g0J72UA+BTPJyxuXcJCsHjjZKUKcG1M0I5Prc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bs5k53fAdIkMbWBGCBGD1rOtBhZMzPTXYTUkdNvyIuk=; b=d6SXhkPC1Athb6XCOp2CamSO43vnpuW67cs5FXFLL4e5zEgUruE9cKyrYQEtvm8p6S R2ttuiKqJ6SfKiV+qmbi8qY1XHu7tHcDoGrcyIy72Ck89fWQEFq/3f0FbU1jaeCjBpnk XpUhiEHhGp24FOuzBJF973QTckML95o7rktdrLjsoscQA86ikVnu+ggGC3lbLfrnEHxd 0RlgqY+Sbk+o5rNkqn1i3cF/PDHa3bQku4Ael5SJ0+adsmmgB/MD/MQcDLXSNEH+9kLm AY51CBwgmRK9AnrDsnIPgvqM653fcJhnRAuwHUUwCxmRoS1i3yKgrDfSzzdCTBC0p97u d5oA== X-Gm-Message-State: AD7BkJIDKagswZavQvhZVS0f5ykjdRGFnTvVmBM0LJU60Iy5Z7/jozwHmhSATQL6o8sNoPUi X-Received: by 10.28.130.67 with SMTP id e64mr25031692wmd.6.1459959356034; Wed, 06 Apr 2016 09:15:56 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id om6sm3961219wjc.40.2016.04.06.09.15.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Apr 2016 09:15:55 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, lersek@redhat.com Date: Wed, 6 Apr 2016 18:15:15 +0200 Message-Id: <1459959319-19293-18-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459959319-19293-1-git-send-email-ard.biesheuvel@linaro.org> References: <1459959319-19293-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 17/21] ArmVirtPkg/VirtFdtDxe: drop PCI host bridge handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Now that the PCI host bridge driver parses the DT node that describes the PCI host bridge directly via the FDT client protocol, we can drop the handling from VirtFdtDxe completely. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirtQemu.dsc | 7 - ArmVirtPkg/ArmVirtQemuKernel.dsc | 7 - ArmVirtPkg/ArmVirtXen.dsc | 7 - ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 203 -------------------- ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf | 9 - 5 files changed, 233 deletions(-) -- 2.5.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 4eb350e805d4..9942c0228687 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -212,13 +212,6 @@ [PcdsDynamicDefault.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0 # diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc index 32484fffa126..1e4d176a1f82 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -197,13 +197,6 @@ [PcdsDynamicDefault.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0 # diff --git a/ArmVirtPkg/ArmVirtXen.dsc b/ArmVirtPkg/ArmVirtXen.dsc index 0af82be42913..2677c1900c49 100644 --- a/ArmVirtPkg/ArmVirtXen.dsc +++ b/ArmVirtPkg/ArmVirtXen.dsc @@ -133,13 +133,6 @@ [PcdsDynamicDefault.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0 - gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0 - gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0 gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c index 0a47092e35ce..31e0ca7db8b4 100644 --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c @@ -45,7 +45,6 @@ typedef enum { PropertyTypeRtc, PropertyTypeVirtio, PropertyTypeUart, - PropertyTypePciHost, PropertyTypeXen, } PROPERTY_TYPE; @@ -58,7 +57,6 @@ STATIC CONST PROPERTY CompatibleProperties[] = { { PropertyTypeRtc, "arm,pl031" }, { PropertyTypeVirtio, "virtio,mmio" }, { PropertyTypeUart, "arm,pl011" }, - { PropertyTypePciHost, "pci-host-ecam-generic" }, { PropertyTypeXen, "xen,xen" }, { PropertyTypeUnknown, "" } }; @@ -88,176 +86,6 @@ GetTypeFromNode ( return PropertyTypeUnknown; } -// -// We expect the "ranges" property of "pci-host-ecam-generic" to consist of -// records like this. -// -#pragma pack (1) -typedef struct { - UINT32 Type; - UINT64 ChildBase; - UINT64 CpuBase; - UINT64 Size; -} DTB_PCI_HOST_RANGE_RECORD; -#pragma pack () - -#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31 -#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30 -#define DTB_PCI_HOST_RANGE_ALIASED BIT29 -#define DTB_PCI_HOST_RANGE_MMIO32 BIT25 -#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) -#define DTB_PCI_HOST_RANGE_IO BIT24 -#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24) - -/** - Process the device tree node describing the generic PCI host controller. - - param[in] DeviceTreeBase Pointer to the device tree. - - param[in] Node Offset of the device tree node whose "compatible" - property is "pci-host-ecam-generic". - - param[in] RegProp Pointer to the "reg" property of Node. The caller - is responsible for ensuring that the size of the - property is 4 UINT32 cells. - - @retval EFI_SUCCESS Parsing successful, properties parsed from Node - have been stored in dynamic PCDs. - - @retval EFI_PROTOCOL_ERROR Parsing failed. PCDs are left unchanged. -**/ -STATIC -EFI_STATUS -EFIAPI -ProcessPciHost ( - IN CONST VOID *DeviceTreeBase, - IN INT32 Node, - IN CONST VOID *RegProp - ) -{ - UINT64 ConfigBase, ConfigSize; - CONST VOID *Prop; - INT32 Len; - UINT32 BusMin, BusMax; - UINT32 RecordIdx; - UINT64 IoBase, IoSize, IoTranslation; - UINT64 MmioBase, MmioSize, MmioTranslation; - - // - // Fetch the ECAM window. - // - ConfigBase = fdt64_to_cpu (((CONST UINT64 *)RegProp)[0]); - ConfigSize = fdt64_to_cpu (((CONST UINT64 *)RegProp)[1]); - - // - // Fetch the bus range (note: inclusive). - // - Prop = fdt_getprop (DeviceTreeBase, Node, "bus-range", &Len); - if (Prop == NULL || Len != 2 * sizeof(UINT32)) { - DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n", - __FUNCTION__)); - return EFI_PROTOCOL_ERROR; - } - BusMin = fdt32_to_cpu (((CONST UINT32 *)Prop)[0]); - BusMax = fdt32_to_cpu (((CONST UINT32 *)Prop)[1]); - - // - // Sanity check: the config space must accommodate all 4K register bytes of - // all 8 functions of all 32 devices of all buses. - // - if (BusMax < BusMin || BusMax - BusMin == MAX_UINT32 || - DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < BusMax - BusMin + 1) { - DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n", - __FUNCTION__)); - return EFI_PROTOCOL_ERROR; - } - - // - // Iterate over "ranges". - // - Prop = fdt_getprop (DeviceTreeBase, Node, "ranges", &Len); - if (Prop == NULL || Len == 0 || - Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) { - DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__)); - return EFI_PROTOCOL_ERROR; - } - - // - // IoBase, IoTranslation, MmioBase and MmioTranslation are initialized only - // in order to suppress '-Werror=maybe-uninitialized' warnings *incorrectly* - // emitted by some gcc versions. - // - IoBase = 0; - IoTranslation = 0; - MmioBase = 0; - MmioTranslation = 0; - - // - // IoSize and MmioSize are initialized to zero because the logic below - // requires it. - // - IoSize = 0; - MmioSize = 0; - for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD); - ++RecordIdx) { - CONST DTB_PCI_HOST_RANGE_RECORD *Record; - - Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx; - switch (fdt32_to_cpu (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) { - case DTB_PCI_HOST_RANGE_IO: - IoBase = fdt64_to_cpu (Record->ChildBase); - IoSize = fdt64_to_cpu (Record->Size); - IoTranslation = fdt64_to_cpu (Record->CpuBase) - IoBase; - break; - - case DTB_PCI_HOST_RANGE_MMIO32: - MmioBase = fdt64_to_cpu (Record->ChildBase); - MmioSize = fdt64_to_cpu (Record->Size); - MmioTranslation = fdt64_to_cpu (Record->CpuBase) - MmioBase; - - if (MmioBase > MAX_UINT32 || MmioSize > MAX_UINT32 || - MmioBase + MmioSize > SIZE_4GB) { - DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__)); - return EFI_PROTOCOL_ERROR; - } - - if (MmioTranslation != 0) { - DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation " - "0x%Lx\n", __FUNCTION__, MmioTranslation)); - return EFI_UNSUPPORTED; - } - - break; - } - } - if (IoSize == 0 || MmioSize == 0) { - DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__, - (IoSize == 0) ? "IO" : "MMIO32")); - return EFI_PROTOCOL_ERROR; - } - - PcdSet64 (PcdPciExpressBaseAddress, ConfigBase); - - PcdSet32 (PcdPciBusMin, BusMin); - PcdSet32 (PcdPciBusMax, BusMax); - - PcdSet64 (PcdPciIoBase, IoBase); - PcdSet64 (PcdPciIoSize, IoSize); - PcdSet64 (PcdPciIoTranslation, IoTranslation); - - PcdSet32 (PcdPciMmio32Base, (UINT32)MmioBase); - PcdSet32 (PcdPciMmio32Size, (UINT32)MmioSize); - - PcdSetBool (PcdPciDisableBusEnumeration, FALSE); - - DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] " - "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase, - ConfigSize, BusMin, BusMax, IoBase, IoSize, IoTranslation, MmioBase, - MmioSize, MmioTranslation)); - return EFI_SUCCESS; -} - - EFI_STATUS EFIAPI InitializeVirtFdtDxe ( @@ -277,7 +105,6 @@ InitializeVirtFdtDxe ( VIRTIO_TRANSPORT_DEVICE_PATH *DevicePath; EFI_HANDLE Handle; UINT64 RegBase; - BOOLEAN HavePci; Hob = GetFirstGuidHob(&gFdtHobGuid); if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) { @@ -293,7 +120,6 @@ InitializeVirtFdtDxe ( DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase)); RtcNode = -1; - HavePci = FALSE; // // Now enumerate the nodes and install peripherals that we are interested in, // i.e., GIC, RTC and virtio MMIO nodes @@ -323,13 +149,6 @@ InitializeVirtFdtDxe ( ASSERT (RegProp != NULL); switch (PropType) { - case PropertyTypePciHost: - ASSERT (Len == 2 * sizeof (UINT64)); - Status = ProcessPciHost (DeviceTreeBase, Node, RegProp); - ASSERT_EFI_ERROR (Status); - HavePci = TRUE; - break; - case PropertyTypeVirtio: ASSERT (Len == 16); // @@ -433,28 +252,6 @@ InitializeVirtFdtDxe ( "disabled") != 0) { DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n")); } - - if (HavePci) { - // - // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI - // setup we will perform in the firmware is honored by the Linux OS, - // rather than torn down and done from scratch. This is generally a more - // sensible approach, and aligns with what ACPI based OSes do in general. - // - // In case we are exposing an emulated VGA PCI device to the guest, which - // may subsequently get exposed via the Graphics Output protocol and - // driven as an efifb by Linux, we need this setting to prevent the - // framebuffer from becoming unresponsive. - // - Node = fdt_path_offset (DeviceTreeBase, "/chosen"); - if (Node < 0) { - Node = fdt_add_subnode (DeviceTreeBase, 0, "/chosen"); - } - if (Node < 0 || - fdt_setprop_u32 (DeviceTreeBase, Node, "linux,pci-probe-only", 1) < 0) { - DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only property\n")); - } - } } return EFI_SUCCESS; } diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf index 6c8ba68599ae..8ebce337747f 100644 --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.inf @@ -51,15 +51,6 @@ [Guids] [Pcd] gArmPlatformTokenSpaceGuid.PcdPL031RtcBase - gArmPlatformTokenSpaceGuid.PcdPciBusMin - gArmPlatformTokenSpaceGuid.PcdPciBusMax - gArmPlatformTokenSpaceGuid.PcdPciIoBase - gArmPlatformTokenSpaceGuid.PcdPciIoSize - gArmPlatformTokenSpaceGuid.PcdPciIoTranslation - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration [FeaturePcd] gArmVirtTokenSpaceGuid.PcdPureAcpiBoot