From patchwork Tue May 10 00:37:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 67385 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp1858388qge; Mon, 9 May 2016 17:37:45 -0700 (PDT) X-Received: by 10.98.25.15 with SMTP id 15mr54580809pfz.60.1462840665884; Mon, 09 May 2016 17:37:45 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id c75si40513133pfb.9.2016.05.09.17.37.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 May 2016 17:37:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8CE3E1A1F0B; Mon, 9 May 2016 17:37:44 -0700 (PDT) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CDBAF1A1F07 for ; Mon, 9 May 2016 17:37:42 -0700 (PDT) Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6893A7D0EF; Tue, 10 May 2016 00:37:42 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-38.phx2.redhat.com [10.3.113.38]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4A0bc8H001870; Mon, 9 May 2016 20:37:41 -0400 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 10 May 2016 02:37:31 +0200 Message-Id: <1462840655-1802-3-git-send-email-lersek@redhat.com> In-Reply-To: <1462840655-1802-1-git-send-email-lersek@redhat.com> References: <1462840655-1802-1-git-send-email-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 10 May 2016 00:37:42 +0000 (UTC) Subject: [edk2] [PATCH 2/6] OvmfPkg: add and use industry standard macro PIIX4_PMBA_MASK X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" We already have the identical purpose (but different value) macro for ICH9, namely ICH9_PMBASE_MASK in "OvmfPkg/Include/IndustryStandard/Q35MchIch9.h". Also, stop bit-negating signed integer constants. Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 2 ++ OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c | 2 +- OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 2 +- OvmfPkg/PlatformPei/Platform.c | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h index 8cbd685ab509..baa4c063f16a 100644 --- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -31,10 +31,12 @@ // B/D/F/Type: 0/1/3/PCI // #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset)) #define PIIX4_PMBA 0x40 +#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \ + BIT10 | BIT9 | BIT8 | BIT7 | BIT6) #define PIIX4_PMREGMISC 0x80 #define PIIX4_PMREGMISC_PMIOSE BIT0 #endif diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c index f722731ca4f6..e85f18f8090d 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -71,11 +71,11 @@ AcpiTimerLibConstructor ( if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) { // // If the Power Management Base Address is not programmed, // then program the Power Management Base Address from a PCD. // - PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, + PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress)); // // Enable PMBA I/O port decodes // diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c index b0ab783843a8..52eaaf0ad339 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -67,11 +67,11 @@ AcpiTimerLibConstructor ( if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) { // // If the Power Management Base Address is not programmed, // then program the Power Management Base Address from a PCD. // - PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, + PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress)); // // Enable PMBA I/O port decodes // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index e4e21da5aa9b..a40be990696b 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -410,11 +410,11 @@ MiscInitialization ( if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) { // // The PEI phase should be exited with fully accessibe ACPI PM IO space: // 1. set PMBA // - PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, + PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, FixedPcdGet16 (PcdPiix4AcpiPmBaseAddress)); // // 2. set PCICMD/IOSE //