From patchwork Tue May 10 00:37:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 67389 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp1858433qge; Mon, 9 May 2016 17:37:54 -0700 (PDT) X-Received: by 10.67.13.144 with SMTP id ey16mr54179821pad.147.1462840674500; Mon, 09 May 2016 17:37:54 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id co4si41787646pad.101.2016.05.09.17.37.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 May 2016 17:37:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7AD961A1F21; Mon, 9 May 2016 17:37:48 -0700 (PDT) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3BDBE1A1F02 for ; Mon, 9 May 2016 17:37:47 -0700 (PDT) Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C9CA061A0C; Tue, 10 May 2016 00:37:46 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-38.phx2.redhat.com [10.3.113.38]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4A0bc8L001870; Mon, 9 May 2016 20:37:46 -0400 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 10 May 2016 02:37:35 +0200 Message-Id: <1462840655-1802-7-git-send-email-lersek@redhat.com> In-Reply-To: <1462840655-1802-1-git-send-email-lersek@redhat.com> References: <1462840655-1802-1-git-send-email-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 10 May 2016 00:37:46 +0000 (UTC) Subject: [edk2] [PATCH 6/6] OvmfPkg/PlatformPei: provide 10 * 4KB of PCI IO Port space on Q35 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This can accommodate 10 bridges (including root bridges, PCIe upstream and downstream ports, etc -- see for more details). 10 is not a whole lot, but closer to the architectural limit of 15 than our current 4, so it can be considered a stop-gap solution until all guests manage to migrate to virtio-1.0, and no longer need PCI IO BARs behind PCIe downstream ports. Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/Platform.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 15a51f2abb03..fd60a9c91c1b 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -242,10 +242,20 @@ MemMapInitialization ( AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB, EfiReservedMemoryType); } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); + + // + // On Q35, the IO Port space is available for PCI resource allocations from + // 0x6000 up. + // + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + PciIoBase = 0x6000; + PciIoSize = 0xA000; + ASSERT ((FixedPcdGet16 (PcdIch9AcpiPmBaseAddress) & 0xF000) < PciIoBase); + } } // // Add PCI IO Port space available for PCI resource allocations. //