From patchwork Tue May 10 02:24:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wu, Hao A" X-Patchwork-Id: 67391 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp1889373qge; Mon, 9 May 2016 19:25:22 -0700 (PDT) X-Received: by 10.66.236.167 with SMTP id uv7mr55644042pac.75.1462847122853; Mon, 09 May 2016 19:25:22 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id z68si41056724pfz.158.2016.05.09.19.25.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 May 2016 19:25:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 520CF1A1F2D; Mon, 9 May 2016 19:25:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by ml01.01.org (Postfix) with ESMTP id 0A4F31A1F1B for ; Mon, 9 May 2016 19:25:15 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 09 May 2016 19:25:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,603,1455004800"; d="scan'208";a="972208662" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.34]) by orsmga002.jf.intel.com with ESMTP; 09 May 2016 19:25:06 -0700 From: Hao Wu To: edk2-devel@lists.01.org, feng.tian@intel.com Date: Tue, 10 May 2016 10:24:50 +0800 Message-Id: <1462847091-32836-6-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1462847091-32836-1-git-send-email-hao.a.wu@intel.com> References: <1462847091-32836-1-git-send-email-hao.a.wu@intel.com> Subject: [edk2] [PATCH v2 5/6] OvmfPkg/QemuNewBootOrderLib: adapt Q35 SATA PMPN to UEFI spec Mantis 1353 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Jordan Justen , Laszlo Ersek MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Laszlo Ersek On the Q35 machine type of QEMU, there is no port multiplier connected to the on-board SATA controller. Therefore the AtaAtapiPassThru driver update for Mantis ticket 1353 changes the middle number (the Port Multiplier Port Number) in the Sata() device path nodes from 0x0 to 0xFFFF. Adapt the translation from OpenFirmware in QemuNewBootOrderLib. Cc: Jordan Justen Cc: Feng Tian Cc: Hao Wu Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 1.9.5.msysgit.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c b/OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c index 6c57612..c5f165a 100644 --- a/OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c +++ b/OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c @@ -786,11 +786,11 @@ TranslatePciOfwNodes ( // // UEFI device path: // - // PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x1,0x0,0x0) - // ^ ^ ^ - // | | LUN (always 0 on Q35) + // PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x1,0xFFFF,0x0) + // ^ ^ ^ + // | | LUN (always 0 on Q35) // | port multiplier port number, - // | always 0 on Q35 + // | always 0xFFFF on Q35 // channel (port) number // UINT64 Channel; @@ -805,7 +805,7 @@ TranslatePciOfwNodes ( Written = UnicodeSPrintAsciiFormat ( Translated, *TranslatedSize * sizeof (*Translated), // BufferSize in bytes - "PciRoot(0x%x)%s/Pci(0x%Lx,0x%Lx)/Sata(0x%Lx,0x0,0x0)", + "PciRoot(0x%x)%s/Pci(0x%Lx,0x%Lx)/Sata(0x%Lx,0xFFFF,0x0)", PciRoot, Bridges, PciDevFun[0],