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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id a73si944590pfc.20.2016.08.31.11.00.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Aug 2016 11:00:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3E6681A1E6C; Wed, 31 Aug 2016 11:00:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B29E1A1E67 for ; Wed, 31 Aug 2016 11:00:01 -0700 (PDT) Received: by mail-wm0-x235.google.com with SMTP id 1so54727705wmz.1 for ; Wed, 31 Aug 2016 11:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5HL95h2THFQxHURKE9gFVUK4DU8z18/fL6YyxpIPHH0=; b=jc2S8K+xWuyUnQrIG7JRJHfotkRezDXlOC5vTu7ap2m8JIvCP3voNA6uYo/5ihToPb TJkHNq43FqXCCDOdNYqwoGhVp2O5r0FRZP3L131pkHHBaCmMSM4J7Ze7l+nU02adeM1e WUukm19fjxpvzlORj1Ws7DnvWlb1q34iGC4a0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5HL95h2THFQxHURKE9gFVUK4DU8z18/fL6YyxpIPHH0=; b=Q3DfxmnRJQDC6v24NRbynwh6t6oiCUwtD70ywvK20vTVFUXVjBSEnfN0p2WIDBbud8 gS9ZYhvz9Taki76fEK/O5DkLQDoEqTFooQ7sDndKBEThGO5TRONY6nfhWmnzQiC5dBa3 hCwITSdvWv6YAKtcbvAFNQ1Y4FGkFw3sDSHrwNDoD4cG1lCvpy2/Hyma9zVVHQOmam4C zID1FiGzN/GMIIQvwohI9+dLLy8LYLFwtpmRLQq9uC5IP9T0svEZV8xj6qln9L/bc2t0 6vQFf2h4myDEQmwc2DluLmMiWk11kj9IicOyxw7EzQwQZo9/qfs/f+5dfFhUnWN9DllT Cg6A== X-Gm-Message-State: AE9vXwNE3Lm4BKtYQQ18crbmn4RBFBDL5uyUfap41TM/XLZ9GG9nQ7fSYoL+OjXwPg8EpkKn X-Received: by 10.195.11.104 with SMTP id eh8mr10280353wjd.128.1472666400007; Wed, 31 Aug 2016 11:00:00 -0700 (PDT) Received: from localhost.localdomain ([105.151.173.94]) by smtp.gmail.com with ESMTPSA id d62sm10118417wmd.7.2016.08.31.10.59.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Aug 2016 10:59:59 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, lersek@redhat.com Date: Wed, 31 Aug 2016 18:59:38 +0100 Message-Id: <1472666379-25426-6-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472666379-25426-1-git-send-email-ard.biesheuvel@linaro.org> References: <1472666379-25426-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" If the pci-host-ecam-generic DT node describes a 64-bit MMIO region, account for it in the PCI_ROOT_BRIDGE description that we return to the generic PciHostBridgeDxe implementation, which will be able to allocate BARs from it without any further changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65 --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 78 ++++++++++++++------ ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 + 2 files changed, 57 insertions(+), 22 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Laszlo Ersek diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index c2aa4a339c19..efccedcca14f 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -87,8 +87,10 @@ EFI_STATUS ProcessPciHost ( OUT UINT64 *IoBase, OUT UINT64 *IoSize, - OUT UINT64 *MmioBase, - OUT UINT64 *MmioSize, + OUT UINT64 *Mmio32Base, + OUT UINT64 *Mmio32Size, + OUT UINT64 *Mmio64Base, + OUT UINT64 *Mmio64Size, OUT UINT32 *BusMin, OUT UINT32 *BusMax ) @@ -101,7 +103,8 @@ ProcessPciHost ( UINT32 RecordIdx; EFI_STATUS Status; UINT64 IoTranslation; - UINT64 MmioTranslation; + UINT64 Mmio32Translation; + UINT64 Mmio64Translation; // // The following output arguments are initialized only in @@ -109,17 +112,19 @@ ProcessPciHost ( // *incorrectly* emitted by some gcc versions. // *IoBase = 0; - *MmioBase = 0; + *Mmio32Base = 0; + *Mmio64Base = MAX_UINT64; *BusMin = 0; *BusMax = 0; // - // *IoSize, *MmioSize and IoTranslation are initialized to zero because the + // *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the // logic below requires it. However, since they are also affected by the issue // reported above, they are initialized early. // *IoSize = 0; - *MmioSize = 0; + *Mmio32Size = 0; + *Mmio64Size = 0; IoTranslation = 0; Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL, @@ -209,28 +214,43 @@ ProcessPciHost ( break; case DTB_PCI_HOST_RANGE_MMIO32: - *MmioBase = SwapBytes64 (Record->ChildBase); - *MmioSize = SwapBytes64 (Record->Size); - MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase; + *Mmio32Base = SwapBytes64 (Record->ChildBase); + *Mmio32Size = SwapBytes64 (Record->Size); + Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base; - if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 || - *MmioBase + *MmioSize > SIZE_4GB) { + if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 || + *Mmio32Base + *Mmio32Size > SIZE_4GB) { DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__)); return EFI_PROTOCOL_ERROR; } - ASSERT (PcdGet64 (PcdPciMmio32Translation) == MmioTranslation); + ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation); - if (MmioTranslation != 0) { + if (Mmio32Translation != 0) { DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation " - "0x%Lx\n", __FUNCTION__, MmioTranslation)); + "0x%Lx\n", __FUNCTION__, Mmio32Translation)); + return EFI_UNSUPPORTED; + } + + break; + + case DTB_PCI_HOST_RANGE_MMIO64: + *Mmio64Base = SwapBytes64 (Record->ChildBase); + *Mmio64Size = SwapBytes64 (Record->Size); + Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base; + + ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation); + + if (Mmio64Translation != 0) { + DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO64 translation " + "0x%Lx\n", __FUNCTION__, Mmio64Translation)); return EFI_UNSUPPORTED; } break; } } - if (*IoSize == 0 || *MmioSize == 0) { + if (*IoSize == 0 || *Mmio32Size == 0) { DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__, (*IoSize == 0) ? "IO" : "MMIO32")); return EFI_PROTOCOL_ERROR; @@ -243,9 +263,9 @@ ProcessPciHost ( ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase); DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] " - "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase, - ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *MmioBase, - *MmioSize)); + "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n", + __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, + IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size)); return EFI_SUCCESS; } @@ -268,6 +288,7 @@ PciHostBridgeGetRootBridges ( { UINT64 IoBase, IoSize; UINT64 Mmio32Base, Mmio32Size; + UINT64 Mmio64Base, Mmio64Size; UINT32 BusMin, BusMax; EFI_STATUS Status; @@ -278,8 +299,8 @@ PciHostBridgeGetRootBridges ( return NULL; } - Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, &BusMin, - &BusMax); + Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, + &Mmio64Base, &Mmio64Size, &BusMin, &BusMax); if (EFI_ERROR (Status)) { DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n", __FUNCTION__, Status)); @@ -308,8 +329,21 @@ PciHostBridgeGetRootBridges ( mRootBridge.Io.Limit = IoBase + IoSize - 1; mRootBridge.Mem.Base = Mmio32Base; mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1; - mRootBridge.MemAbove4G.Base = MAX_UINT64; - mRootBridge.MemAbove4G.Limit = 0; + + if (sizeof (UINTN) == sizeof (UINT64)) { + mRootBridge.MemAbove4G.Base = Mmio64Base; + mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1; + mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + } else { + // + // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit + // architecture such as ARM, we will not be able to access 64-bit MMIO + // BARs unless they are allocated below 4 GB. So ignore the range above + // 4 GB in this case. + // + mRootBridge.MemAbove4G.Base = MAX_UINT64; + mRootBridge.MemAbove4G.Limit = 0; + } // // No separate ranges for prefetchable and non-prefetchable BARs diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index fc1d37fb3c23..0995f4b7a156 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -47,6 +47,7 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Translation [Pcd] gArmTokenSpaceGuid.PcdPciIoTranslation