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[198.145.21.10]) by mx.google.com with ESMTPS id r78si845430pfb.617.2017.09.21.04.07.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Sep 2017 04:07:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KYctsk0F; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0061221D492FB; Thu, 21 Sep 2017 04:04:13 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-pf0-x22e.google.com (mail-pf0-x22e.google.com [IPv6:2607:f8b0:400e:c00::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3515721D492FB for ; Thu, 21 Sep 2017 04:04:11 -0700 (PDT) Received: by mail-pf0-x22e.google.com with SMTP id l188so3052164pfc.6 for ; Thu, 21 Sep 2017 04:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5okhHE/a/4jp/CoPvoSZWybK1hFfVS5fSxHpykCrh8U=; b=KYctsk0F0AWU2+y2A1h+d1usXpQCX4RYGEXJErGagoXe5rooLtx8nrK+01Iid8BcPD n4BsOy4hajj7gW7PhZGXRxCpZIUD2qgcDcwBwZzuZ64v0lPg3zrgfn7Aii37zG7yIFiq KURJxIhD9cuHqZOWul0/8XkWMzFyrl5ZXE/PY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5okhHE/a/4jp/CoPvoSZWybK1hFfVS5fSxHpykCrh8U=; b=dl6EyeZrBP/I4AspUYqUDy3TirYKvajqS38PdIiAQf5dn2ZYmVd95sORx0xi2L1Hzj jnXicZ10MD+NPvj9/rOpTx5EYCZgKVPv/KCAboNAt9gbDhvQ6qZApd7qdSbkVQVDv+uM zjZaktlGJ60RQ/H133HKyKEKpCKaBEUF86WM6bWjodi4JHb2nDDfW3YiaRty8IDKJNoU eSuqAm4yF2Pa4CYsHieC+K0fauWG0JGGOU10re2YQzQ7n4yynphO610jj5vwkfev8uA/ J7+8bhkbVVu5Lr18IZYD2+d50DyvxqLALejjUOa0IDb0qc32XMOusd0/onZTuE62FoyB Kkjw== X-Gm-Message-State: AHPjjUjJaMX2TZAgS9PDm/7QAGx2VIGx2H9zON8roBwRFEGod4AL2WSC nS1Bfy5rn4Fac+9UiCT3ZJDKvw== X-Google-Smtp-Source: AOwi7QAUsQsNZetHNH2M3e8OJbZhKH6QxF0zGvDHr75CUliDVhb7egnHvdZCKr2HsGIo++HUbozstw== X-Received: by 10.99.125.81 with SMTP id m17mr5310171pgn.343.1505992037738; Thu, 21 Sep 2017 04:07:17 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x124sm2090762pfx.56.2017.09.21.04.07.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 04:07:17 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Thu, 21 Sep 2017 18:59:49 +0800 Message-Id: <1505991597-52989-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , guoheyi@huawei.com, waip23@126.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++-------- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++-- 2 files changed, 35 insertions(+), 17 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..e3d3988 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..10d766a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase + + PrivateData->PciRegionBase; + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } }