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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id e87si3442089pfj.381.2018.03.15.00.18.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Mar 2018 00:18:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q9PTTlTx; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DE9532253FB69; Thu, 15 Mar 2018 00:11:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x244.google.com (mail-pg0-x244.google.com [IPv6:2607:f8b0:400e:c05::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D7B5F224E6903 for ; Thu, 15 Mar 2018 00:11:46 -0700 (PDT) Received: by mail-pg0-x244.google.com with SMTP id r26so2438256pgv.13 for ; Thu, 15 Mar 2018 00:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EaiJNvt6MZdZJRjgUvP8Q0ocFLg+9CdNNGlrY/SxfsU=; b=Q9PTTlTxN9Ao3SWmYKmR696GAwWAfqHZu97RZms32q0suZ6PUXMz5P9T5NY4JxdVQm jzWzCVP1DxB/L9RO5jCjjHUMqmAeqgMzpmlg+vTz0HC54fMr2mxPG6UHvPtiEcKzafYb RdFhSRVI3B11D6Xy2AzLspfqKqtI2kwkcY9DQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EaiJNvt6MZdZJRjgUvP8Q0ocFLg+9CdNNGlrY/SxfsU=; b=sq/HK+PDvn+X0c0xniJmuX6DAIIvaVzAb16fLQ2V5ffGe2kChchEADYoVUlvpkkH7o 1B7ny7vEGdKvfrLLUkHhAJFS0VQ4nHtKEMxngqMjP6MPCp/0WYK4eVOo+XFRcEEGlKRW 1TUuMYjxWFy9VtejF1WR83Q+Li0w6ZTajhatrvcuMILGhqcTuqQwD0z5NtKngJiQPGC2 pX9N+mn87xHZMqx76R8Kk8crFEqI/Tc0LAKx//Axzw+cm1uYs3Se2ub4sADipR483H8c rofUeHcXEnm/iQ4I/oUAymKzI4CnBn3Jo+14gGJexjvpPQniSzCtp5QJ1OUvTrpRpbAe 2Nkg== X-Gm-Message-State: AElRT7Hie57meErN9441fg002033hv8HW+R/tbC1zW8sASZyFeBoRtL0 6R88mV8seEMqysYXGfVsAkG5Zo3UAFU= X-Received: by 10.98.200.131 with SMTP id i3mr6924084pfk.40.1521098290114; Thu, 15 Mar 2018 00:18:10 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id i186sm9026113pfg.25.2018.03.15.00.18.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 00:18:09 -0700 (PDT) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 15 Mar 2018 15:17:43 +0800 Message-Id: <1521098263-52823-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521098263-52823-1-git-send-email-heyi.guo@linaro.org> References: <1521098263-52823-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v3 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Heyi Guo , Yi Li , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" If timer interrupt is level sensitive, reloading timer compare register has a side effect of clearing GIC pending status, so a "ISB" is needed to make sure this instruction is executed before enabling CPU IRQ, or else we may get spurious timer interrupts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Acked-by: Marc Zyngier Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Marc Zyngier --- Notes: v3: - Move ISB after enabling timer [Marc] v2: - Use ISB instead of DSB [Marc] - Update commit message accordingly. ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Ard Biesheuvel diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 33d7c922221f..a3202fa056f3 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -338,6 +338,7 @@ TimerInterruptHandler ( // Set next compare value ArmGenericTimerSetCompareVal (CompareValue); ArmGenericTimerEnableTimer (); + ArmInstructionSynchronizationBarrier (); } gBS->RestoreTPL (OriginalTPL);