From patchwork Thu Nov 24 19:56:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Lloyd X-Patchwork-Id: 83989 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp222910qgi; Thu, 24 Nov 2016 11:56:26 -0800 (PST) X-Received: by 10.84.217.216 with SMTP id d24mr8991087plj.10.1480017386390; Thu, 24 Nov 2016 11:56:26 -0800 (PST) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id g15si12151739plm.255.2016.11.24.11.56.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Nov 2016 11:56:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 084C081EFA; Thu, 24 Nov 2016 11:56:23 -0800 (PST) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 71BE281EF1 for ; Thu, 24 Nov 2016 11:56:20 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.35.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id uAOJuHJX021110; Thu, 24 Nov 2016 19:56:17 GMT From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 24 Nov 2016 19:56:11 +0000 Message-Id: <20161124195612.17632-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20161124195612.17632-1-evan.lloyd@arm.com> References: <20161124195612.17632-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 1/2] ArmPlatformPkg: Reformat VE Memory Map code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Evan Lloyd This change is purely cosmetic, with no functional impact, and only exists to isolate cosmetic changes from a functional fix. Some indentation is adjusted. Overlength lines are re-flowed. alignment on = is adjusted as some lines exceeded 80 columns. if statement converted to conditional assignment. Redundant re-calculation of CacheAttributes removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 99 +++++++++----------- 1 file changed, 45 insertions(+), 54 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 115df246796d23081dadcbda94f743bc63233f56..14541183d1eb6916690823d7e04507fc50639f5f 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -24,17 +24,19 @@ #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 // DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED /** Return the Virtual Memory Map of your platform - This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + This Virtual Memory Map is used by MemoryInitPei Module to initialize + the MMU on your platform. - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- - Virtual Memory mapping. This array must be ended by a zero-filled - entry + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR + describing a Physical-to-Virtual Memory + mapping. This array must be ended by a + zero-filled entry. **/ VOID @@ -59,12 +61,12 @@ ArmPlatformGetVirtualMemoryMap ( HasSparseMemory = TRUE; ResourceAttributes = - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED; + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; // Declared the additional DRAM from 2GB to 4GB SparseMemoryBase = 0x0880000000; @@ -81,77 +83,66 @@ ArmPlatformGetVirtualMemoryMap ( SparseMemorySize = 0x0; } - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*) + AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) + * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); if (VirtualMemoryTable == NULL) { - return; + return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = (FeaturePcdGet(PcdCacheEnable)) + ? DDR_ATTRIBUTES_CACHED + : DDR_ATTRIBUTES_UNCACHED; // ReMap (Either NOR Flash or DRAM) VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; - VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; - - if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) { - // Map the NOR Flash as Secure Memory - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; - } else { - VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED; - } - } else { - // DRAM mapping - VirtualMemoryTable[Index].Attributes = CacheAttributes; - } + VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; // DDR VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; - VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; - VirtualMemoryTable[Index].Attributes = CacheAttributes; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; // CPU peripherals. TRM. Manual says not all of them are implemented. VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; - VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // SMB CS0-CS1 - NOR Flash 1 & 2 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; - VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; - VirtualMemoryTable[Index].Attributes = CacheAttributes; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; // SMB CS2 - SRAM VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; - VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; - VirtualMemoryTable[Index].Attributes = CacheAttributes; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; // Peripheral CS2 and CS3 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; - VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase; - VirtualMemoryTable[Index].Length = SparseMemorySize; - VirtualMemoryTable[Index].Attributes = CacheAttributes; + VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase; + VirtualMemoryTable[Index].Length = SparseMemorySize; + VirtualMemoryTable[Index].Attributes = CacheAttributes; } // End of Table VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; *VirtualMemoryMap = VirtualMemoryTable; }