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[198.145.21.10]) by mx.google.com with ESMTPS id r39si8925776pld.493.2017.11.10.06.23.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:23:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kqOc+vm7; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E887B2035D0E3; Fri, 10 Nov 2017 06:18:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 42B4A2035521F for ; Fri, 10 Nov 2017 06:18:48 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id t139so3095995wmt.1 for ; Fri, 10 Nov 2017 06:22:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2+NrkXNjPu2QqN2RvVtFItDj77TGk3/ZimULNsl7cac=; b=kqOc+vm7XQPj/CX8zHdJiV6i0X5r+Tg4SU26PkgpIvxtny13eoeyqn/OxBc6xkd9nE RsdXOtxRdrK32mrXZXaSK0RWDbX/mHFOnaFRDOQzvaNNxJ4zKDGoJAHjS5ledLCjHVK+ zCYBo2q5KuM63PFoI90NjMK/LRK0pNiqUiXyY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2+NrkXNjPu2QqN2RvVtFItDj77TGk3/ZimULNsl7cac=; b=PtB6J9IimHM8iyzKQ+CRaNyOeAwvOKT7fPS3d76Mu8zFSYSMRitbLGfWyZh8Erwj/x 9BDKoqFiREsDHdmeW2cBDWBVWdOXzdyvbJubwg+IKplONxc/qabSNgnOkabMacvgfFJu HzkXE2fboqL6Q875wmV5EF2XAj6fAwl6Mm0BJovrgfHKwCB8PY3WiH5t8ykqECn8s+59 12JSd9Wdr9e2zasDp9rWuE0Dx6ngwJzjdp3FpQ6NNGD1WCqjG2SLMUL0wY0x1gmX9o66 Sxy6FIE9NL2JginbnsTPoNJORrSkIqMpLYm3WU35PyTo/Hyc3WPXKZ4ED2PRxwo42pmf SdVA== X-Gm-Message-State: AJaThX5JVDGeAJ6XsInc9SSrCUmm71CTzZfK0NCwwZREfyA2L2Egkeqt AxCO6onoTKG6JRnyVuW7JvO0J4+fTF0= X-Received: by 10.28.139.144 with SMTP id n138mr392362wmd.78.1510323769712; Fri, 10 Nov 2017 06:22:49 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.22.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:48 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:21:17 +0000 Message-Id: <20171110142127.12018-25-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 24/34] Silicon/SynQuacer: add description of GPIO block to device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a description of the SoCs GPIO controller as well as a description of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the evaluation board as well as the Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- v4: replace pin 'hogs' with descriptive names of all the pins, including PD8 which has been repurposed as the power button on v0.2 of the schematics Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 11 +++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 12 ++++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 11 +++++++++++ 3 files changed, 34 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 9e0acd593311..6ae7d5f300b6 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -19,3 +19,14 @@ model = "Socionext Developer Box"; compatible = "socionext,developer-box", "socionext,synquacer"; }; + +&gpio { + gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index f89e722219ad..966952b9a224 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -21,6 +21,9 @@ #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + / { #address-cells = <2>; #size-cells = <2>; @@ -511,4 +514,13 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; }; + + gpio: gpio@51000000 { + compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; + reg = <0x0 0x51000000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk_apb>; + base = <0>; + }; }; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index cda72fdf2f99..7de7db182b27 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -19,3 +19,14 @@ model = "SynQuacer Evaluation Board"; compatible = "socionext,synquacer-eval-board", "socionext,synquacer"; }; + +&gpio { + gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PEC-PD8", "PEC-PD9", "PEC-PD10", "PEC-PD11", + "NC", "NC", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY_P2_2", "PHY_P1_2", "NC", "NC", + "NC", "NC", "NC", "NC", + "NC", "NC", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +};