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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id r84si3552692pfa.352.2017.11.17.11.04.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=AlXfDjof; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9F8F62035BB28; Fri, 17 Nov 2017 11:00:29 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0182A21B00DD0 for ; Fri, 17 Nov 2017 11:00:27 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id o88so2941644wrb.6 for ; Fri, 17 Nov 2017 11:04:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RbK5ZrtY+zvajrdhrWlMkw2NFZyuNpDulwRrcwjffcA=; b=AlXfDjofEt4MCX7NdYXmujr2Hu85CXPW6e7RSrVGTc73bR/h1192EiXf6MzYjZyT9P LaYwGbDN0D7UMZEv2je5nVVNs4D7giFmn+ka01pDg8KFz2oca0jl5ASeoKZSg/t5UEyk gnT3aFnCLf3VRD4AET7VtkpoJ8rEJb1oG25BM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RbK5ZrtY+zvajrdhrWlMkw2NFZyuNpDulwRrcwjffcA=; b=riQwYVbUz8LwlSdBbInyVWuisOeGlYJrkd5TxrtZu/VQQJoy33s5PpVErbyvv+/WJ2 Ws7w4UqUeClmJTLGiIPkNL2DpLMOem55HHnDgM+ewCh4kRz3Ytx4xvLxMo8h8dqwfaRz tEdo+9e8rhTT9O31pk6U+hBTIlMrm1YfWS0XTgBzyq0K6jq0S6R2JpaIlMzopte7by7K a0nfvyzzVlNp0krXSTaEuH8CwpfCi1c7kzHnl3ugG9EOi4vnRGpl1hiNyYhPHhLCOZEq to94lP/xNQm9Cidls8CGWC/vUpS9FpbsXFz1bRn5Y8TsLtWbcjcNEO/2ZISCIM+o2/VX OIJg== X-Gm-Message-State: AJaThX7Oq0XTgAzLk5WyL0298p0v8xd2DT+rWAFfLBF2t8B4YxhTLlxd KR27sfUjZ5qdEbdU/IfXD3ZVJI4VqXA= X-Received: by 10.223.160.184 with SMTP id m53mr5685063wrm.126.1510945477186; Fri, 17 Nov 2017 11:04:37 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id c54sm7139022wra.84.2017.11.17.11.04.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:36 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 17 Nov 2017 19:04:18 +0000 Message-Id: <20171117190423.19511-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171117190423.19511-1-ard.biesheuvel@linaro.org> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 1/6] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Ordinary computers typically have a physical switch or jumper on the board that allows non-volatile settings to be cleared. Let's implement the same using DIP switch #1 on block #3, and clear the EFI variable store if it is set to ON at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v5: use MAX_UINT8 as 'not implemented' GPIO index Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 4 +++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 1 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 4 +++ Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 1 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 30 +++++++++++++++++++- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 ++++ Silicon/Socionext/SynQuacer/SynQuacer.dec | 3 ++ 7 files changed, 48 insertions(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index b73e88c5f29b..6c084efa9fb6 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -381,6 +381,9 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -418,6 +421,7 @@ [Components.common] MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 34100bb63da4..6cc523fac4f3 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -258,6 +258,7 @@ [FV.FVMAIN_COMPACT] INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index dd1469decc5d..c8a9f39cd1ae 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -369,6 +369,9 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x08420000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -406,6 +409,7 @@ [Components.common] MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 365085c8f243..4577bd316a1f 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -248,6 +248,7 @@ [FV.FVMAIN_COMPACT] INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c index 358dd5a91f08..401cf3c81273 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -21,8 +21,11 @@ #include #include #include +#include #include +#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED 0xff + STATIC CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); @@ -103,10 +106,35 @@ PlatformPeim ( VOID ) { - EFI_STATUS Status; + EMBEDDED_GPIO_PPI *Gpio; + EFI_STATUS Status; + UINTN Value; + UINT8 Pin; ASSERT (mDramInfo->NumRegions > 0); + Pin = FixedPcdGet8 (PcdClearSettingsGpioPin); + if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) { + Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, + (VOID **)&Gpio); + ASSERT_EFI_ERROR (Status); + + Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n", + __FUNCTION__, Status)); + } else { + Status = Gpio->Get (Gpio, Pin, &Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n", + __FUNCTION__, Status)); + } else if (Value > 0) { + DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); + PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); + } + } + } + // // Record the first region into PcdSystemMemoryBase and PcdSystemMemorySize. // This is the region we will use for UEFI itself. diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf index 70eb715d44e3..a6501fb205e1 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf @@ -25,6 +25,7 @@ [Sources] [Packages] ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -40,11 +41,16 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdFvSize + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin gSynQuacerTokenSpaceGuid.PcdDramInfoBase [Ppis] + gEdkiiEmbeddedGpioPpiGuid ## CONSUMES gSynQuacerDramInfoPpiGuid ## PRODUCES [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + gEdkiiEmbeddedGpioPpiGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 1a683b81521b..cb3f836f5922 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -30,3 +30,6 @@ [PcdsFixedAtBuild] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0|UINT32|0x00000002 gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress|0|UINT8|0x00000003 + + # GPIO pin index [0 .. 31] or 0xFF for not implemented + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004