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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id f10si3233521pln.509.2017.11.17.11.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E7lROhjk; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE1EB21B00DF2; Fri, 17 Nov 2017 11:00:39 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 54EBD21B00DEF for ; Fri, 17 Nov 2017 11:00:38 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id v186so8321931wma.2 for ; Fri, 17 Nov 2017 11:04:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ebD7qN2esH9cZIfIc0nxuH3nRYoC4lsuoHiILGSveg=; b=E7lROhjkR9kyjHFxroLx8Ge6JsNngDP7ymqfwV0nltr3qh30Zbncp86V3aOR5GUDzG +KZGRWOw7AmTcmoTVsCRP9DTBdkAVdryV8JgP2RE9yluHEf5eUXX4dM5534hSRxistF/ 4eGJLVeCPqdkxa4iYKTFw6V73GhC6Uyw1stKA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ebD7qN2esH9cZIfIc0nxuH3nRYoC4lsuoHiILGSveg=; b=WDO4ye89xanVtYO0ANkUvq8ku/PZ6ZWkDf607o3vcjPM3TxpYQmZMpYJ11zVHvm7dV BCla1l2EQiC7rRb4LcxRFdfwNagS5DD44XimEAPAYLpHEo2S537uzsry/6DTQkFW3xeM Llm3MKEHS9DNPN0lKcNuj1B7MBm1Y2l+CbkH5DSEzyTY27kxTx3y0VaRYa1YMGOvG1Mr zYxoErRo0OfqgaLV03QV5PMOoEFdaqfirD02PQdjSSjdl9dgv3O9umSkYkaMlqi2brVt vBCO3ILxQaQmjfuPhv6/zDDoHR5eDnLfcVWhJqFs1pXCrkoZhNjrnkbzkp/yAM57BiFN xhWQ== X-Gm-Message-State: AJaThX50Xv+ac2JzdlvtnW0bgvBhUGhg8vCPe7wR032krFw9JBX2qnma 5KKe+tt0IJ/k9DFCUiY6iLPWqC11OFA= X-Received: by 10.28.144.140 with SMTP id s134mr5277626wmd.82.1510945487647; Fri, 17 Nov 2017 11:04:47 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id c54sm7139022wra.84.2017.11.17.11.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:46 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 17 Nov 2017 19:04:22 +0000 Message-Id: <20171117190423.19511-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171117190423.19511-1-ard.biesheuvel@linaro.org> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 5/6] Platform/DeveloperBox: wire up RTC support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add the drivers, library resolutions and PCD settings to enable RTC support on DeveloperBox. Also, update PlatformDxe to register the non-discoverable device handles for both I2C controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 8 ++- Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 5 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 76 +++++++++++++++++--- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 6 +- Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 8 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 ++ 6 files changed, 96 insertions(+), 11 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 6c084efa9fb6..5d3dec8ba3a8 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -446,8 +446,7 @@ [Components.common] MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { - ## TODO - RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + RealTimeClockLib|Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf } MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf @@ -623,3 +622,8 @@ [Components.common] MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + + # + # I2C + # + Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 6cc523fac4f3..8443986fc3e7 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -229,6 +229,11 @@ [FV.FvMain] SECTION UI = "Pkcs7TestRoot" } + # + # I2C + # + INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf + [FV.FVMAIN_COMPACT] FvAlignment = 16 BlockSize = 0x10000 diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 9639ffffc09f..070e6be92edd 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -62,27 +62,61 @@ STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = { } }; +STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mI2c0Desc[] = { + { + ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len + ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType + 0, // GenFlag + 0, // SpecificFlag + 32, // AddrSpaceGranularity + SYNQUACER_I2C0_BASE, // AddrRangeMin + SYNQUACER_I2C0_BASE + SYNQUACER_I2C0_SIZE - 1, // AddrRangeMax + 0, // AddrTranslationOffset + SYNQUACER_I2C0_SIZE, // AddrLen + }, { + ACPI_END_TAG_DESCRIPTOR // Desc + } +}; + +STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mI2c1Desc[] = { + { + ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len + ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType + 0, // GenFlag + 0, // SpecificFlag + 32, // AddrSpaceGranularity + SYNQUACER_I2C1_BASE, // AddrRangeMin + SYNQUACER_I2C1_BASE + SYNQUACER_I2C1_SIZE - 1, // AddrRangeMax + 0, // AddrTranslationOffset + SYNQUACER_I2C1_SIZE, // AddrLen + }, { + ACPI_END_TAG_DESCRIPTOR // Desc + } +}; + STATIC EFI_STATUS -RegisterNetsec ( - VOID +RegisterDevice ( + IN EFI_GUID *TypeGuid, + IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc, + OUT EFI_HANDLE *Handle ) { NON_DISCOVERABLE_DEVICE *Device; EFI_STATUS Status; - EFI_HANDLE Handle; Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device)); if (Device == NULL) { return EFI_OUT_OF_RESOURCES; } - Device->Type = &gNetsecNonDiscoverableDeviceGuid; + Device->Type = TypeGuid; Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent; - Device->Resources = mNetsecDesc; + Device->Resources = Desc; - Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + Status = gBS->InstallMultipleProtocolInterfaces (Handle, &gEdkiiNonDiscoverableDeviceProtocolGuid, Device, NULL); if (EFI_ERROR (Status)) { @@ -106,6 +140,7 @@ PlatformDxeEntryPoint ( EFI_STATUS Status; VOID *Dtb; UINTN DtbSize; + EFI_HANDLE Handle; Dtb = NULL; Status = DtPlatformLoadDtb (&Dtb, &DtbSize); @@ -118,5 +153,30 @@ PlatformDxeEntryPoint ( Status)); } - return RegisterNetsec (); + Handle = NULL; + Status = RegisterDevice (&gNetsecNonDiscoverableDeviceGuid, mNetsecDesc, + &Handle); + ASSERT_EFI_ERROR (Status); + + Handle = NULL; + Status = RegisterDevice (&gSynQuacerNonDiscoverableRuntimeI2cMasterGuid, + mI2c0Desc, &Handle); + ASSERT_EFI_ERROR (Status); + + // + // Install the PCF8563 I2C Master protocol on this handle so the RTC driver + // can identify it as the I2C master it can invoke directly, rather than + // through the I2C driver stack (which cannot be used at runtime) + // + Status = gBS->InstallProtocolInterface (&Handle, + &gPcf8563RealTimeClockLibI2cMasterProtolGuid, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + + Handle = NULL; + Status = RegisterDevice (&gSynQuacerNonDiscoverableI2cMasterGuid, mI2c1Desc, + &Handle); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 25e6248f1c61..478e0c7d33e9 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -29,6 +29,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -43,9 +44,12 @@ [LibraryClasses] [Guids] gFdtTableGuid gNetsecNonDiscoverableDeviceGuid + gSynQuacerNonDiscoverableI2cMasterGuid + gSynQuacerNonDiscoverableRuntimeI2cMasterGuid [Protocols] - gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index f29a35809bac..3c7bd58866cc 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -42,6 +42,14 @@ #define SYNQUACER_GPIO_BASE 0x51000000 #define SYNQUACER_GPIO_SIZE SIZE_4KB +// I2C0 block +#define SYNQUACER_I2C0_BASE 0x51200000 +#define SYNQUACER_I2C0_SIZE SIZE_4KB + +// I2C1 block +#define SYNQUACER_I2C1_BASE 0x51210000 +#define SYNQUACER_I2C1_SIZE SIZE_4KB + // eMMC(SDH30) #define SYNQUACER_EMMC_BASE 0x52300000 #define SYNQUACER_EMMC_BASE_SZ SIZE_4KB diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index 0c5df14482a2..a640b3e0c0d1 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -82,6 +82,10 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { ARM_CACHED_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase), SYNQUACER_EEPROM_BASE_SZ), + // SynQuacer I2C + ARM_DEVICE_REGION (SYNQUACER_I2C0_BASE, SYNQUACER_I2C0_SIZE), + ARM_DEVICE_REGION (SYNQUACER_I2C1_BASE, SYNQUACER_I2C1_SIZE), + // SynQuacer NETSEC ARM_DEVICE_REGION (SYNQUACER_NETSEC1_BASE, SYNQUACER_NETSEC1_BASE_SZ),