deleted file mode 100644
@@ -1,285 +0,0 @@
-/**
-
- Copyright (c) 2012, ARM Ltd. All rights reserved.
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Library/ArmPlatformSysConfigLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/LcdPlatformLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/EdidDiscovered.h>
-#include <Protocol/EdidActive.h>
-
-#include <ArmPlatform.h>
-
-typedef struct {
- UINT32 Mode;
- UINT32 HorizontalResolution;
- UINT32 VerticalResolution;
- LCD_BPP Bpp;
- UINT32 OscFreq;
-
- // These are used by HDLCD
- UINT32 HSync;
- UINT32 HBackPorch;
- UINT32 HFrontPorch;
- UINT32 VSync;
- UINT32 VBackPorch;
- UINT32 VFrontPorch;
-} LCD_RESOLUTION;
-
-
-LCD_RESOLUTION mResolutions[] = {
- { // Mode 0 : VGA : 640 x 480 x 24 bpp
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
- },
- { // Mode 1 : SVGA : 800 x 600 x 24 bpp
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
- },
- { // Mode 2 : XGA : 1024 x 768 x 24 bpp
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- },
- { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
- SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
- SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
- SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
- },
- { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
- UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
- UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
- UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
- },
- { // Mode 5 : HD : 1920 x 1080 x 24 bpp
- HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
- HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
- HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
- }
-};
-
-EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
- 0,
- NULL
-};
-
-EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
- 0,
- NULL
-};
-
-EFI_STATUS
-LcdPlatformInitializeDisplay (
- IN EFI_HANDLE Handle
- )
-{
- EFI_STATUS Status;
-
- // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
- // Install the EDID Protocols
- Status = gBS->InstallMultipleProtocolInterfaces (
- &Handle,
- &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
- &gEfiEdidActiveProtocolGuid, &mEdidActive,
- NULL
- );
-
- return Status;
-}
-
-EFI_STATUS
-LcdPlatformGetVram (
- OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
- OUT UINTN* VramSize
- )
-{
- EFI_STATUS Status;
- EFI_ALLOCATE_TYPE AllocationType;
-
- // Set the vram size
- *VramSize = LCD_VRAM_SIZE;
-
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;
-
- // Allocate the VRAM from the DRAM so that nobody else uses it.
- if (*VramBaseAddress == 0) {
- AllocationType = AllocateAnyPages;
- } else {
- AllocationType = AllocateAddress;
- }
- Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
- // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.
- Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,
- EFI_MEMORY_WC);
- ASSERT_EFI_ERROR(Status);
- if (EFI_ERROR(Status)) {
- gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize));
- return Status;
- }
-
- return EFI_SUCCESS;
-}
-
-UINT32
-LcdPlatformGetMaxMode (
- VOID
- )
-{
- //
- // The following line will report correctly the total number of graphics modes
- // that could be supported by the graphics driver:
- //
- return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));
-}
-
-EFI_STATUS
-LcdPlatformSetMode (
- IN UINT32 ModeNumber
- )
-{
- EFI_STATUS Status;
-
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- // Set the video mode oscillator
- do {
- Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);
- } while (Status == EFI_TIMEOUT);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
-
- // Set the DVI into the new mode
- do {
- Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
- } while (Status == EFI_TIMEOUT);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
-
- // Set the multiplexer
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
-
- return Status;
-}
-
-EFI_STATUS
-LcdPlatformQueryMode (
- IN UINT32 ModeNumber,
- OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- Info->Version = 0;
- Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
- Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
- Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
-
- switch (mResolutions[ModeNumber].Bpp) {
- case LCD_BITS_PER_PIXEL_24:
- Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
- Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
- Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
- Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
- Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
- break;
-
- case LCD_BITS_PER_PIXEL_16_555:
- case LCD_BITS_PER_PIXEL_16_565:
- case LCD_BITS_PER_PIXEL_12_444:
- case LCD_BITS_PER_PIXEL_8:
- case LCD_BITS_PER_PIXEL_4:
- case LCD_BITS_PER_PIXEL_2:
- case LCD_BITS_PER_PIXEL_1:
- default:
- // These are not supported
- ASSERT(FALSE);
- break;
- }
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdPlatformGetTimings (
- IN UINT32 ModeNumber,
- OUT UINT32* HRes,
- OUT UINT32* HSync,
- OUT UINT32* HBackPorch,
- OUT UINT32* HFrontPorch,
- OUT UINT32* VRes,
- OUT UINT32* VSync,
- OUT UINT32* VBackPorch,
- OUT UINT32* VFrontPorch
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- *HRes = mResolutions[ModeNumber].HorizontalResolution;
- *HSync = mResolutions[ModeNumber].HSync;
- *HBackPorch = mResolutions[ModeNumber].HBackPorch;
- *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
- *VRes = mResolutions[ModeNumber].VerticalResolution;
- *VSync = mResolutions[ModeNumber].VSync;
- *VBackPorch = mResolutions[ModeNumber].VBackPorch;
- *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdPlatformGetBpp (
- IN UINT32 ModeNumber,
- OUT LCD_BPP * Bpp
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- *Bpp = mResolutions[ModeNumber].Bpp;
-
- return EFI_SUCCESS;
-}
deleted file mode 100644
@@ -1,45 +0,0 @@
-#/** @file
-#
-# Component description file for HdLcdArmLib module
-#
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = HdLcdArmVExpress
- FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = LcdPlatformLib
-
-[Sources.common]
-
-HdLcdArmVExpress.c
-
-[Packages]
- MdePkg/MdePkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
-
-[LibraryClasses]
- ArmPlatformSysConfigLib
- BaseLib
- DxeServicesTableLib
-
-[Protocols]
- gEfiEdidDiscoveredProtocolGuid # Produced
- gEfiEdidActiveProtocolGuid # Produced
-
-[Pcd]
- gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
- gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId
deleted file mode 100644
@@ -1,370 +0,0 @@
-/** @file
-
- Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Library/ArmPlatformSysConfigLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/LcdPlatformLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/EdidDiscovered.h>
-#include <Protocol/EdidActive.h>
-
-#include <ArmPlatform.h>
-
-typedef struct {
- UINT32 Mode;
- UINT32 HorizontalResolution;
- UINT32 VerticalResolution;
- LCD_BPP Bpp;
- UINT32 OscFreq;
-
- UINT32 HSync;
- UINT32 HBackPorch;
- UINT32 HFrontPorch;
- UINT32 VSync;
- UINT32 VBackPorch;
- UINT32 VFrontPorch;
-} LCD_RESOLUTION;
-
-
-LCD_RESOLUTION mResolutions[] = {
- { // Mode 0 : VGA : 640 x 480 x 24 bpp
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
- },
- { // Mode 1 : SVGA : 800 x 600 x 24 bpp
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
- },
- { // Mode 2 : XGA : 1024 x 768 x 24 bpp
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- },
- { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
- SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
- SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
- SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
- },
- { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
- UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
- UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
- UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
- },
- { // Mode 5 : HD : 1920 x 1080 x 24 bpp
- HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
- HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
- HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
- },
- { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
- },
- { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
- },
- { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- },
- { // Mode 9 : VGA : 640 x 480 x 15 bpp
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
- },
- { // Mode 10 : SVGA : 800 x 600 x 15 bpp
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
- },
- { // Mode 11 : XGA : 1024 x 768 x 15 bpp
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- },
- { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- },
- { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)
- VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,
- VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
- VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
- },
- { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)
- SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,
- SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
- SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
- },
- { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)
- XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,
- XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
- XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
- }
-};
-
-EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
- 0,
- NULL
-};
-
-EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
- 0,
- NULL
-};
-
-
-EFI_STATUS
-LcdPlatformInitializeDisplay (
- IN EFI_HANDLE Handle
- )
-{
- EFI_STATUS Status;
-
- // Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);
- if (!EFI_ERROR(Status)) {
- // Install the EDID Protocols
- Status = gBS->InstallMultipleProtocolInterfaces(
- &Handle,
- &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
- &gEfiEdidActiveProtocolGuid, &mEdidActive,
- NULL
- );
- }
-
- return Status;
-}
-
-EFI_STATUS
-LcdPlatformGetVram (
- OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
- OUT UINTN* VramSize
- )
-{
- EFI_STATUS Status;
-
- Status = EFI_SUCCESS;
-
- // Is it on the motherboard or on the daughterboard?
- switch(PL111_CLCD_SITE) {
-
- case ARM_VE_MOTHERBOARD_SITE:
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;
- *VramSize = LCD_VRAM_SIZE;
- break;
-
- case ARM_VE_DAUGHTERBOARD_1_SITE:
- *VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;
- *VramSize = LCD_VRAM_SIZE;
-
- // Allocate the VRAM from the DRAM so that nobody else uses it.
- Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
- // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.
- Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,
- EFI_MEMORY_WC);
- ASSERT_EFI_ERROR(Status);
- if (EFI_ERROR(Status)) {
- gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize));
- return Status;
- }
- break;
-
- default:
- // Unsupported site
- Status = EFI_UNSUPPORTED;
- break;
- }
-
- return Status;
-}
-
-UINT32
-LcdPlatformGetMaxMode (
- VOID
- )
-{
- // The following line will report correctly the total number of graphics modes
- // supported by the PL111CLCD.
- //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;
-
- // However, on some platforms it is desirable to ignore some graphics modes.
- // This could be because the specific implementation of PL111 has certain limitations.
-
- // Set the maximum mode allowed
- return (PcdGet32(PcdPL111LcdMaxMode));
-}
-
-EFI_STATUS
-LcdPlatformSetMode (
- IN UINT32 ModeNumber
- )
-{
- EFI_STATUS Status;
- UINT32 LcdSite;
- UINT32 OscillatorId;
- SYS_CONFIG_FUNCTION Function;
- UINT32 SysId;
-
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- LcdSite = PL111_CLCD_SITE;
-
- switch(LcdSite) {
- case ARM_VE_MOTHERBOARD_SITE:
- Function = SYS_CFG_OSC;
- OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;
- break;
- case ARM_VE_DAUGHTERBOARD_1_SITE:
- Function = SYS_CFG_OSC_SITE1;
- OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);
- break;
- default:
- return EFI_UNSUPPORTED;
- }
-
- // Set the video mode oscillator
- Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
-
- // The FVP foundation model does not have an LCD.
- // On the FVP models the GIC variant in encoded in bits [15:12].
- // Note: The DVI Mode is not modelled by RTSM or FVP models.
- SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
- if (SysId != ARM_RTSM_SYS_ID) {
- // Take out the FVP GIC variant to reduce the permutations.
- SysId &= ~ARM_FVP_SYS_ID_VARIANT_MASK;
- if (SysId != ARM_FVP_BASE_BOARD_SYS_ID) {
- // Set the DVI into the new mode
- Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
- }
- }
-
- // Set the multiplexer
- Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);
- if (EFI_ERROR(Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
-
- return Status;
-}
-
-EFI_STATUS
-LcdPlatformQueryMode (
- IN UINT32 ModeNumber,
- OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- Info->Version = 0;
- Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
- Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
- Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
-
- switch (mResolutions[ModeNumber].Bpp) {
- case LCD_BITS_PER_PIXEL_24:
- Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
- Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
- Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
- Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
- Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
- break;
-
- case LCD_BITS_PER_PIXEL_16_555:
- case LCD_BITS_PER_PIXEL_16_565:
- case LCD_BITS_PER_PIXEL_12_444:
- case LCD_BITS_PER_PIXEL_8:
- case LCD_BITS_PER_PIXEL_4:
- case LCD_BITS_PER_PIXEL_2:
- case LCD_BITS_PER_PIXEL_1:
- default:
- // These are not supported
- ASSERT(FALSE);
- break;
- }
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdPlatformGetTimings (
- IN UINT32 ModeNumber,
- OUT UINT32* HRes,
- OUT UINT32* HSync,
- OUT UINT32* HBackPorch,
- OUT UINT32* HFrontPorch,
- OUT UINT32* VRes,
- OUT UINT32* VSync,
- OUT UINT32* VBackPorch,
- OUT UINT32* VFrontPorch
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- *HRes = mResolutions[ModeNumber].HorizontalResolution;
- *HSync = mResolutions[ModeNumber].HSync;
- *HBackPorch = mResolutions[ModeNumber].HBackPorch;
- *HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
- *VRes = mResolutions[ModeNumber].VerticalResolution;
- *VSync = mResolutions[ModeNumber].VSync;
- *VBackPorch = mResolutions[ModeNumber].VBackPorch;
- *VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdPlatformGetBpp (
- IN UINT32 ModeNumber,
- OUT LCD_BPP * Bpp
- )
-{
- if (ModeNumber >= LcdPlatformGetMaxMode ()) {
- return EFI_INVALID_PARAMETER;
- }
-
- *Bpp = mResolutions[ModeNumber].Bpp;
-
- return EFI_SUCCESS;
-}
deleted file mode 100644
@@ -1,44 +0,0 @@
-#/** @file
-#
-# Component description file for ArmVeGraphicsDxe module
-#
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PL111LcdArmVExpressLib
- FILE_GUID = b7f06f20-496f-11e0-a8e8-0002a5d5c51b
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = LcdPlatformLib
-
-[Sources.common]
- PL111LcdArmVExpress.c
-
-[Packages]
- MdePkg/MdePkg.dec
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmPlatformSysConfigLib
- BaseLib
- DxeServicesTableLib
-
-[Protocols]
- gEfiEdidDiscoveredProtocolGuid # Produced
- gEfiEdidActiveProtocolGuid # Produced
-
-[Pcd]
- gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
- gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId
deleted file mode 100644
@@ -1,133 +0,0 @@
-/** @file Lcd.c
-
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/LcdPlatformLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-
-#include <Drivers/HdLcd.h>
-
-#include "LcdGraphicsOutputDxe.h"
-
-/**********************************************************************
- *
- * This file contains all the bits of the Lcd that are
- * platform independent.
- *
- **********************************************************************/
-
-EFI_STATUS
-LcdInitialize (
- IN EFI_PHYSICAL_ADDRESS VramBaseAddress
- )
-{
- // Disable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
-
- // Disable all interrupts
- MmioWrite32(HDLCD_REG_INT_MASK, 0);
-
- // Define start of the VRAM. This never changes for any graphics mode
- MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
-
- // Setup various registers that never change
- MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
- MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
- MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
- MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
- MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
- MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdSetMode (
- IN UINT32 ModeNumber
- )
-{
- EFI_STATUS Status;
- UINT32 HRes;
- UINT32 HSync;
- UINT32 HBackPorch;
- UINT32 HFrontPorch;
- UINT32 VRes;
- UINT32 VSync;
- UINT32 VBackPorch;
- UINT32 VFrontPorch;
- UINT32 BytesPerPixel;
- LCD_BPP LcdBpp;
-
-
- // Set the video mode timings and other relevant information
- Status = LcdPlatformGetTimings (ModeNumber,
- &HRes,&HSync,&HBackPorch,&HFrontPorch,
- &VRes,&VSync,&VBackPorch,&VFrontPorch);
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
- return EFI_DEVICE_ERROR;
- }
-
- Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
- return EFI_DEVICE_ERROR;
- }
-
- BytesPerPixel = GetBytesPerPixel(LcdBpp);
-
- // Disable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
-
- // Update the frame buffer information with the new settings
- MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
- MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
- MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);
-
- // Set the vertical timing information
- MmioWrite32(HDLCD_REG_V_SYNC, VSync);
- MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);
- MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);
- MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
-
- // Set the horizontal timing information
- MmioWrite32(HDLCD_REG_H_SYNC, HSync);
- MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);
- MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);
- MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
-
- // Enable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);
-
- return EFI_SUCCESS;
-}
-
-VOID
-LcdShutdown (
- VOID
- )
-{
- // Disable the controller
- MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
-}
-
-EFI_STATUS
-LcdIdentify (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
deleted file mode 100644
@@ -1,63 +0,0 @@
-#/** @file
-#
-# Component description file for HDLCD module
-#
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = HdLcdGraphicsDxe
- FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = LcdGraphicsOutputDxeInitialize
-
-[Sources.common]
- LcdGraphicsOutputDxe.c
- LcdGraphicsOutputBlt.c
- HdLcd.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmLib
- UefiLib
- BaseLib
- DebugLib
- TimerLib
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- IoLib
- BaseMemoryLib
- LcdPlatformLib
-
-[Protocols]
- gEfiDevicePathProtocolGuid
- gEfiGraphicsOutputProtocolGuid # Produced
- gEfiEdidDiscoveredProtocolGuid # Produced
- gEfiEdidActiveProtocolGuid # Produced
- gEfiEdidOverrideProtocolGuid # Produced
-
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase
-
-[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices
-
-[Depex]
- gEfiCpuArchProtocolGuid
deleted file mode 100644
@@ -1,126 +0,0 @@
-/** @file PL111Lcd.c
-
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-
-#include <Drivers/PL111Lcd.h>
-
-#include "LcdGraphicsOutputDxe.h"
-
-/**********************************************************************
- *
- * This file contains all the bits of the PL111 that are
- * platform independent.
- *
- **********************************************************************/
-
-EFI_STATUS
-LcdIdentify (
- VOID
- )
-{
- DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n",
- PL111_REG_CLCD_PERIPH_ID_0));
-
- // Check if this is a PL111
- if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&
- MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&
- (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&
- MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {
- return EFI_SUCCESS;
- }
- return EFI_NOT_FOUND;
-}
-
-EFI_STATUS
-LcdInitialize (
- IN EFI_PHYSICAL_ADDRESS VramBaseAddress
- )
-{
- // Define start of the VRAM. This never changes for any graphics mode
- MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);
- MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
-
- // Disable all interrupts from the PL111
- MmioWrite32(PL111_REG_LCD_IMSC, 0);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdSetMode (
- IN UINT32 ModeNumber
- )
-{
- EFI_STATUS Status;
- UINT32 HRes;
- UINT32 HSync;
- UINT32 HBackPorch;
- UINT32 HFrontPorch;
- UINT32 VRes;
- UINT32 VSync;
- UINT32 VBackPorch;
- UINT32 VFrontPorch;
- UINT32 LcdControl;
- LCD_BPP LcdBpp;
-
- // Set the video mode timings and other relevant information
- Status = LcdPlatformGetTimings (ModeNumber,
- &HRes,&HSync,&HBackPorch,&HFrontPorch,
- &VRes,&VSync,&VBackPorch,&VFrontPorch);
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
- return EFI_DEVICE_ERROR;
- }
-
- Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
- return EFI_DEVICE_ERROR;
- }
-
- // Disable the CLCD_LcdEn bit
- LcdControl = MmioRead32( PL111_REG_LCD_CONTROL);
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1);
-
- // Set Timings
- MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes));
- MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes));
- MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes));
- MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
-
- // PL111_REG_LCD_CONTROL
- LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
-
- // Turn on power to the LCD Panel
- LcdControl |= PL111_CTRL_LCD_PWR;
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
-
- return EFI_SUCCESS;
-}
-
-VOID
-LcdShutdown (
- VOID
- )
-{
- // Disable the controller
- MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
-}
deleted file mode 100644
@@ -1,59 +0,0 @@
-#/** @file
-#
-# Component description file for PL111LcdGraphicsOutputDxe module
-#
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PL111LcdGraphicsDxe
- FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = LcdGraphicsOutputDxeInitialize
-
-[Sources.common]
- LcdGraphicsOutputDxe.c
- LcdGraphicsOutputBlt.c
- PL111Lcd.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmLib
- UefiLib
- BaseLib
- DebugLib
- TimerLib
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- IoLib
- BaseMemoryLib
- LcdPlatformLib
-
-[Protocols]
- gEfiDevicePathProtocolGuid
- gEfiGraphicsOutputProtocolGuid
-
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdPL111LcdBase
-
-[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices
-
-[Depex]
- gEfiCpuArchProtocolGuid
deleted file mode 100644
@@ -1,89 +0,0 @@
-/** @file HDLcd.h
-
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- **/
-
-#ifndef _HDLCD_H_
-#define _HDLCD_H_
-
-//
-// HDLCD Controller Register Offsets
-//
-
-#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
-#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
-#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
-#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
-#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
-#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
-#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
-#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
-#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
-#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
-#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
-#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
-#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
-#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
-#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
-#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
-#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
-#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
-#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
-#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
-#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
-#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
-#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
-#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
-
-
-//
-// HDLCD Values of registers
-//
-
-// HDLCD Interrupt mask, clear and status register
-#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
-#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
-#define HDLCD_SYNC BIT2 /* Vertical sync */
-#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
-
-// CLCD_CONTROL Control register
-#define HDLCD_DISABLE 0
-#define HDLCD_ENABLE BIT0
-
-// Bus Options
-#define HDLCD_BURST_1 BIT0
-#define HDLCD_BURST_2 BIT1
-#define HDLCD_BURST_4 BIT2
-#define HDLCD_BURST_8 BIT3
-#define HDLCD_BURST_16 BIT4
-
-// Polarities - HIGH
-#define HDLCD_VSYNC_HIGH BIT0
-#define HDLCD_HSYNC_HIGH BIT1
-#define HDLCD_DATEN_HIGH BIT2
-#define HDLCD_DATA_HIGH BIT3
-#define HDLCD_PXCLK_HIGH BIT4
-// Polarities - LOW (for completion and for ease of understanding the hardware settings)
-#define HDLCD_VSYNC_LOW 0
-#define HDLCD_HSYNC_LOW 0
-#define HDLCD_DATEN_LOW 0
-#define HDLCD_DATA_LOW 0
-#define HDLCD_PXCLK_LOW 0
-
-// Pixel Format
-#define HDLCD_LITTLE_ENDIAN (0 << 31)
-#define HDLCD_BIG_ENDIAN (1 << 31)
-
-// Number of bytes per pixel
-#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
-
-#endif /* _HDLCD_H_ */
deleted file mode 100644
@@ -1,149 +0,0 @@
-/** @file PL111Lcd.h
-
- Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- **/
-
-#ifndef _PL111LCD_H__
-#define _PL111LCD_H__
-
-/**********************************************************************
- *
- * This header file contains all the bits of the PL111 that are
- * platform independent.
- *
- **********************************************************************/
-
-// Controller Register Offsets
-#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
-#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
-#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
-#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
-#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
-#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
-#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
-#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
-#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
-#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
-#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
-#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
-#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
-#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
-
-// Identification Register Offsets
-#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
-#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
-#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
-#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
-#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
-#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
-#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
-#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
-
-#define PL111_CLCD_PERIPH_ID_0 0x11
-#define PL111_CLCD_PERIPH_ID_1 0x11
-#define PL111_CLCD_PERIPH_ID_2 0x04
-#define PL111_CLCD_PERIPH_ID_3 0x00
-#define PL111_CLCD_P_CELL_ID_0 0x0D
-#define PL111_CLCD_P_CELL_ID_1 0xF0
-#define PL111_CLCD_P_CELL_ID_2 0x05
-#define PL111_CLCD_P_CELL_ID_3 0xB1
-
-/**********************************************************************/
-
-// Register components (register bits)
-
-// This should make life easier to program specific settings in the different registers
-// by simplifying the setting up of the individual bits of each register
-// and then assembling the final register value.
-
-/**********************************************************************/
-
-// Register: PL111_REG_LCD_TIMING_0
-#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
-
-// Register: PL111_REG_LCD_TIMING_1
-#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
-
-// Register: PL111_REG_LCD_TIMING_2
-#define PL111_BIT_SHIFT_PCD_HI 27
-#define PL111_BIT_SHIFT_BCD 26
-#define PL111_BIT_SHIFT_CPL 16
-#define PL111_BIT_SHIFT_IOE 14
-#define PL111_BIT_SHIFT_IPC 13
-#define PL111_BIT_SHIFT_IHS 12
-#define PL111_BIT_SHIFT_IVS 11
-#define PL111_BIT_SHIFT_ACB 6
-#define PL111_BIT_SHIFT_CLKSEL 5
-#define PL111_BIT_SHIFT_PCD_LO 0
-
-#define PL111_BCD (1 << 26)
-#define PL111_IPC (1 << 13)
-#define PL111_IHS (1 << 12)
-#define PL111_IVS (1 << 11)
-
-#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
-
-// Register: PL111_REG_LCD_TIMING_3
-#define PL111_BIT_SHIFT_LEE 16
-#define PL111_BIT_SHIFT_LED 0
-
-#define PL111_CTRL_WATERMARK (1 << 16)
-#define PL111_CTRL_LCD_V_COMP (1 << 12)
-#define PL111_CTRL_LCD_PWR (1 << 11)
-#define PL111_CTRL_BEPO (1 << 10)
-#define PL111_CTRL_BEBO (1 << 9)
-#define PL111_CTRL_BGR (1 << 8)
-#define PL111_CTRL_LCD_DUAL (1 << 7)
-#define PL111_CTRL_LCD_MONO_8 (1 << 6)
-#define PL111_CTRL_LCD_TFT (1 << 5)
-#define PL111_CTRL_LCD_BW (1 << 4)
-#define PL111_CTRL_LCD_1BPP (0 << 1)
-#define PL111_CTRL_LCD_2BPP (1 << 1)
-#define PL111_CTRL_LCD_4BPP (2 << 1)
-#define PL111_CTRL_LCD_8BPP (3 << 1)
-#define PL111_CTRL_LCD_16BPP (4 << 1)
-#define PL111_CTRL_LCD_24BPP (5 << 1)
-#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
-#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
-#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
-#define PL111_CTRL_LCD_EN 1
-
-/**********************************************************************/
-
-// Register: PL111_REG_LCD_TIMING_0
-#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
-#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
-#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
-#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
-
-// Register: PL111_REG_LCD_TIMING_1
-#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
-#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
-#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
-#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
-
-// Register: PL111_REG_LCD_TIMING_2
-#define PL111_BIT_MASK_PCD_HI 0xF8000000
-#define PL111_BIT_MASK_BCD 0x04000000
-#define PL111_BIT_MASK_CPL 0x03FF0000
-#define PL111_BIT_MASK_IOE 0x00004000
-#define PL111_BIT_MASK_IPC 0x00002000
-#define PL111_BIT_MASK_IHS 0x00001000
-#define PL111_BIT_MASK_IVS 0x00000800
-#define PL111_BIT_MASK_ACB 0x000007C0
-#define PL111_BIT_MASK_CLKSEL 0x00000020
-#define PL111_BIT_MASK_PCD_LO 0x0000001F
-
-// Register: PL111_REG_LCD_TIMING_3
-#define PL111_BIT_MASK_LEE 0x00010000
-#define PL111_BIT_MASK_LED 0x0000007F
-
-#endif /* _PL111LCD_H__ */