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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w16-v6si23873323pgc.232.2018.06.07.04.08.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jun 2018 04:08:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=c5KeHvRw; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 01271211C3F47; Thu, 7 Jun 2018 04:08:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFC3C211DDA00 for ; Thu, 7 Jun 2018 04:08:22 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id f16-v6so9647793wrm.3 for ; Thu, 07 Jun 2018 04:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IDGZTFa44cMq31H+VcVxKIAVLEOpjBlqf99JEjpN1rg=; b=c5KeHvRwLMyCedDlQA5ES4N9PoLaT/+rLodZY+fdzg+WgFw0sJXUPexwZRA7qccS+/ lRfxYLZStaObVsX78LZw0Rz20C8/wy7ZHsKuWIOWOHheNCniQFs6ZJ1bI3Kp9WuE8Nzu wQrXVC0euA060gVLGNYn3S86SLsTyVr8zchWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IDGZTFa44cMq31H+VcVxKIAVLEOpjBlqf99JEjpN1rg=; b=IA+t55BJ2dtMo8tUZSlFTbkE5cxriKkEGLk+95olIcLgfhyOiAYbo+ovOrAHOYTKFg +JTnkcv+NHCruL9O2gYJTn/w+QNoCmttZqSVIWzfy7TnAaaFB9rclTYnB83rd6WSPxzG jiDVQvN7flX6cGyM4OrGRrG7Fuu/TveJYR60WAIeVny/QVV4pfxlkl+jERydI5z5WW9C dBMZWgVYn971fAR1sSC1/F6VOCm8AgrubD6xafz54J7x0yovjcL7+1wtzON1EDOltZFq TILs1qVlDnHoILHR2OfU5E/0++tCWqsNXToHDbJJ0GuzYMwIBGsWs7l3/0yfWcnmkOlI vp5A== X-Gm-Message-State: APt69E18lE/gvytctczyrVzFLhb1pJzf+4RH8GsX76kQU7Fg3Ffk0flO hOhBVJaHVTNIViki3zNHMKQotqdiOsU= X-Received: by 2002:adf:91e5:: with SMTP id 92-v6mr1342871wri.124.1528369701227; Thu, 07 Jun 2018 04:08:21 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:88ff:8f90:37f1:db91]) by smtp.gmail.com with ESMTPSA id 72-v6sm54997900wrb.22.2018.06.07.04.08.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jun 2018 04:08:20 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 7 Jun 2018 13:08:12 +0200 Message-Id: <20180607110812.26778-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180607110812.26778-1-ard.biesheuvel@linaro.org> References: <20180607110812.26778-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 5/5] ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.d.kinney@intel.com, jiewen.yao@intel.com, star.zeng@intel.com, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/ArmPkg.dec | 4 ++++ ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 21 ++++++++++++++++++-- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 9 +++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index debe066b6f7b..3aa229fe2ec9 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -85,6 +85,10 @@ [PcdsFeatureFlag.common] # Define if the GICv3 controller should use the GICv2 legacy gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + # Whether to implement warm reboot for capsule update using a jump back to the + # PEI entry point with caches and interrupts disabled. + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F + [PcdsFeatureFlag.ARM] # Whether to map normal memory as non-shareable. FALSE is the safe choice, but # TRUE may be appropriate to fix performance problems if you don't care about diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index d6d26bce5009..10ceafd14d5d 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -15,10 +15,13 @@ #include +#include +#include #include #include #include -#include +#include +#include #include @@ -89,7 +92,21 @@ EnterS3WithImmediateWake ( VOID ) { - // Not implemented + VOID (*Reset)(VOID); + + if (FeaturePcdGet (PcdArmReenterPeiForCapsuleWarmReboot) && + !EfiAtRuntime ()) { + // + // At boot time, we are the only core running, so we can implement the + // immediate wake (which is used by capsule update) by disabling the MMU + // and interrupts, and jumping to the PEI entry point. + // + Reset = (VOID (*)(VOID))(UINTN)FixedPcdGet64 (PcdFvBaseAddress); + + gBS->RaiseTPL (TPL_HIGH_LEVEL); + ArmDisableMmu (); + Reset (); + } } /** diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf index 5a1ee976e5bc..19021cd1e8b6 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -30,6 +30,15 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + ArmMmuLib ArmSmcLib BaseLib DebugLib + UefiBootServicesTableLib + UefiRuntimeLib + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress