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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id m3-v6si3037988plt.71.2018.07.04.00.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDN19Alq; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DD905210C42D3; Wed, 4 Jul 2018 00:51:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0D322098EAC7 for ; Wed, 4 Jul 2018 00:51:32 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id m16-v6so2289668pls.11 for ; Wed, 04 Jul 2018 00:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=aDN19AlqtSnaYjhijcH06XJ3M4U8eCUzLKvXX2B7yt+FLpHjEHqxud324YXKmx5mka BssYTY3Ak87vWJILkJyGaojsKMmzcZFwyc678N/BgHQQnD+x5sJVBWFqtyDigK/xouep nfQz9XDn/B1HLkc4CJD3X0WY9KOHzMNYrF8/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=kJV1KALn3B1NEFwsjNwizXdFfJSbqvj9vLBCnvjbVTHq2ZOPzlahRTqqrMHguqeiB7 mZfAFkRkSZjunDaTJvjqNusMjhkyS3bu4/TrIpEo3PbRp644IwK08+hMAsCj+AAKppHF axG8DAi86J7L7rSli4g1cprTqVnIxiiq39nwpTKATAWJ8hpf8unSxknKkIj76lizEe7/ ghA3aD9kOAVIzra1kna0EtdbVOvBgtppz/0h0USTLKiYTbFs4wX5iDanmIsbgr09w0Rk uig+G0xVWxYS3el1n/ykPHO/Fq1VN8eD1eDqBHZkJMYC5CTjXTOwuSnuLQhgMIsd28Hj Wn6w== X-Gm-Message-State: APt69E0QIq9NYKAy2emg0XnmQxlQiIiF17LetdhUTsP6byJXighECdgT 1nbdz4bbjdRvZR2U2OZ7eF4uKw== X-Received: by 2002:a17:902:b589:: with SMTP id a9-v6mr1064382pls.140.1530690692674; Wed, 04 Jul 2018 00:51:32 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:32 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:13 +0800 Message-Id: <20180704075117.7427-3-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Jason Zhang 1. During test PCIe mcs9922 UART card, the card can't work because the IO ATU config is overlap by Cfg0/Cfg1 ATU address. 2. After adjust the ATU windows, Cfg0/Cfg1 config as below: Cfg0 is equal to "ECAM + (BusBase, 0, 0)" Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Heyi Guo Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 55b80aa4e4..e5f66eaa4a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -640,11 +640,12 @@ void SetAtuConfig0RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; + UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); @@ -666,12 +667,12 @@ void SetAtuConfig1RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; - + UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);