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[198.145.21.10]) by mx.google.com with ESMTPS id n1-v6si1143717plp.166.2018.07.20.01.06.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 01:06:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=f7Y678Z0; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9D59820D7ADC9; Fri, 20 Jul 2018 01:06:20 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C36F02098EAD3 for ; Fri, 20 Jul 2018 01:06:19 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id s17-v6so4848855plp.7 for ; Fri, 20 Jul 2018 01:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xr5k2XZ09ZKR2+N8woM4YZ2+Kg0IN22WSqn6JeGlzfU=; b=f7Y678Z00ai7rmo92+R/maX3F3h1Cztq4g7SeqD9YwSQzf5WOW/xvp2gUvupIl7pTe 6khcbtU7YKiW17n8MQpVG/Z91wrcyjf+Qa1ipWWQTYZLrpmWSR5O+erwn/osAhpfSjdm EzM6OjDmtMmqhB7/uKnnr4f/HeKylS1SeFmX0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xr5k2XZ09ZKR2+N8woM4YZ2+Kg0IN22WSqn6JeGlzfU=; b=exMlTraehg7BOzg9iQgYr2qO3dKbKvjjPe+KNW8P+Mm1qgqQ/rBxSkDrTdyYG5OLHc 10obtiM7KXrb/oPdzncIp7ceWQrBOvuRtghBnQaEBym9UPu7WMpqWeoJm5YBSQ9/8y3g YOJTr/ovPDu9NSWjgDMoHGwShRa6PRx9/n0HAyEbVzIhra3rG4CDk6ITj5B3X1k3DI1V r9MKCvA8h4r2Sah+L5BXBYrNNudyjRji5XweB7wwTfLukCcaMWF5NcK1ziU4R20JGI9q 0BPKAgHpmwq1TBQIiE3ILInBpVEBtIt8fR2BVw7fTPKGwDUqclTH2EljEyfyXwf9fk+3 F7uA== X-Gm-Message-State: AOUpUlF99hVsunCphnY+SlbtHTFFYXenodHuAA9oUDAO5iDFc02RI4Dh w1ApCNZ5IL2qRwQKjE6RYOz1Vg== X-Received: by 2002:a17:902:e209:: with SMTP id ce9-v6mr1073835plb.233.1532073979480; Fri, 20 Jul 2018 01:06:19 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id n18-v6sm2066812pfa.50.2018.07.20.01.06.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jul 2018 01:06:18 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 20 Jul 2018 16:02:40 +0800 Message-Id: <20180720080242.3777-12-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180720080242.3777-1-ming.huang@linaro.org> References: <20180720080242.3777-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 11/13] Hisilicon/D0x: Switch to generic PciHostBridge driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Heyi Guo Address translation support is added to generic PciHostBridge driver in edk2 by commit 74d0a33, so we can switch to it for Hisilicon D03 and D05 which are using address translation between device address and host address for resource BAR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Ming Huang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney Cc: Haojian Zhuang --- Platform/Hisilicon/D03/D03.dsc | 13 ++++++++++--- Platform/Hisilicon/D03/D03.fdf | 3 ++- Platform/Hisilicon/D05/D05.dsc | 13 ++++++++++--- Platform/Hisilicon/D05/D05.fdf | 3 ++- Silicon/Hisilicon/Hisilicon.dsc.inc | 6 +++++- 5 files changed, 29 insertions(+), 9 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 6ceebba4ee..9e766a05a0 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -81,7 +81,11 @@ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf + PlatformPciLib|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf + PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. @@ -337,6 +341,7 @@ ArmPkg/Drivers/CpuDxe/CpuDxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf @@ -458,10 +463,12 @@ NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf } diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 264d134f98..cc15a5469c 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -157,6 +157,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf INF Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -264,7 +265,7 @@ READ_LOCK_STATUS = TRUE # INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 585184654b..db8cf2b8f9 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -97,6 +97,10 @@ LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + PlatformPciLib|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf + PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf [LibraryClasses.common.SEC] ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf @@ -472,6 +476,7 @@ ArmPkg/Drivers/CpuDxe/CpuDxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf @@ -611,10 +616,12 @@ NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf } diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 2fa7a63d72..6ca2b45345 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -161,6 +161,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -286,7 +287,7 @@ READ_LOCK_STATUS = TRUE # INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc index 20ff1ec25b..3ac8e20232 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -254,7 +254,11 @@ [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + # + # IO is mapped to memory space, so we use the same size of + # PcdPrePiCpuMemorySize + # + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000