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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id e10-v6si10614202pgm.94.2018.07.23.23.33.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jul 2018 23:33:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OVDxUv88; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9CB53210C1248; Mon, 23 Jul 2018 23:33:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1E2C9210C1243 for ; Mon, 23 Jul 2018 23:33:04 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id j8-v6so1235866pll.12 for ; Mon, 23 Jul 2018 23:33:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JFIGb5UXcq0ui387JGWxFCxLkZUXiE3WejYTz+Q3Lfw=; b=OVDxUv881oPJfpaks91goit6jSrETS1HXIvkCLFjXyXO5an4M9q4AZSqCeNYKpdxjq rJ2qnDBz3WQ5E0VjZSRrQYRZDZCmy2QxyQ6/t/IrLQMXULmsnZNt+UUeB4Ah2TRew/dg 2pv09GZEiMFJipa7qtwQcJwz/Rin3JKBkbtwc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JFIGb5UXcq0ui387JGWxFCxLkZUXiE3WejYTz+Q3Lfw=; b=cCz97rzQFiSPhdlOrm09F41ioojYXqXQK7rjff78izyWtvqHOOr2WvBBUm7NPx8M5D +CS+SISDtsdQH6CDGuuzlQB/ywVPrL33S5PoahFxjFqf4T4zMyxYdNRoVnopddd8+QPt UAhQOTpn0Xz3/re4uhlG2HKUnos5ui+N6fPwWu70k7oyoxvhM6FJPrgamosaG0c/G73m 1HcE/C5XBj0uxe3jD/SbSnyHiLg3zlax3Os1J8zxnpBaa0abbFBbszyrjAF14oUHOYga x4uAuN8Ew3DXHF2qRHEEOvBavcEtNQxSQqqBX0LtqCcWyrP/jejx+WF4vabHksaQfLWb NV+Q== X-Gm-Message-State: AOUpUlFJa76eYZfx5HIScA3t8HSn4Xju29nPuzMo7WTE8FoOxJ1W6FZ0 wGMOkt4s2q0gsifkM943l8CdhA== X-Received: by 2002:a17:902:9348:: with SMTP id g8-v6mr3090273plp.302.1532413983784; Mon, 23 Jul 2018 23:33:03 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.32.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:33:03 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:18 +0800 Message-Id: <20180724063220.61679-11-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Heyi Guo Address translation support is added to generic PciHostBridge driver in edk2 by commit 74d0a33, so we can switch to it for Hisilicon D03 and D05 which are using address translation between device address and host address for resource BAR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Ming Huang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney Cc: Haojian Zhuang --- Platform/Hisilicon/D03/D03.dsc | 14 +++++++++++--- Platform/Hisilicon/D03/D03.fdf | 3 ++- Platform/Hisilicon/D05/D05.dsc | 14 +++++++++++--- Platform/Hisilicon/D05/D05.fdf | 3 ++- Silicon/Hisilicon/Hisilicon.dsc.inc | 6 +++++- 5 files changed, 31 insertions(+), 9 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 6ceebba4ee..38548a0f23 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -81,7 +81,11 @@ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf + PlatformPciLib|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf + PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. @@ -122,6 +126,7 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmTokenSpaceGuid.PcdPciIoTranslation|0 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 @@ -337,6 +342,7 @@ ArmPkg/Drivers/CpuDxe/CpuDxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf @@ -458,10 +464,12 @@ NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf } diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 264d134f98..cf11aeccc8 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -157,6 +157,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf INF Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -264,7 +265,7 @@ READ_LOCK_STATUS = TRUE # INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 585184654b..f2bbf27639 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -97,6 +97,10 @@ LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + PlatformPciLib|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf + PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf [LibraryClasses.common.SEC] ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf @@ -134,6 +138,7 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmTokenSpaceGuid.PcdPciIoTranslation|0 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 @@ -472,6 +477,7 @@ ArmPkg/Drivers/CpuDxe/CpuDxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf @@ -611,10 +617,12 @@ NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf } diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 2fa7a63d72..701804360e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -161,6 +161,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -286,7 +287,7 @@ READ_LOCK_STATUS = TRUE # INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc index 20ff1ec25b..3ac8e20232 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -254,7 +254,11 @@ [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + # + # IO is mapped to memory space, so we use the same size of + # PcdPrePiCpuMemorySize + # + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000