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[198.145.21.10]) by mx.google.com with ESMTPS id t24-v6si10573015pgm.106.2018.07.23.23.32.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jul 2018 23:32:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=W5DS2D2F; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 43E9A210C1240; Mon, 23 Jul 2018 23:32:57 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 403D3210C1231 for ; Mon, 23 Jul 2018 23:32:56 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id w3-v6so1301365plq.2 for ; Mon, 23 Jul 2018 23:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kmx5VE0T7s3UrjSqX+fV9HYUF7VbiMnQpduGNCuypoc=; b=W5DS2D2Fryz39CmgDYasPIOL5kvLIfK36GHTxQY9SxfxwsMqoUg/9E/Xvg+FLXeoNA YDdDRcTJtkdSPZGxqYK8D+0nEEc7VLVpH+TnZEQUm7xQKb9OkoQktY/MYI8QP2eHJayR o+Y9SchQXci+R2oo0zvoe01vbHB7Ede3zyyKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kmx5VE0T7s3UrjSqX+fV9HYUF7VbiMnQpduGNCuypoc=; b=tZG6d5SCCIv7Dpj8sMeo1PLtV21lVY5o8Ui6+bflIEOhKF97+F6XZDGroo+vV5xYtd hLwQyzMICBFnmwBiSFJx7fIzJNa5tExrgSXRdTJ0l9TrdBT1gfiZcVdVALsJcB96B84k hqTkwy0dqKkzVGVFoontPT6Hb8GEDfhmqrfdsf1yPPNLCwMtY1tQCC/gwWbbPuwP9rGP 6BYN5HuO0J9WkLI8w5S0WDnrB+pwyXMKEdoUphDwpXVmUoLbgbaqFHsPRnAA/K5E4UsS HZsXO7RaEkDvVTm0MZ3bC2dsoWU8NXzQEz8gUtM8t4rsHGPzul+ymn92dP2gYKG/hQD7 KOvA== X-Gm-Message-State: AOUpUlEbDZ90kPyX4sdrWqxea7noRFXuAB9KtKVHZmUv1KCmcv1UULz/ 5q7QCfoA3xM75w5SP/OEVWWKeg== X-Received: by 2002:a17:902:ac1:: with SMTP id 59-v6mr6574998plp.18.1532413975913; Mon, 23 Jul 2018 23:32:55 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.32.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:32:55 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:16 +0800 Message-Id: <20180724063220.61679-9-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 08/12] Hisilicon: add PciHostBridgeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Heyi Guo This is to prepare for switching to generic PciHostBridge, and PciHostBridgeLib is needed by PciHostBridge driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c | 304 ++++++++++++++++++++ Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++++ 2 files changed, 355 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c new file mode 100644 index 0000000000..6aff5cdd3d --- /dev/null +++ b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,304 @@ +/** @file + PCI Host Bridge Library instance for Hisilicon D0x + + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), // PCI + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + 0, + 0 + }, { + // Io + 0, + 0, + 0 + }, { + // Mem + MAX_UINT64, + 0, + 0 + }, { + // MemAbove4G + MAX_UINT64, + 0, + 0 + }, { + // PMem + MAX_UINT64, + 0, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +STATIC +EFI_STATUS +ConstructRootBridge ( + PCI_ROOT_BRIDGE *Bridge, + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture + ) +{ + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + CopyMem (Bridge, &mRootBridgeTemplate, sizeof *Bridge); + Bridge->Segment = Appeture->Segment; + Bridge->Bus.Base = Appeture->BusBase; + Bridge->Bus.Limit = Appeture->BusLimit; + Bridge->Io.Base = Appeture->IoBase; + // According to UEFI 2.7, device address = host address + translation + Bridge->Io.Translation = Appeture->IoBase - Appeture->CpuIoRegionBase; + // IoLimit is actually an address in CPU view + // TODO: improve the definition of PCI_ROOT_BRIDGE_RESOURCE_APPETURE + Bridge->Io.Limit = Appeture->IoLimit + Bridge->Io.Translation; + if (Appeture->PciRegionBase > MAX_UINT32) { + Bridge->MemAbove4G.Base = Appeture->PciRegionBase; + Bridge->MemAbove4G.Limit = Appeture->PciRegionLimit; + Bridge->MemAbove4G.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase; + } else { + Bridge->Mem.Base = Appeture->PciRegionBase; + Bridge->Mem.Limit = Appeture->PciRegionLimit; + Bridge->Mem.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase; + } + + DevicePath = AllocateCopyPool(sizeof mEfiPciRootBridgeDevicePath, &mEfiPciRootBridgeDevicePath); + if (DevicePath == NULL) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] AllocatePool failed!\n", __FUNCTION__, __LINE__)); + return EFI_OUT_OF_RESOURCES; + } + + DevicePath->AcpiDevicePath.UID = Bridge->Segment; + Bridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; + return EFI_SUCCESS; +} + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + EFI_STATUS Status; + UINTN Loop1; + UINTN Loop2; + UINT32 PcieRootBridgeMask; + UINTN RootBridgeCount = 0; + PCI_ROOT_BRIDGE *Bridges; + + // Set default value to 0 in case we got any error. + *Count = 0; + + + if (!OemIsMpBoot()) + { + PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask); + } + else + { + PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P); + } + + for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { + if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { + continue; + } + + for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) { + if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) { + continue; + } + RootBridgeCount++; + } + } + + Bridges = AllocatePool (RootBridgeCount * sizeof *Bridges); + if (Bridges == NULL) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - AllocatePool failed!\n", __FUNCTION__, __LINE__)); + return NULL; + } + + for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { + if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { + continue; + } + + for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) { + if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) { + continue; + } + Status = ConstructRootBridge (&Bridges[*Count], &mResAppeture[Loop1][Loop2]); + if (EFI_ERROR (Status)) { + continue; + } + (*Count)++; + } + } + + if (*Count == 0) { + FreePool (Bridges); + return NULL; + } + return Bridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + UINTN Index; + + for (Index = 0; Index < Count; Index++) { + FreePool (Bridges[Index].DevicePath); + } + + if (Bridges != NULL) { + FreePool (Bridges); + } +} + + +#ifndef MDEPKG_NDEBUG +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { + L"Mem", L"I/O", L"Bus" +}; +#endif + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf new file mode 100644 index 0000000000..dd451cff33 --- /dev/null +++ b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -0,0 +1,51 @@ +## @file +# PCI Host Bridge Library instance for Hisilicon D0x +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = PciHostBridgeLib + FILE_GUID = e5c91e8a-0b2b-11e8-9533-286ed489ee9b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 ARM +# + +[Sources] + PciHostBridgeLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + OemMiscLib + +[Pcd] + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P