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[198.145.21.10]) by mx.google.com with ESMTPS id f23si4008897pgv.431.2018.11.30.02.55.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 02:55:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OyKHhzq5; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4727B21197392; Fri, 30 Nov 2018 02:55:11 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E98A7211944DE for ; Fri, 30 Nov 2018 02:55:09 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id r10so4817913wrs.10 for ; Fri, 30 Nov 2018 02:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Fxn0md9W326VGS6X4FYnc4hR5Lx8p28p29wHy3DIYk8=; b=OyKHhzq5KMzA6fPpw/2HmEeeTpjeZ985Z6MTUca+Gzrp/G4WSfyAaApIenK7GhZ6WZ H/UeyoFEIjCCsL+sIyxFbfgAoLkKR74IgUwfzmWassMzuiT0vEXJRmHi/LW/TMEAhnHV 5veN1xh+TftsNlFebja7rpSGYceWR9/xCEeAQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Fxn0md9W326VGS6X4FYnc4hR5Lx8p28p29wHy3DIYk8=; b=gqztlXgBJ2DT/vvGX/0UYdPhL3Q1Envhl14c/JNrVHSl7kXLG+HbXNRfg8K40ao2X5 g1EzY35DR7XAjgfVOz9rR9h9E2KEI6P/iQ0rbn7sWvzFMCFImx+m4xVF5h7E2u6Qqg/q wpuXz94x3jMCKAz78WEprgNYcztqdcxc8h0DP6mDeoAJqNX+xU7d7R0t3BTax6WYm5pb TRcImKneQ3xyvOij+eboiomgUNW30H83RwuU2QuobKZWvKWEBMPSySFW+mdDabWDQxhk ZbUXaNH3ShZpc/zYoYhXBoqbWUSJ96BmHtfbfdoRucHc7zqPgUKQZHGKBmW3DjtoHTYM 0MIw== X-Gm-Message-State: AA+aEWbFbjntP8WwiMjB5Qd7KyK/bqxrlb/FH67o0ocmP3eLSxB70Vr+ CZCoa/dDhHRuofk4g0JRzuva8PXQJdI= X-Received: by 2002:a5d:4d46:: with SMTP id a6mr4553140wru.28.1543575307231; Fri, 30 Nov 2018 02:55:07 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:f070:d240:312e:9f99]) by smtp.gmail.com with ESMTPSA id k73sm5101225wmd.36.2018.11.30.02.55.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 02:55:06 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 30 Nov 2018 11:55:03 +0100 Message-Id: <20181130105503.3313-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms] Platform, Silicon: drop gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize will be removed, so drop any overrides from the platforms in edk2-platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Hisilicon/Hisilicon.dsc.inc | 1 - Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 - Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 5 ----- Platform/ARM/SgiPkg/SgiPlatform.dsc | 1 - Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 3 --- Platform/Comcast/RDKQemu/RDKQemu.dsc | 4 ---- Platform/Hisilicon/D06/D06.dsc | 1 - Platform/LeMaker/CelloBoard/CelloBoard.dsc | 5 ----- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 - Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 1 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 5 ----- 11 files changed, 28 deletions(-) -- 2.19.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc index 3ac8e202322d..63d28a57406b 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -253,7 +253,6 @@ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE [PcdsFixedAtBuild.common] - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 # # IO is mapped to memory space, so we use the same size of # PcdPrePiCpuMemorySize diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index 14a1bda7b8b4..b3fd1846c0bf 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -375,7 +375,6 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x41F0000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 51327a67dffb..b062f671f57f 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -385,11 +385,6 @@ DEFINE DO_CAPSULE = FALSE # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 - # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the - # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below - # that) - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 - # # ARM PrimeCell # diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc index 68249add3127..52ca796a4f28 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc @@ -145,7 +145,6 @@ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x60000000 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc index d20f1a738710..7094e57ee13a 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc +++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -159,9 +159,6 @@ # Set tick frequency value to 100Mhz gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000 - # the entire FVP address space can be covered by 36 bit VAs - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 - # # ACPI Table Version # diff --git a/Platform/Comcast/RDKQemu/RDKQemu.dsc b/Platform/Comcast/RDKQemu/RDKQemu.dsc index b36c7cb7842f..f22f14aed99d 100644 --- a/Platform/Comcast/RDKQemu/RDKQemu.dsc +++ b/Platform/Comcast/RDKQemu/RDKQemu.dsc @@ -154,10 +154,6 @@ gRdkTokenSpaceGuid.PcdRdkConfFileDevicePath|L"PciRoot(0x0)/Pci(0x2,0x0)" [PcdsFixedAtBuild.AARCH64] - # KVM limits it IPA space to 40 bits (1 TB), so there is no need to - # support anything bigger, even if the host hardware does - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 - # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point, # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the # presence of the 32-bit entry point anyway (because many AARCH64 systems diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 742fe30b62c3..396bd03c9d24 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -128,7 +128,6 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|48 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|48 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index e63cda1af99a..103c2fb74114 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -375,11 +375,6 @@ DEFINE DO_FLASHER = FALSE # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 - # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the - # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below - # that) - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 - # # ARM PrimeCell # diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 997ea344330d..d3225125a9a6 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -243,7 +243,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFFC0 gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 gArmPlatformTokenSpaceGuid.PcdCoreCount|2 diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index d506ca112147..8dbf836f7e29 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -234,7 +234,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFFC0 gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 # 12x 2-core processor clusters diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 4cfbe1985854..1927ef3ebafb 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -368,11 +368,6 @@ DEFINE DO_FLASHER = FALSE # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 - # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the - # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below - # that) - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 - # # ARM PrimeCell #