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[198.145.21.10]) by mx.google.com with ESMTPS id x3si18589258pgj.493.2018.12.05.10.50.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=a1oFPVIn; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 115AC21199264; Wed, 5 Dec 2018 10:50:28 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 83FE4211982C9 for ; Wed, 5 Dec 2018 10:50:26 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id q18so20777021wrx.9 for ; Wed, 05 Dec 2018 10:50:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NCvZDJXswWfPyXzuoG9wrhqYajJJheQJ1vp945q5J8Q=; b=a1oFPVIn6IiafvQQ1damYFF9ro770Gn0cNay7xvcPVLrypJ344yKSBhXe2ZFCf38zz ivfOp/WgDtagLKsa40kbtArdgTEsm38XSPEPkctOmI63rkW/dkomHVVmVDB+RuryuLq1 vjB44+/M/0k53orqBNgKX9XCyueIm5CCRP9Ik= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NCvZDJXswWfPyXzuoG9wrhqYajJJheQJ1vp945q5J8Q=; b=gOntetg6Ppf0sbDWlNgVOctQymwiMU10NFhcmuky+ZcKm40ry8AR8AZpCJZcERmJei MnV2kqi3iyeIsWwTFWcVHPd9ubQ/uUSwVDkMgSZJGNDNhv+ZS5QivakdwLIc98jRVafc 7UM8A7LE/rNkQyFI3YudqMKAa+g4pARfz0622z1BT5bDTHs8FYwIrHtzO3A2+nGKbRww RzERAXO2XNvRSH2QNH6aESzMHzUozARRQbHwMi2lDhefvM6gidW3/j3kRd73lr5PVwoQ aAFNDMx8HcE9ADihXKKr475F5WiDIMGL4ovVLJ3oAyQYxQRssoAaADM0tzVXXgCeJXe9 sTdw== X-Gm-Message-State: AA+aEWa5Z9LpaZFZOI5xCIEPO5ueF/xpQEv9NIz32dNtisj9nORr7XRC IpHyMi230bNoberwQYUZRSGe25NU3eq5BA== X-Received: by 2002:adf:c612:: with SMTP id n18mr21928809wrg.174.1544035824640; Wed, 05 Dec 2018 10:50:24 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:15 +0100 Message-Id: <20181205185020.21441-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 1/6] Silicon/AMD/Styx: move SOC version macros to common header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of adding yet another redefinition in the next patch, move the silicon revision testing macros into a shared header file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/Common/SocVersion.h | 19 +++++++++++++++++++ Silicon/AMD/Styx/AcpiTables/Iort.c | 6 +----- Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c | 7 ++----- Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 7 ++----- 4 files changed, 24 insertions(+), 15 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/AMD/Styx/Common/SocVersion.h b/Silicon/AMD/Styx/Common/SocVersion.h new file mode 100644 index 000000000000..fc270b7c3431 --- /dev/null +++ b/Silicon/AMD/Styx/Common/SocVersion.h @@ -0,0 +1,19 @@ +#/** @file +# SoC specific defines +# +# Copyright (c) 2018 Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c index 370e71e13610..9c232379eff5 100644 --- a/Silicon/AMD/Styx/AcpiTables/Iort.c +++ b/Silicon/AMD/Styx/AcpiTables/Iort.c @@ -14,6 +14,7 @@ #include #include +#include #define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) @@ -354,11 +355,6 @@ STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { #pragma pack() -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - EFI_ACPI_DESCRIPTION_HEADER * IortHeader ( VOID diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c index ea49cae9890f..1d2bca3d57ba 100644 --- a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c @@ -22,6 +22,8 @@ #include +#include + STATIC VOID ResetSataController ( @@ -144,11 +146,6 @@ InitializeSataController ( AhciBaseAddr, SIZE_4KB); } -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - EFI_STATUS EFIAPI StyxSataPlatformDxeEntryPoint ( diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 7e8f918b11b4..b9dfa2367ab2 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -28,6 +28,8 @@ #include +#include + #define PMU_INT_FLAG_SPI 0 #define PMU_INT_TYPE_HIGH_LEVEL 4 @@ -230,11 +232,6 @@ DisableSmmu ( } } -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - STATIC VOID SetSocIdStatus (