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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w17si11411760pgl.6.2018.12.11.07.02.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gGEEVUtJ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2DD832119955F; Tue, 11 Dec 2018 07:02:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3469121199539 for ; Tue, 11 Dec 2018 07:02:48 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id a62so2553960wmh.4 for ; Tue, 11 Dec 2018 07:02:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z6kr7v+j7MK4EvibR24pT6/uaEiR9kc0U6Zb6kPUkb0=; b=gGEEVUtJwXmIfEC5+1vKxr/glw5FXJCX61d/+DImcALsd7fhD7Axim3Z9qT+kVmjKL jiaPVGSJikiaJqwXMJxLHyb6xw5lh5qT7jD+gMhEm9o9nLTKhywxZwTXoQVeB9AWwJKZ 5sZ4yYE/mcq6byyjQE4zUnCPgTNbn7cTtah+M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z6kr7v+j7MK4EvibR24pT6/uaEiR9kc0U6Zb6kPUkb0=; b=ENGaMxTks5BviDpSKQ3eg5kYDuHaCXoz8y6EG/JVGbVEAq9XGJNkJdvqf1wbeIJsYy 3XmeNhEAPCM6uSMFYFTa40RiPUrgWH9Hz72/kfZteiyTRFA0yZg3GA+IoALs6z4S4ubK FZGnm4L6ZxDX1St1QRoed0yNel0eReIX3M0R4smVcoruieVqAckL2CLLcURzFmTYs3I4 CTNNrT5G194q00QJs5iFv46qbcDsPKnIzQEsCMpM6SdXZ9HBGQTL/LBuh2kyiMkMd2kO Mt9241lC8VtaR9Z6+qHt6JUKglLqtVAMjHU09UHc0hft5O+xoKGeAJKHi6FDRAh6nx44 ULDQ== X-Gm-Message-State: AA+aEWYhd2TiVp522CO3tC87V5Pkp7BYdxYmJ8wxMd48hq1NGj7uh+az 0IcFJ3iTN+dprpNhTA+6ISMKNCKptyGdlA== X-Received: by 2002:a1c:6a16:: with SMTP id f22mr1947905wmc.25.1544540565791; Tue, 11 Dec 2018 07:02:45 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:44 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:34 +0100 Message-Id: <20181211150237.32275-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 3/6] Silicon/Styx: get rid of NUM_CORES preprocessor define on command line X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of relying on the compiler command line to pass the value of NUM_CORES as a preprocessor define, use the value of the PcdCoreCount PCD that we already set in the platform .DSC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 4 ++-- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 4 ++-- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 4 ++-- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 ++ Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 ++ Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 2 ++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl | 2 ++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc | 2 ++ 8 files changed, 16 insertions(+), 6 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 9172c82fdeba..696090cfb2dd 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -268,8 +268,8 @@ DEFINE DO_CAPSULE = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index f556591b9e25..5056122aa681 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -260,8 +260,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 5abf1d52f916..8187e799a6fc 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -258,8 +258,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 2a42d76d4883..be885d6aea90 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -42,6 +42,7 @@ SsdtXgbe.asl [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -84,6 +85,7 @@ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 3f36799f5df1..87cdcb3e6b25 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -24,6 +24,7 @@ StyxDtbLoaderLib.c [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec @@ -49,6 +50,7 @@ gArmTokenSpaceGuid.PcdSystemMemoryBase [FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment gAmdStyxTokenSpaceGuid.PcdSata1PortCount diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 4ca5d9bebed6..b1e4984d3fd0 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -33,6 +33,8 @@ #define PMU_INT_FLAG_SPI 0 #define PMU_INT_TYPE_HIGH_LEVEL 4 +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + // // PMU interrupts per core // diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl index c1417e7e1cd7..60288114aeab 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl @@ -21,6 +21,8 @@ **/ +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) { Scope (_SB) diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc index 64a6cda7fd87..031307fa3c36 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc @@ -18,6 +18,8 @@ #define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + #pragma pack(1) typedef struct { EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;