From patchwork Fri Feb 5 08:05:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4809C433E9 for ; Fri, 5 Feb 2021 08:06:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53D1964F97 for ; Fri, 5 Feb 2021 08:06:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231314AbhBEIGD (ORCPT ); Fri, 5 Feb 2021 03:06:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231145AbhBEIGA (ORCPT ); Fri, 5 Feb 2021 03:06:00 -0500 Received: from forward100p.mail.yandex.net (forward100p.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 408BFC061786; Fri, 5 Feb 2021 00:05:19 -0800 (PST) Received: from forward101q.mail.yandex.net (forward101q.mail.yandex.net [IPv6:2a02:6b8:c0e:4b:0:640:4012:bb98]) by forward100p.mail.yandex.net (Yandex) with ESMTP id D6D235982E0B; Fri, 5 Feb 2021 11:05:15 +0300 (MSK) Received: from vla1-ce2e345b2df9.qloud-c.yandex.net (vla1-ce2e345b2df9.qloud-c.yandex.net [IPv6:2a02:6b8:c0d:3609:0:640:ce2e:345b]) by forward101q.mail.yandex.net (Yandex) with ESMTP id D235ACF40007; Fri, 5 Feb 2021 11:05:15 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-ce2e345b2df9.qloud-c.yandex.net (mxback/Yandex) with ESMTP id jUZApgPp6V-5FI0VE0S; Fri, 05 Feb 2021 11:05:15 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512315; bh=MeAaehzU5jX+Y31M8ISgyWDTvBZM7hVZBTAtcfUrJDw=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=Ij9QbLnmeCc7Dl8b0jENRfKXCPyzTj0GgSemhrKZvGWv9D2vxmq5c1ApQVAkcrdgQ wPAzNYFZYP6GsOZkoElQFO1sGhTwC9/FcIWqUU26iKhV6d5u9oMgZhfN5kR+aGjGs6 YE031dfpEw+kN6K5pCKeh0B9buBHxI7OOHczkidk= Authentication-Results: vla1-ce2e345b2df9.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5En8GQxu; Fri, 05 Feb 2021 11:05:15 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/7] gpio: gpio-ep93xx: fix BUG_ON port F usage Date: Fri, 5 Feb 2021 11:05:01 +0300 Message-Id: <20210205080507.16007-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Two index spaces and ep93xx_gpio_port conversion are confusing. Instead add a separate struct to store necessary data and remove ep93xx_gpio_port. - add struct to store IRQ related data for each IRQ capable chip - replace offset array with defined offsets - add IRQ registers offset for each IRQ capable chip into ep93xx_gpio_banks ------------[ cut here ]------------ kernel BUG at drivers/gpio/gpio-ep93xx.c:64! ---[ end trace 3f6544e133e9f5ae ]--- Fixes: fd935fc421e74 ("gpio: ep93xx: Do not pingpong irq numbers") Signed-off-by: Nikita Shubin --- v3->v4: - drop ep93xx_gpio_port - embed IRQ data into struct ep93xx_gpio_irq_chip, which also contains offset of specific IRQ - allocate ep93xx_gpio_irq_chip for IRQ capable gpiochips - drop offset arrays - add IRQ register offsets defines - add IRQ chip offset to ep93xx_gpio_banks --- drivers/gpio/gpio-ep93xx.c | 186 ++++++++++++++++++++----------------- 1 file changed, 99 insertions(+), 87 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 226da8df6f10..e3b5e2c37259 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -25,6 +25,9 @@ /* Maximum value for gpio line identifiers */ #define EP93XX_GPIO_LINE_MAX 63 +/* Number of GPIO chips in EP93XX */ +#define EP93XX_GPIO_CHIP_NUM 8 + /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 @@ -34,74 +37,74 @@ */ #define EP93XX_GPIO_F_IRQ_BASE 80 -struct ep93xx_gpio { - void __iomem *base; - struct gpio_chip gc[8]; +struct ep93xx_gpio_irq_chip { + u8 irq_offset; + u8 int_unmasked; + u8 int_enabled; + u8 int_type1; + u8 int_type2; + u8 int_debounce; }; -/************************************************************************* - * Interrupt handling for EP93xx on-chip GPIOs - *************************************************************************/ -static unsigned char gpio_int_unmasked[3]; -static unsigned char gpio_int_enabled[3]; -static unsigned char gpio_int_type1[3]; -static unsigned char gpio_int_type2[3]; -static unsigned char gpio_int_debounce[3]; - -/* Port ordering is: A B F */ -static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; -static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; -static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; -static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; -static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; - -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) -{ - BUG_ON(port > 2); +struct ep93xx_gpio_chip { + struct gpio_chip gc; + struct ep93xx_gpio_irq_chip *eic; +}; - writeb_relaxed(0, epg->base + int_en_register_offset[port]); +struct ep93xx_gpio { + void __iomem *base; + struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; +}; - writeb_relaxed(gpio_int_type2[port], - epg->base + int_type2_register_offset[port]); +#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) - writeb_relaxed(gpio_int_type1[port], - epg->base + int_type1_register_offset[port]); +struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc) +{ + struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc); - writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], - epg->base + int_en_register_offset[port]); + return egc->eic; } -static int ep93xx_gpio_port(struct gpio_chip *gc) +/************************************************************************* + * Interrupt handling for EP93xx on-chip GPIOs + *************************************************************************/ +#define EP93XX_INT_TYPE1_OFFSET 0x00 +#define EP93XX_INT_TYPE2_OFFSET 0x04 +#define EP93XX_INT_EOI_OFFSET 0x08 +#define EP93XX_INT_EN_OFFSET 0x0c +#define EP93XX_INT_STATUS_OFFSET 0x10 +#define EP93XX_INT_RAW_STATUS_OFFSET 0x14 +#define EP93XX_INT_DEBOUNCE_OFFSET 0x18 + +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, + struct ep93xx_gpio_irq_chip *eic) { - struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = 0; + writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); - while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port]) - port++; + writeb_relaxed(eic->int_type2, + epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); - /* This should not happen but is there as a last safeguard */ - if (port == ARRAY_SIZE(epg->gc)) { - pr_crit("can't find the GPIO port\n"); - return 0; - } + writeb_relaxed(eic->int_type1, + epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); - return port; + writeb_relaxed(eic->int_unmasked & eic->int_enabled, + epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); } static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); int port_mask = BIT(offset); if (enable) - gpio_int_debounce[port] |= port_mask; + eic->int_debounce |= port_mask; else - gpio_int_debounce[port] &= ~port_mask; + eic->int_debounce &= ~port_mask; - writeb(gpio_int_debounce[port], - epg->base + int_debounce_register_offset[port]); + writeb(eic->int_debounce, + epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); } static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) @@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) */ stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain, offset)); stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); for_each_set_bit(offset, &stat, 8) - generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, + generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain, offset)); chained_irq_exit(irqchip, desc); @@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { - gpio_int_type2[port] ^= port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, port); + eic->int_type2 ^= port_mask; /* switch edge direction */ + ep93xx_gpio_update_int_params(epg, eic); } - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); int port_mask = BIT(d->irq & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) - gpio_int_type2[port] ^= port_mask; /* switch edge direction */ + eic->int_type2 ^= port_mask; /* switch edge direction */ - gpio_int_unmasked[port] &= ~port_mask; - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &= ~port_mask; + ep93xx_gpio_update_int_params(epg, eic); - writeb(port_mask, epg->base + eoi_register_offset[port]); + writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); } static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] &= ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked &= ~BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); - gpio_int_unmasked[port] |= BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, port); + eic->int_unmasked |= BIT(d->irq & 7); + ep93xx_gpio_update_int_params(epg, eic); } /* @@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int port = ep93xx_gpio_port(gc); int offset = d->irq & 7; int port_mask = BIT(offset); irq_flow_handler_t handler; @@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) switch (type) { case IRQ_TYPE_EDGE_RISING: - gpio_int_type1[port] |= port_mask; - gpio_int_type2[port] |= port_mask; + eic->int_type1 |= port_mask; + eic->int_type2 |= port_mask; handler = handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: - gpio_int_type1[port] |= port_mask; - gpio_int_type2[port] &= ~port_mask; + eic->int_type1 |= port_mask; + eic->int_type2 &= ~port_mask; handler = handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: - gpio_int_type1[port] &= ~port_mask; - gpio_int_type2[port] |= port_mask; + eic->int_type1 &= ~port_mask; + eic->int_type2 |= port_mask; handler = handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: - gpio_int_type1[port] &= ~port_mask; - gpio_int_type2[port] &= ~port_mask; + eic->int_type1 &= ~port_mask; + eic->int_type2 &= ~port_mask; handler = handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: - gpio_int_type1[port] |= port_mask; + eic->int_type1 |= port_mask; /* set initial polarity based on current input level */ if (gc->get(gc, offset)) - gpio_int_type2[port] &= ~port_mask; /* falling */ + eic->int_type2 &= ~port_mask; /* falling */ else - gpio_int_type2[port] |= port_mask; /* rising */ + eic->int_type2 |= port_mask; /* rising */ handler = handle_edge_irq; break; default: @@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) irq_set_handler_locked(d, handler); - gpio_int_enabled[port] |= port_mask; + eic->int_enabled |= port_mask; - ep93xx_gpio_update_int_params(epg, port); + ep93xx_gpio_update_int_params(epg, eic); return 0; } @@ -276,17 +279,19 @@ struct ep93xx_gpio_bank { const char *label; int data; int dir; + int irq; int base; bool has_irq; bool has_hierarchical_irq; unsigned int irq_base; }; -#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \ { \ .label = _label, \ .data = _data, \ .dir = _dir, \ + .irq = _irq, \ .base = _base, \ .has_irq = _has_irq, \ .has_hierarchical_irq = _has_hier, \ @@ -295,16 +300,16 @@ struct ep93xx_gpio_bank { static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), + EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), + EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), + EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), + EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), + EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), }; static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, @@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } -static int ep93xx_gpio_add_bank(struct gpio_chip *gc, +static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, struct ep93xx_gpio_bank *bank) { void __iomem *data = epg->base + bank->data; void __iomem *dir = epg->base + bank->dir; + struct gpio_chip *gc = &egc->gc; struct device *dev = &pdev->dev; struct gpio_irq_chip *girq; int err; @@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc, girq = &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { gc->set_config = ep93xx_gpio_set_config; + egc->eic = devm_kcalloc(dev, 1, + sizeof(*egc->eic), + GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; + egc->eic->irq_offset = bank->irq; girq->chip = &ep93xx_gpio_irq_chip; } @@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev) return PTR_ERR(epg->base); for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct gpio_chip *gc = &epg->gc[i]; + struct ep93xx_gpio_chip *gc = &epg->gc[i]; struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) From patchwork Fri Feb 5 08:05:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B85C9C433DB for ; Fri, 5 Feb 2021 08:06:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8755764F9B for ; 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Fri, 5 Feb 2021 11:05:16 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-7d66b24b62b3.qloud-c.yandex.net (mxback/Yandex) with ESMTP id ARjQYZbpdq-5GIi5ll7; Fri, 05 Feb 2021 11:05:16 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512316; bh=JPTXGO5bMF41hdHAoaK/g/DYbPxZx1DNYfpjY6Od3C0=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=AOisBGI1HVCQ5Szt40XevfiNU724Dz+GXL3JnrIrbTHy93OkzgrpwDsabM1PEhCBv TrhSUnHBV0GPHe4arq1cLIU73zV+QgdP88y84Zx6Ot+KfL6wkgcSMdskkGJtkUAAmB u5oYzBOS4npyFvl72OYN1ZxxEZ2eowjMaoflgQs4= Authentication-Results: vla1-7d66b24b62b3.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5Gn8UpBD; Fri, 05 Feb 2021 11:05:16 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/7] gpio: gpio-ep93xx: Fix single irqchip with multi gpiochips Date: Fri, 5 Feb 2021 11:05:02 +0300 Message-Id: <20210205080507.16007-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fixes the following warnings which results in interrupts disabled on port B/F: gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochips: please fix the driver. gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochips: please fix the driver. - added separate irqchip for each interrupt capable gpiochip - provided unique names for each irqchip Fixes: d2b091961510 ("gpio: ep93xx: Pass irqchip when adding gpiochip") Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index e3b5e2c37259..3c9f7233e62d 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -38,6 +38,7 @@ #define EP93XX_GPIO_F_IRQ_BASE 80 struct ep93xx_gpio_irq_chip { + struct irq_chip ic; u8 irq_offset; u8 int_unmasked; u8 int_enabled; @@ -284,9 +285,11 @@ struct ep93xx_gpio_bank { bool has_irq; bool has_hierarchical_irq; unsigned int irq_base; + const char *irq_name; }; -#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \ +#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base, \ +_irq_name) \ { \ .label = _label, \ .data = _data, \ @@ -296,20 +299,21 @@ struct ep93xx_gpio_bank { .has_irq = _has_irq, \ .has_hierarchical_irq = _has_hier, \ .irq_base = _irq_base, \ + .irq_name = _irq_name, \ } static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64, "gpio-irq-a"), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72, "gpio-irq-b"), + EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0, 0), + EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0, 0), + EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0, "gpio-irq-b"), + EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0, 0), + EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0, 0), }; static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, @@ -331,6 +335,16 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) return EP93XX_GPIO_F_IRQ_BASE + offset; } +static void ep93xx_init_irq_chip(struct irq_chip *ic, const char *irq_name) +{ + ic->name = irq_name; + ic->irq_ack = ep93xx_gpio_irq_ack; + ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack; + ic->irq_mask = ep93xx_gpio_irq_mask; + ic->irq_unmask = ep93xx_gpio_irq_unmask; + ic->irq_set_type = ep93xx_gpio_irq_type; +} + static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, @@ -352,6 +366,8 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, girq = &gc->irq; if (bank->has_irq || bank->has_hierarchical_irq) { + struct irq_chip *ic; + gc->set_config = ep93xx_gpio_set_config; egc->eic = devm_kcalloc(dev, 1, sizeof(*egc->eic), @@ -359,7 +375,9 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, if (!egc->eic) return -ENOMEM; egc->eic->irq_offset = bank->irq; - girq->chip = &ep93xx_gpio_irq_chip; + ic = &egc->eic->ic; + ep93xx_init_irq_chip(ic, bank->irq_name); + girq->chip = ic; } if (bank->has_irq) { From patchwork Fri Feb 5 08:05:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F18C433E6 for ; Fri, 5 Feb 2021 08:06:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 606C064F9B for ; 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Fri, 5 Feb 2021 11:05:17 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-2e2fe8fd096a.qloud-c.yandex.net (mxback/Yandex) with ESMTP id kq3TvhGqOL-5HI4TAcp; Fri, 05 Feb 2021 11:05:17 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512317; bh=L3i2GMpCyjFi2r2lWDiygR7hyvUJiR70+wZlbupXrw4=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=bKMBPtC1fMKSDNbS5HIRqxJIkORcpOoor9qm/DMFyEj865JxHfowdZMTIYwUQBZ/S eC2OTY13u+pF24ia9LjQT2NC6WeBSMJLdSvhWr8zBBeauxH97ZSlTwmeAzBXCyFcEc jNSDA+zJchNPm1hcTr0bfWSrkp8gSpF/dDgRGE0s= Authentication-Results: vla1-2e2fe8fd096a.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5Gn8ZJw6; Fri, 05 Feb 2021 11:05:17 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/7] gpio: gpio-ep93xx: Fix wrong irq numbers in port F Date: Fri, 5 Feb 2021 11:05:03 +0300 Message-Id: <20210205080507.16007-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Port F irq's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE. So we need to specify girq->first otherwise: "If device tree is used, then first_irq will be 0 and irqs get mapped dynamically on the fly" And that's not the thing we want. Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 3c9f7233e62d..38eeaa5c0e1e 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -426,6 +426,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; gc->to_irq = ep93xx_gpio_f_to_irq; + girq->first = EP93XX_GPIO_F_IRQ_BASE; } return devm_gpiochip_add_data(dev, gc, epg); From patchwork Fri Feb 5 08:05:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B037CC43381 for ; Fri, 5 Feb 2021 08:06:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78DFD64FB8 for ; Fri, 5 Feb 2021 08:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231316AbhBEIGE (ORCPT ); Fri, 5 Feb 2021 03:06:04 -0500 Received: from forward101o.mail.yandex.net ([37.140.190.181]:57780 "EHLO forward101o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbhBEIGC (ORCPT ); Fri, 5 Feb 2021 03:06:02 -0500 Received: from forward100q.mail.yandex.net (forward100q.mail.yandex.net [IPv6:2a02:6b8:c0e:4b:0:640:4012:bb97]) by forward101o.mail.yandex.net (Yandex) with ESMTP id 5B7D73C03740; Fri, 5 Feb 2021 11:05:18 +0300 (MSK) Received: from vla1-ae662a693c21.qloud-c.yandex.net (vla1-ae662a693c21.qloud-c.yandex.net [IPv6:2a02:6b8:c0d:2915:0:640:ae66:2a69]) by forward100q.mail.yandex.net (Yandex) with ESMTP id 575C77080009; Fri, 5 Feb 2021 11:05:18 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-ae662a693c21.qloud-c.yandex.net (mxback/Yandex) with ESMTP id iilsBm1FJI-5IHmpm7V; Fri, 05 Feb 2021 11:05:18 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512318; bh=+WtcWBh58n5WNwBJ+Z/NkhGBdSYSmclbOjEUFB/CcOE=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=ahbC8NAwD+LjDX/63GTuQdw9YYfH/toKKnlgWpEsD0B2XSymcNJw3T/G6oYG+W426 315h16PCAbsPcaxByKccKIcyYAM4BtfNZfInwFf+22qe5tSbWNCoqp+ClgbOSIVjP3 NxI7kOTPaZSXAp8RqHx+juTqhhenuyl3Z7AZ/BCg= Authentication-Results: vla1-ae662a693c21.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5Hn8rYH6; Fri, 05 Feb 2021 11:05:17 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/7] gpio: ep93xx: drop to_irq binding Date: Fri, 5 Feb 2021 11:05:04 +0300 Message-Id: <20210205080507.16007-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in driver is useless, so let's drop it. Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 38eeaa5c0e1e..6208a8010ff5 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -330,11 +330,6 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, return 0; } -static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) -{ - return EP93XX_GPIO_F_IRQ_BASE + offset; -} - static void ep93xx_init_irq_chip(struct irq_chip *ic, const char *irq_name) { ic->name = irq_name; @@ -425,7 +420,6 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, } girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - gc->to_irq = ep93xx_gpio_f_to_irq; girq->first = EP93XX_GPIO_F_IRQ_BASE; } From patchwork Fri Feb 5 08:05:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFF59C433E0 for ; Fri, 5 Feb 2021 08:13:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B771C64F99 for ; Fri, 5 Feb 2021 08:13:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231466AbhBEIG3 (ORCPT ); Fri, 5 Feb 2021 03:06:29 -0500 Received: from forward102o.mail.yandex.net ([37.140.190.182]:52882 "EHLO forward102o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231378AbhBEIGM (ORCPT ); Fri, 5 Feb 2021 03:06:12 -0500 Received: from forward102q.mail.yandex.net (forward102q.mail.yandex.net [IPv6:2a02:6b8:c0e:1ba:0:640:516:4e7d]) by forward102o.mail.yandex.net (Yandex) with ESMTP id 3BBF166837F6; Fri, 5 Feb 2021 11:05:19 +0300 (MSK) Received: from vla1-85d2a0988c40.qloud-c.yandex.net (vla1-85d2a0988c40.qloud-c.yandex.net [IPv6:2a02:6b8:c0d:511a:0:640:85d2:a098]) by forward102q.mail.yandex.net (Yandex) with ESMTP id 392D23A20010; Fri, 5 Feb 2021 11:05:19 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-85d2a0988c40.qloud-c.yandex.net (mxback/Yandex) with ESMTP id q3Bxqkxiwg-5JHiwiVJ; Fri, 05 Feb 2021 11:05:19 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512319; bh=Dp6HxZC/4K5OdVprRMjSdc4GwEMF/JOfPqAMm/0L38Y=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=HkKzNoR6SgmJX0Ld1WtB4MtOZRBehEDe03JrBUS4NIiP14GJ4JdH1ocotZrwwuyKP vHsHaOMEmL2rJkmZy0PK+dvQO0i+HyDKgvv18GxM/PIsvm+JuNQNt3SR5ZcYq6t1Z0 Heq1CshG4p8Kd21T1MyVvzjZkkQfj7t3pg9pYUW8= Authentication-Results: vla1-85d2a0988c40.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5In8Bom7; Fri, 05 Feb 2021 11:05:18 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/7] gpio: ep93xx: Fix typo s/hierarchial/hierarchical Date: Fri, 5 Feb 2021 11:05:05 +0300 Message-Id: <20210205080507.16007-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix typo in comment. Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 6208a8010ff5..d330bff4d9f9 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -398,7 +398,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, /* * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchial. + * this requires fixing the root irqchip to be hierarchical. */ girq->parent_handler = ep93xx_gpio_f_irq_handler; girq->num_parents = 8; From patchwork Fri Feb 5 08:05:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C052C433E0 for ; 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Fri, 5 Feb 2021 11:05:20 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-977d04bfd94d.qloud-c.yandex.net (mxback/Yandex) with ESMTP id VHRza60bZi-5JH01gO7; Fri, 05 Feb 2021 11:05:20 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512320; bh=dNqi01d8QzHphiScOYF0PoGYfIs0vwlJHIgHUmqjP9k=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=hL9uVhABSYCAyq5EK80SP87y1HIzpWO63eb3Biw18Gk0wMcXXYI6apOUXegSoOKvx 9Fb4ZN5xkaJvqSpxVcYHTnzoV3buHF6bym48at4nsTaVwyj9vVwUncLJXmnNWYu+P5 nPZq8/c9DBWq7MS1OlvnIUKRku/9u1ks/AlyFAoU= Authentication-Results: vla1-977d04bfd94d.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5Jn8AvRb; Fri, 05 Feb 2021 11:05:19 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/7] gpio: ep93xx: refactor ep93xx_gpio_add_bank Date: Fri, 5 Feb 2021 11:05:06 +0300 Message-Id: <20210205080507.16007-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org - replace plain numbers with girq->num_parents in devm_kcalloc - replace plain numbers with girq->num_parents for port F - refactor i - 1 to i + 1 to make loop more readable - combine getting IRQ's loop and setting handler's into single loop Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index d330bff4d9f9..41b5b1de14f6 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -380,7 +380,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, girq->parent_handler = ep93xx_gpio_ab_irq_handler; girq->num_parents = 1; - girq->parents = devm_kcalloc(dev, 1, + girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) @@ -402,15 +402,14 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, */ girq->parent_handler = ep93xx_gpio_f_irq_handler; girq->num_parents = 8; - girq->parents = devm_kcalloc(dev, 8, + girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; /* Pick resources 1..8 for these IRQs */ - for (i = 1; i <= 8; i++) - girq->parents[i - 1] = platform_get_irq(pdev, i); - for (i = 0; i < 8; i++) { + for (i = 0; i < girq->num_parents; i++) { + girq->parents[i] = platform_get_irq(pdev, i + 1); gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, From patchwork Fri Feb 5 08:05:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 377254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2BACC433E0 for ; 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Fri, 5 Feb 2021 11:05:20 +0300 (MSK) Received: from vla1-1bc5b51c612f.qloud-c.yandex.net (vla1-1bc5b51c612f.qloud-c.yandex.net [2a02:6b8:c0d:89c:0:640:1bc5:b51c]) by vla1-4e4ee944ff6b.qloud-c.yandex.net (mxback/Yandex) with ESMTP id EmakGzbKsi-5KHOfrIV; Fri, 05 Feb 2021 11:05:20 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1612512320; bh=C5tU/jiLrZmvj9xOWKPAfwt+7YcgCQ3SmmER8nQlmxc=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=DOgAfDXIHXQm6lp8n6o9EdKgZe9lkl9EYWzW9kYbNUwQcZQ86xshLa4bhC76uq/v/ smhm76sS+RpTZd3n4vkXQEaUdBf1KoOLtMcVfPtVHf4kigsdrwMvxmPYJmQ4cGiVCQ 73EUaafLOKLyU7B3hz0CiLGCRnkfJLM0fHKl6bsQ= Authentication-Results: vla1-4e4ee944ff6b.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla1-1bc5b51c612f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 8MWdPhaokU-5Kn8lqqC; Fri, 05 Feb 2021 11:05:20 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin Cc: Andy Shevchenko , Nikita Shubin , Linus Walleij , Bartosz Golaszewski , Alexander Sverdlin , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/7] gpio: ep93xx: refactor base IRQ number Date: Fri, 5 Feb 2021 11:05:07 +0300 Message-Id: <20210205080507.16007-8-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205080507.16007-1-nikita.shubin@maquefel.me> References: <20210205080507.16007-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org - use predefined constants instead of plain numbers - use provided bank IRQ number instead of defined constant for port F Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 41b5b1de14f6..252f7d765ff2 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -31,6 +31,8 @@ /* Maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ 23 +#define EP93XX_GPIO_A_IRQ_BASE 64 +#define EP93XX_GPIO_B_IRQ_BASE 72 /* * Static mapping of GPIO bank F IRQS: * F0..F7 (16..24) to irq 80..87. @@ -304,14 +306,17 @@ _irq_name) \ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64, "gpio-irq-a"), + EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, + EP93XX_GPIO_A_IRQ_BASE, "gpio-irq-a"), /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72, "gpio-irq-b"), + EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, + EP93XX_GPIO_B_IRQ_BASE, "gpio-irq-b"), EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0, 0), EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0, 0), EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0, 0), /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0, "gpio-irq-b"), + EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0, + EP93XX_GPIO_F_IRQ_BASE, "gpio-irq-b"), EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0, 0), EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0, 0), }; @@ -410,7 +415,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, /* Pick resources 1..8 for these IRQs */ for (i = 0; i < girq->num_parents; i++) { girq->parents[i] = platform_get_irq(pdev, i + 1); - gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; + gpio_irq = bank->irq_base + i; irq_set_chip_data(gpio_irq, &epg->gc[5]); irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, @@ -419,7 +424,7 @@ static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, } girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - girq->first = EP93XX_GPIO_F_IRQ_BASE; + girq->first = bank->irq_base; } return devm_gpiochip_add_data(dev, gc, epg);