From patchwork Mon Feb 8 01:26:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 378753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78369C433E9 for ; Mon, 8 Feb 2021 01:28:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45FF664E24 for ; Mon, 8 Feb 2021 01:28:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229702AbhBHB1y (ORCPT ); Sun, 7 Feb 2021 20:27:54 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:55762 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229636AbhBHB1q (ORCPT ); Sun, 7 Feb 2021 20:27:46 -0500 X-UUID: c72bcf8059bd40d5a8db221b94012885-20210208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=a310sQCUgDOdkn7zckKGWmxpMKVjRJUxcAXM3gBCOzs=; b=isS3c6eUBbRZW7knun9BxikH5cwYkulL1GIdpz7V8N23vd2E5SyaddNt91cw462j8hjgcSc68p0CHAJ+y8l6YSRZV1nAbdUEWseCMowFjz+h8zAxJ8VF1zRcXxYoSl4c4uI5t4pz7rp4jxgbMN7W3HThqt2Hpw93BQ4QVyPKPaM=; X-UUID: c72bcf8059bd40d5a8db221b94012885-20210208 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2005433819; Mon, 08 Feb 2021 09:27:01 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Feb 2021 09:26:57 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Feb 2021 09:26:56 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel CC: , , , , , , , , , , , , , , , , Jitao Shi Subject: [PATCH v2 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid Date: Mon, 8 Feb 2021 09:26:51 +0800 Message-ID: <20210208012653.196060-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208012653.196060-1-jitao.shi@mediatek.com> References: <20210208012653.196060-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 35E44BCD518AF53872D91D83AB998C84AA1C82442F38503E175707842121A90C2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.25.1 diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..ffa4a0f1989f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit { struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; + u32 max_clock_khz; bool edge_sel_en; }; @@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_set_display_mode(dpi, &dpi->mode); } +static enum drm_mode_status +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, + .mode_valid = mtk_dpi_bridge_mode_valid, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, }; @@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock) static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 300000, }; static const struct mtk_dpi_conf mt2701_conf = { .cal_factor = mt2701_calculate_factor, .reg_h_fre_con = 0xb0, .edge_sel_en = true, + .max_clock_khz = 150000, }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 100000, }; static int mtk_dpi_probe(struct platform_device *pdev) From patchwork Mon Feb 8 01:26:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 378752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B60B3C4332B for ; Mon, 8 Feb 2021 01:28:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8512064E22 for ; Mon, 8 Feb 2021 01:28:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbhBHB1y (ORCPT ); Sun, 7 Feb 2021 20:27:54 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:21290 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229618AbhBHB1q (ORCPT ); Sun, 7 Feb 2021 20:27:46 -0500 X-UUID: f78ce9460e154e3cadc416e0717d58e6-20210208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=L7LVdcpjTRLx50fmWNOp80798p9i+Ih9lUss/NrthBU=; b=jbuL3gDRN8TAtpCnbYDvSQT3QMuzPwyMioWlcJpdnU4xN4FwO3MMoFSY4vTmW8S7M45h4EYbLOGTFF/HxJ47fxl+rEh/LAs7e4dgaFZdNWrsmsERIDYJKRu3EGk/eDzCka0DOqTd6LXrBCgBDW054XEmShOa0x6PyAEth2W1xNs=; X-UUID: f78ce9460e154e3cadc416e0717d58e6-20210208 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2156666; Mon, 08 Feb 2021 09:27:01 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Feb 2021 09:26:59 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Feb 2021 09:26:58 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel CC: , , , , , , , , , , , , , , , , Jitao Shi Subject: [PATCH v2 3/3] dt-bindings: mediatek, dpi: add mt8192 to mediatek, dpi Date: Mon, 8 Feb 2021 09:26:53 +0800 Message-ID: <20210208012653.196060-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208012653.196060-1-jitao.shi@mediatek.com> References: <20210208012653.196060-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: B649D45953B1C84CB86819603152F0DA615BE01E44E72C18E594A859D23335072000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi. Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6cdb734c91a9..2f566f19e6e0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-dpi - mediatek,mt8173-dpi - mediatek,mt8183-dpi + - mediatek,mt8192-dpi reg: maxItems: 1