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[23.128.96.18]) by mx.google.com with ESMTP id t21si210241eju.452.2021.02.09.13.26.50; Tue, 09 Feb 2021 13:26:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b+p4OX1p; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234000AbhBIVZW (ORCPT + 16 others); Tue, 9 Feb 2021 16:25:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233723AbhBIUj1 (ORCPT ); Tue, 9 Feb 2021 15:39:27 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9A57C0698CF for ; Tue, 9 Feb 2021 12:28:57 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id h26so4102037lfm.1 for ; Tue, 09 Feb 2021 12:28:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xp4VsyxHOqEhAHKGKETwGM5yW+arT2DW9ndgALlXFUI=; b=b+p4OX1p9P1I1qr4wpx8uFUayUQtZ+P1yidIohv20NrhAdrOt1Fii3hjXl8NLMKTL7 kmi339UCip0vlK1fsCsX7++JKM633J+tmcsFblAaDE+dG8YBoatRDCWoRfMgYLFJxZs9 n3IRvVPFU6NqsalGXKtl2CynB6G5ObcYLS73CUkrQp2WevJEqUijTCPrEMTi2J2fsrBa UZqD7jFZzck8fhXi6JsuhMbJYLqW9CRTaFtalbgUBEnpoV80N+vQ4CfNIVhBdcEfGoBP jbODiDvZUKIiHzyduYeWxTWGphzyWHGqDSVEN0YXEk4oX/0MtDo2i0LiP5kcn2zjRsCD +WIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xp4VsyxHOqEhAHKGKETwGM5yW+arT2DW9ndgALlXFUI=; b=WfPvftOhVvAfL3Teeq//wGSIYoKVm5y3+FYJK0BeMjxlFB86z01EsxqJ961zGQ3n7O M/Utg2ItyZyTrSRz2QPgdyGsPZH/yveFBlZ0TcndkwBcvfDEq2fos+7w+Yjoiq2/of0x A98eAIpakRfTa2UKb0dRMywS5riEzr7VbrKIgGH2AG+R8W46HiQZcDGVSFD9p9TZir8m mb3XYHBJ/Bf2fDOAnpJmeHxD5YNqaxfS4DABdvs1aThxpibrCmkmsWWR/i8BqoarTLUD ZqFUSHNoO229ijGRxXPUD4fsznHK/u01jSlfcrkjnMIYuBaTBu09E8f0BCk2otdQozVF qIFQ== X-Gm-Message-State: AOAM531eO6PnDTpit8ZCWcrPRNRbF9BrYfIVFzMgaZUKEgzDVt9Aca0w KCsZPw+p8OnLqCx/MLP5y2U1dg== X-Received: by 2002:a05:6512:130f:: with SMTP id x15mr14295414lfu.259.1612902536271; Tue, 09 Feb 2021 12:28:56 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id o19sm2680449lfu.182.2021.02.09.12.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 12:28:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Date: Tue, 9 Feb 2021 23:28:46 +0300 Message-Id: <20210209202849.1148569-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209202849.1148569-1-dmitry.baryshkov@linaro.org> References: <20210209202849.1148569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As discussed on linux-arm-msm list, start splitting sm8250 pinctrl settings into generic and board-specific parts. The first part to receive such treatment is the spi, so split spi pinconf to the board device tree. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 300 +++++------------------ 2 files changed, 65 insertions(+), 240 deletions(-) -- 2.30.0 Reviewed-by: Douglas Anderson diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2f0528d01299..787da8ccba54 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,6 +815,11 @@ &pm8150_rtc { status = "okay"; }; +&qup_spi0_default { + drive-strength = <6>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..51d103671759 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2984,303 +2984,123 @@ config { }; qup_spi0_default: qup-spi0-default { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "qup0"; }; qup_spi1_default: qup-spi1-default { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup1"; }; qup_spi2_default: qup-spi2-default { - mux { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio115", "gpio116", + "gpio117", "gpio118"; + function = "qup2"; }; qup_spi3_default: qup-spi3-default { - mux { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio119", "gpio120", + "gpio121", "gpio122"; + function = "qup3"; }; qup_spi4_default: qup-spi4-default { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup4"; }; qup_spi5_default: qup-spi5-default { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "qup5"; }; qup_spi6_default: qup-spi6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup6"; }; qup_spi7_default: qup-spi7-default { - mux { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup7"; }; qup_spi8_default: qup-spi8-default { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup8"; }; qup_spi9_default: qup-spi9-default { - mux { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio125", "gpio126", + "gpio127", "gpio128"; + function = "qup9"; }; qup_spi10_default: qup-spi10-default { - mux { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio129", "gpio130", + "gpio131", "gpio132"; + function = "qup10"; }; qup_spi11_default: qup-spi11-default { - mux { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup11"; }; qup_spi12_default: qup-spi12-default { - mux { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup12"; }; qup_spi13_default: qup-spi13-default { - mux { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup13"; }; qup_spi14_default: qup-spi14-default { - mux { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup14"; }; qup_spi15_default: qup-spi15-default { - mux { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup15"; }; qup_spi16_default: qup-spi16-default { - mux { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup16"; }; qup_spi17_default: qup-spi17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup17"; }; qup_spi18_default: qup-spi18-default { - mux { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup18"; }; qup_spi19_default: qup-spi19-default { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup19"; }; qup_uart2_default: qup-uart2-default { From patchwork Tue Feb 9 20:28:47 2021 Content-Type: text/plain; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 9 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 201 ++++++++++++++++------- 2 files changed, 148 insertions(+), 62 deletions(-) -- 2.30.0 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 787da8ccba54..922f329d623a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,7 +815,12 @@ &pm8150_rtc { status = "okay"; }; -&qup_spi0_default { +&qup_spi0_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi0_data_clk { drive-strength = <6>; bias-disable; }; @@ -957,6 +962,8 @@ codec { /* CAN */ &spi0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; can@0 { compatible = "microchip,mcp2518fd"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 51d103671759..e4320629d687 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -549,7 +549,6 @@ spi14: spi@880000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -577,7 +576,6 @@ spi15: spi@884000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -605,7 +603,6 @@ spi16: spi@888000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -633,7 +630,6 @@ spi17: spi@88c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -674,7 +670,6 @@ spi18: spi@890000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -715,7 +710,6 @@ spi19: spi@894000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -755,8 +749,6 @@ spi0: spi@980000 { reg = <0 0x00980000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -784,7 +776,6 @@ spi1: spi@984000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -812,7 +803,6 @@ spi2: spi@988000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -853,7 +843,6 @@ spi3: spi@98c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -881,7 +870,6 @@ spi4: spi@990000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -909,7 +897,6 @@ spi5: spi@994000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -937,7 +924,6 @@ spi6: spi@998000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -978,7 +964,6 @@ spi7: spi@99c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1019,7 +1004,6 @@ spi8: spi@a80000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1047,7 +1031,6 @@ spi9: spi@a84000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1075,7 +1058,6 @@ spi10: spi@a88000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1103,7 +1085,6 @@ spi11: spi@a8c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1131,7 +1112,6 @@ spi12: spi@a90000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1172,7 +1152,6 @@ spi13: spi@a94000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -2983,123 +2962,223 @@ config { }; }; - qup_spi0_default: qup-spi0-default { + qup_spi0_cs: qup-spi0-cs { + pins = "gpio31"; + function = "qup0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", - "gpio30", "gpio31"; + "gpio30"; function = "qup0"; }; - qup_spi1_default: qup-spi1-default { + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup1"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + "gpio6"; function = "qup1"; }; - qup_spi2_default: qup-spi2-default { + qup_spi2_cs: qup-spi2-cs { + pins = "gpio118"; + function = "qup2"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { pins = "gpio115", "gpio116", - "gpio117", "gpio118"; + "gpio117"; function = "qup2"; }; - qup_spi3_default: qup-spi3-default { + qup_spi3_cs: qup-spi3-cs { + pins = "gpio122"; + function = "qup3"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { pins = "gpio119", "gpio120", - "gpio121", "gpio122"; + "gpio121"; function = "qup3"; }; - qup_spi4_default: qup-spi4-default { + qup_spi4_cs: qup-spi4-cs { + pins = "gpio11"; + function = "qup4"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { pins = "gpio8", "gpio9", - "gpio10", "gpio11"; + "gpio10"; function = "qup4"; }; - qup_spi5_default: qup-spi5-default { + qup_spi5_cs: qup-spi5-cs { + pins = "gpio15"; + function = "qup5"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { pins = "gpio12", "gpio13", - "gpio14", "gpio15"; + "gpio14"; function = "qup5"; }; - qup_spi6_default: qup-spi6-default { + qup_spi6_cs: qup-spi6-cs { + pins = "gpio19"; + function = "qup6"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { pins = "gpio16", "gpio17", - "gpio18", "gpio19"; + "gpio18"; function = "qup6"; }; - qup_spi7_default: qup-spi7-default { + qup_spi7_cs: qup-spi7-cs { + pins = "gpio23"; + function = "qup7"; + }; + + qup_spi7_data_clk: qup-spi7-data-clk { pins = "gpio20", "gpio21", - "gpio22", "gpio23"; + "gpio22"; function = "qup7"; }; - qup_spi8_default: qup-spi8-default { + qup_spi8_cs: qup-spi8-cs { + pins = "gpio27"; + function = "qup8"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk { pins = "gpio24", "gpio25", - "gpio26", "gpio27"; + "gpio26"; function = "qup8"; }; - qup_spi9_default: qup-spi9-default { + qup_spi9_cs: qup-spi9-cs { + pins = "gpio128"; + function = "qup9"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { pins = "gpio125", "gpio126", - "gpio127", "gpio128"; + "gpio127"; function = "qup9"; }; - qup_spi10_default: qup-spi10-default { + qup_spi10_cs: qup-spi10-cs { + pins = "gpio132"; + function = "qup10"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { pins = "gpio129", "gpio130", - "gpio131", "gpio132"; + "gpio131"; function = "qup10"; }; - qup_spi11_default: qup-spi11-default { + qup_spi11_cs: qup-spi11-cs { + pins = "gpio63"; + function = "qup11"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { pins = "gpio60", "gpio61", - "gpio62", "gpio63"; + "gpio62"; function = "qup11"; }; - qup_spi12_default: qup-spi12-default { + qup_spi12_cs: qup-spi12-cs { + pins = "gpio35"; + function = "qup12"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { pins = "gpio32", "gpio33", - "gpio34", "gpio35"; + "gpio34"; function = "qup12"; }; - qup_spi13_default: qup-spi13-default { + qup_spi13_cs: qup-spi13-cs { + pins = "gpio39"; + function = "qup13"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { pins = "gpio36", "gpio37", - "gpio38", "gpio39"; + "gpio38"; function = "qup13"; }; - qup_spi14_default: qup-spi14-default { + qup_spi14_cs: qup-spi14-cs { + pins = "gpio43"; + function = "qup14"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { pins = "gpio40", "gpio41", - "gpio42", "gpio43"; + "gpio42"; function = "qup14"; }; - qup_spi15_default: qup-spi15-default { + qup_spi15_cs: qup-spi15-cs { + pins = "gpio47"; + function = "qup15"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { pins = "gpio44", "gpio45", - "gpio46", "gpio47"; + "gpio46"; function = "qup15"; }; - qup_spi16_default: qup-spi16-default { + qup_spi16_cs: qup-spi16-cs { + pins = "gpio51"; + function = "qup16"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk { pins = "gpio48", "gpio49", - "gpio50", "gpio51"; + "gpio50"; function = "qup16"; }; - qup_spi17_default: qup-spi17-default { + qup_spi17_cs: qup-spi17-cs { + pins = "gpio55"; + function = "qup17"; + }; + + qup_spi17_data_clk: qup-spi17-data-clk { pins = "gpio52", "gpio53", - "gpio54", "gpio55"; + "gpio54"; function = "qup17"; }; - qup_spi18_default: qup-spi18-default { + qup_spi18_cs: qup-spi18-cs { + pins = "gpio59"; + function = "qup18"; + }; + + qup_spi18_data_clk: qup-spi18-data-clk { pins = "gpio56", "gpio57", - "gpio58", "gpio59"; + "gpio58"; function = "qup18"; }; - qup_spi19_default: qup-spi19-default { + qup_spi19_cs: qup-spi19-cs { + pins = "gpio3"; + function = "qup19"; + }; + + qup_spi19_data_clk: qup-spi19-data-clk { pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + "gpio2"; function = "qup19"; }; From patchwork Tue Feb 9 20:28:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 379385 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp575123jah; 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Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) -- 2.30.0 Reviewed-by: Douglas Anderson diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e4320629d687..0874350f66fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2967,6 +2967,11 @@ qup_spi0_cs: qup-spi0-cs { function = "qup0"; }; + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pins = "gpio31"; + function = "gpio"; + }; + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", "gpio30"; @@ -2978,6 +2983,11 @@ qup_spi1_cs: qup-spi1-cs { function = "qup1"; }; + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pins = "gpio7"; + function = "gpio"; + }; + qup_spi1_data_clk: qup-spi1-data-clk { pins = "gpio4", "gpio5", "gpio6"; @@ -2989,6 +2999,11 @@ qup_spi2_cs: qup-spi2-cs { function = "qup2"; }; + qup_spi2_cs_gpio: qup-spi2-cs-gpio { + pins = "gpio118"; + function = "gpio"; + }; + qup_spi2_data_clk: qup-spi2-data-clk { pins = "gpio115", "gpio116", "gpio117"; @@ -3000,6 +3015,11 @@ qup_spi3_cs: qup-spi3-cs { function = "qup3"; }; + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pins = "gpio122"; + function = "gpio"; + }; + qup_spi3_data_clk: qup-spi3-data-clk { pins = "gpio119", "gpio120", "gpio121"; @@ -3011,6 +3031,11 @@ qup_spi4_cs: qup-spi4-cs { function = "qup4"; }; + qup_spi4_cs_gpio: qup-spi4-cs-gpio { + pins = "gpio11"; + function = "gpio"; + }; + qup_spi4_data_clk: qup-spi4-data-clk { pins = "gpio8", "gpio9", "gpio10"; @@ -3022,6 +3047,11 @@ qup_spi5_cs: qup-spi5-cs { function = "qup5"; }; + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pins = "gpio15"; + function = "gpio"; + }; + qup_spi5_data_clk: qup-spi5-data-clk { pins = "gpio12", "gpio13", "gpio14"; @@ -3033,6 +3063,11 @@ qup_spi6_cs: qup-spi6-cs { function = "qup6"; }; + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pins = "gpio19"; + function = "gpio"; + }; + qup_spi6_data_clk: qup-spi6-data-clk { pins = "gpio16", "gpio17", "gpio18"; @@ -3044,6 +3079,11 @@ qup_spi7_cs: qup-spi7-cs { function = "qup7"; }; + qup_spi7_cs_gpio: qup-spi7-cs-gpio { + pins = "gpio23"; + function = "gpio"; + }; + qup_spi7_data_clk: qup-spi7-data-clk { pins = "gpio20", "gpio21", "gpio22"; @@ -3055,6 +3095,11 @@ qup_spi8_cs: qup-spi8-cs { function = "qup8"; }; + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pins = "gpio27"; + function = "gpio"; + }; + qup_spi8_data_clk: qup-spi8-data-clk { pins = "gpio24", "gpio25", "gpio26"; @@ -3066,6 +3111,11 @@ qup_spi9_cs: qup-spi9-cs { function = "qup9"; }; + qup_spi9_cs_gpio: qup-spi9-cs-gpio { + pins = "gpio128"; + function = "gpio"; + }; + qup_spi9_data_clk: qup-spi9-data-clk { pins = "gpio125", "gpio126", "gpio127"; @@ -3077,6 +3127,11 @@ qup_spi10_cs: qup-spi10-cs { function = "qup10"; }; + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pins = "gpio132"; + function = "gpio"; + }; + qup_spi10_data_clk: qup-spi10-data-clk { pins = "gpio129", "gpio130", "gpio131"; @@ -3088,6 +3143,11 @@ qup_spi11_cs: qup-spi11-cs { function = "qup11"; }; + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pins = "gpio63"; + function = "gpio"; + }; + qup_spi11_data_clk: qup-spi11-data-clk { pins = "gpio60", "gpio61", "gpio62"; @@ -3099,6 +3159,11 @@ qup_spi12_cs: qup-spi12-cs { function = "qup12"; }; + qup_spi12_cs_gpio: qup-spi12-cs-gpio { + pins = "gpio35"; + function = "gpio"; + }; + qup_spi12_data_clk: qup-spi12-data-clk { pins = "gpio32", "gpio33", "gpio34"; @@ -3110,6 +3175,11 @@ qup_spi13_cs: qup-spi13-cs { function = "qup13"; }; + qup_spi13_cs_gpio: qup-spi13-cs-gpio { + pins = "gpio39"; + function = "gpio"; + }; + qup_spi13_data_clk: qup-spi13-data-clk { pins = "gpio36", "gpio37", "gpio38"; @@ -3121,6 +3191,11 @@ qup_spi14_cs: qup-spi14-cs { function = "qup14"; }; + qup_spi14_cs_gpio: qup-spi14-cs-gpio { + pins = "gpio43"; + function = "gpio"; + }; + qup_spi14_data_clk: qup-spi14-data-clk { pins = "gpio40", "gpio41", "gpio42"; @@ -3132,6 +3207,11 @@ qup_spi15_cs: qup-spi15-cs { function = "qup15"; }; + qup_spi15_cs_gpio: qup-spi15-cs-gpio { + pins = "gpio47"; + function = "gpio"; + }; + qup_spi15_data_clk: qup-spi15-data-clk { pins = "gpio44", "gpio45", "gpio46"; @@ -3143,6 +3223,11 @@ qup_spi16_cs: qup-spi16-cs { function = "qup16"; }; + qup_spi16_cs_gpio: qup-spi16-cs-gpio { + pins = "gpio51"; + function = "gpio"; + }; + qup_spi16_data_clk: qup-spi16-data-clk { pins = "gpio48", "gpio49", "gpio50"; @@ -3154,6 +3239,11 @@ qup_spi17_cs: qup-spi17-cs { function = "qup17"; }; + qup_spi17_cs_gpio: qup-spi17-cs-gpio { + pins = "gpio55"; + function = "gpio"; + }; + qup_spi17_data_clk: qup-spi17-data-clk { pins = "gpio52", "gpio53", "gpio54"; @@ -3165,6 +3255,11 @@ qup_spi18_cs: qup-spi18-cs { function = "qup18"; }; + qup_spi18_cs_gpio: qup-spi18-cs-gpio { + pins = "gpio59"; + function = "gpio"; + }; + qup_spi18_data_clk: qup-spi18-data-clk { pins = "gpio56", "gpio57", "gpio58"; @@ -3176,6 +3271,11 @@ qup_spi19_cs: qup-spi19-cs { function = "qup19"; }; + qup_spi19_cs_gpio: qup-spi19-cs-gpio { + pins = "gpio3"; + function = "gpio"; + }; + qup_spi19_data_clk: qup-spi19-data-clk { pins = "gpio0", "gpio1", "gpio2"; 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[23.128.96.18]) by mx.google.com with ESMTP id x1si15152990eds.502.2021.02.09.12.49.15; Tue, 09 Feb 2021 12:49:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AjJtABr2; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233277AbhBIUrV (ORCPT + 16 others); Tue, 9 Feb 2021 15:47:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233823AbhBIUjm (ORCPT ); Tue, 9 Feb 2021 15:39:42 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBFA5C0698D2 for ; Tue, 9 Feb 2021 12:29:01 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id f1so30423362lfu.3 for ; Tue, 09 Feb 2021 12:29:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6OxpCi4/ew0z4JtIeTxbcNZX4otnbAgHcS0KslAEtyg=; b=AjJtABr2CUrHE5SzrGNhAZLssHLpD3gFc11wcoYbY+Fzgmv0H5HrcUsWY+Sd8j6+6m OdxLy/hQx1oAi8rnlywCpVwrKx75CBjPk1PiAOhUHmWEQxWaEiJCRnIFEXBQ1+KKhUMp ugfBUDB2Bbj+WHdl7PcN41t/2oqN6bmV9LQA8yMXhcsOk/R4Ra6nGoH8gbib31GdZhxo wZjpQNcpduT34Y6l0T2z1vTlu8HpWaA2iO1PFkbXflddCrqW5xf9aG5xZb0FFJ+92ZnO PDRlVvCuBzJwWdEkjw5x7tO5gCGcTBEilwOEB8cfabqdntHf32Wwn5pUoKudA3/O3kWB BXtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6OxpCi4/ew0z4JtIeTxbcNZX4otnbAgHcS0KslAEtyg=; b=o+Vu8xrNNZS1QogJ+MApipoFI2RfCTVETPmUs1CUhhuRFovacD6P9P0hQT+aoSsNyx 3Cp5rJtobCYdngZLMU32QRTJZw4sgam/CujWpXBm1u1QnVQ9nqzFH2jhwmo7Jmr6BIPn FQWqPH/BqPpyEQGIa7ynfK1qvzwC5mIURiPwkAJZbwThMmmaaJ25LspDUGBjeTQgD8Pd xX7jaHASog3vufW+0818FMUieDzOdEm5ZU1ooFBSeiFkDZ97mUz3qKQCDVQhzum0Euyp iv+r3VxDEOpJBFn4gA3vI8ChHZSjhYaKPs4d/wcsrXzSWP/8GSLshr6uXuG2D/bI5tXE 15UA== X-Gm-Message-State: AOAM531D0k3DMnd8Gq8ba82uf2znjc6zwlmPszX7n/NhUqb6dIyC8MfI nEuMr62KfmYAOxY1iNdS+g+gmA== X-Received: by 2002:a19:ad0a:: with SMTP id t10mr14502263lfc.471.1612902540296; Tue, 09 Feb 2021 12:29:00 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id o19sm2680449lfu.182.2021.02.09.12.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 12:28:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Date: Tue, 9 Feb 2021 23:28:49 +0300 Message-Id: <20210209202849.1148569-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209202849.1148569-1-dmitry.baryshkov@linaro.org> References: <20210209202849.1148569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.30.0 Reviewed-by: Douglas Anderson diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 922f329d623a..d329829c61fa 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,7 +815,7 @@ &pm8150_rtc { status = "okay"; }; -&qup_spi0_cs { +&qup_spi0_cs_gpio { drive-strength = <6>; bias-disable; }; @@ -963,7 +963,8 @@ codec { &spi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2518fd";