From patchwork Wed Feb 10 16:16:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 380232 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1301689jah; Wed, 10 Feb 2021 08:18:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiY25WTwmSHf3z8E0m3SuYWNwfCYHOVwVhe0Tr2O1P3JVR63cntZm9Yu1uUNLlcGHEz7vq X-Received: by 2002:a17:906:1796:: with SMTP id t22mr3602281eje.372.1612973928235; Wed, 10 Feb 2021 08:18:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612973928; cv=none; d=google.com; s=arc-20160816; b=byoHqyzGYE0hpwxrWa9ELcGrJMb+DujDqvN8u+gWZEzpWMAfpYseMzkcnMl6f5AWA+ 8FlSHzdvehOvaFqSgy8s5dDx2xh8uxxG5M9hDYfN6S/plqM+LMU3IhMOGllDoDn+LWGx Vx08O39F03zkx0At4D27u56vvEE1t8lPDTA/5icqBVG7TVDmY43ltosWKGjr+BB3JeHd 9r16G0EcABdNLVhsMTVsnJB6W/ZaIi3gj4tlkxPm1eSjLL//AKxSa3W5b6LmPfW7GNV6 0ftWCHnZA0o7xs/hsLa6EhPnOwa6+O/Dz9/cnBkWeHmZYTsJ8N84iMvNjv6sK+9sN/on vpvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=gNY9ffkXQMuYzV0gRWTsGZlQ3EmsDMsCNudbXBfUF0U=; b=nLr3pXbJT10t6mERLyfOfbhAovYlhyKQ08eVaB97PWjlbglI1imc+PGkTVXc5uTkJJ Ltnk80wISfg31DRqj57pf3AWcTw4XztPU1hnnW2osBHokoR0f8u5BchtBAE0dm+1QMSh v2KeZC1aw3trsx6IKFSES77JueOmpOsancKT7IytNQGfLOir8X80xgwYhiHVM18El4au GnTbwm8oA4yvi/LJ73znZ7j6UzFaEbhdJtom6n+9dnh5GIgmeSwDnCPYaM98CLhtXfR+ +7haVGTvY1n78lTZlroEkFUdWH9X/4cBDtgWO2I4IjvumCoZxqEG7PoeiEC835SFh1W5 Y8Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Y0XyTvfr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 10 Feb 2021 16:16:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612973820; bh=hh4UIkJdtViE9hIUqy2HP352No8PkABh6qI6Cce0cZI=; h=From:To:Cc:Subject:Date:From; b=Y0XyTvfrhIwcX/ppb49PkzQCYxWXkGOEC5KujWcwQziC033w4IUoJ7IP5Gje3b8RK 1qWyy5fi6A4/l5c38FstWJSoQjQvLXvsjtGH3wZWQmjtGPKkMyIye2OW52T3+M5nx9 qg6yFU4d3E/XKy0rxPesbQCl4kQc3pdITqXzfJuhiXeWza+qjX9cg6eQab/Uo9oUwX sm5Q9rRLiMwvdfx/YipLKMIkLRQ71tvkwaqWihjTweMtJgiXgARPLmT/5eAKwanOZa wojusx2hbVfr3HIe6nXGWrVS5rxBOADCFwNsnb6SWI5CPH/s1gS/kIUA5KWoFD+bt4 P2kZoh+e8tjMA== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH] clk: qcom: gcc-sm8350: add gdsc Date: Wed, 10 Feb 2021 21:46:49 +0530 Message-Id: <20210210161649.431741-1-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the GDSC found in GCC for SM8350 SoC Signed-off-by: Vinod Koul --- drivers/clk/qcom/gcc-sm8350.c | 100 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8350.h | 12 +++ 2 files changed, 112 insertions(+) -- 2.26.2 diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index a16c08651206..1c23b9f84900 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -16,6 +16,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -3452,6 +3453,90 @@ static struct clk_branch gcc_video_axi1_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x6b004, + .pd = { + .name = "pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x8d004, + .pd = { + .name = "pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_card_gdsc = { + .gdscr = 0x75004, + .pd = { + .name = "ufs_card_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_phy_gdsc = { + .gdscr = 0x77004, + .pd = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0xf004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_sec_gdsc = { + .gdscr = 0x10004, + .pd = { + .name = "usb30_sec_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { + .gdscr = 0x7d050, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { + .gdscr = 0x7d058, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { + .gdscr = 0x7d054, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { + .gdscr = 0x7d06c, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + static struct clk_regmap *gcc_sm8350_clocks[] = { [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, @@ -3646,6 +3731,19 @@ static struct clk_regmap *gcc_sm8350_clocks[] = { [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, }; +static struct gdsc *gcc_sm8350_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, + [UFS_CARD_GDSC] = &ufs_card_gdsc, + [UFS_PHY_GDSC] = &ufs_phy_gdsc, + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, + [USB30_SEC_GDSC] = &usb30_sec_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, +}; + static const struct qcom_reset_map gcc_sm8350_resets[] = { [GCC_CAMERA_BCR] = { 0x26000 }, [GCC_DISPLAY_BCR] = { 0x27000 }, @@ -3724,6 +3822,8 @@ static const struct qcom_cc_desc gcc_sm8350_desc = { .num_clks = ARRAY_SIZE(gcc_sm8350_clocks), .resets = gcc_sm8350_resets, .num_resets = ARRAY_SIZE(gcc_sm8350_resets), + .gdscs = gcc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs), }; static const struct of_device_id gcc_sm8350_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-sm8350.h b/include/dt-bindings/clock/qcom,gcc-sm8350.h index 1331da65f669..f6be3da5f781 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8350.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8350.h @@ -251,4 +251,16 @@ #define GCC_VIDEO_AXI1_CLK_ARES 36 #define GCC_VIDEO_BCR 37 +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9 + #endif