From patchwork Mon Mar 19 18:34:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132074 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3053001ljb; Mon, 19 Mar 2018 11:37:45 -0700 (PDT) X-Google-Smtp-Source: AG47ELu1DY1eXorTsQqW6EpQRflbva0N5POVO1HE+TmBC9nPIfilKuLMb6DVu3wbSqdkd6QKszhO X-Received: by 10.200.27.135 with SMTP id z7mr19563555qtj.294.1521484665048; Mon, 19 Mar 2018 11:37:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484665; cv=none; d=google.com; s=arc-20160816; b=JzoxpSUW5An6FioGS7nrzWl8M5DG/8hALmsLiT9sgVYmWV0+UZbnD3FfFPnMccQudd HQQFUFIHzLHikaSFAq9bKuuxQYYDbfB2noFgChbQajXpkfc/Kz18SbNj1OUSrGEHPYTl pPod1XzS57ptoHHAL/hhjZKTmJThC/zP9bTGXHQfiJsLn30x235EMp1p92T+GhQ6Szvw CiDPZtOke3CEFw8lucrtOoVzYbOZiMvZn70ESYSvBP42Phd7pnjRveL1PfPchpmZ/8Rk +6luw3xj+whkCkIn0yXSGEp+VHB+ogJ8PXWk2FYjyDLS0KUTecqrmtZRDNHfpeXo6fIh SsZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=T1Wjg1Z0Kc/l6/QoDkGmGPQUvApoMSBjLQ6cUwSlJ5M=; b=Ycgl1ON0N+tmpcvVhqGj+i5CNcjF6uNLuYRzxtsY4qy6EpOH4UUr55WKPNpMmiOIII eLaLNtv08O44dMZ6WkFaxE7qULtd0y+ttRdjmHVplW+0cuWJBzdwgXxXUsepNUo+mv0p PXYtfouChHVsojb2eak8X2IEvTT7jWtkZpBP9zPiqlHDTcZEpKVyUE+0Z4xQgqi54BxF B3a1QLEgVFNGiWLoXmmFiXP4RFd33WfMzKVECfkXtL4UO8G9MK/ES/zxeFmq+W1C+m1W x74ZPTus5keGxIs45KB/UYGrhVc6JBkIqgGaZH8JExf2TVm8dwJ4HMRgL9ikJdi7d5oD lAuA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c42si663199qtc.107.2018.03.19.11.37.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:37:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzfE-0004mu-C1 for patch@linaro.org; Mon, 19 Mar 2018 14:37:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzbx-0002JO-9x for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbv-0007dD-UA for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbv-0007bM-NF for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:19 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbt-0002yt-Rq for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:03 +0000 Message-Id: <20180319183415.1976-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck The sabrelite machine model used by qemu-system-arm is based on the Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet controller which is supported in QEMU using the imx_fec.c module (actually called imx.enet for this model.) The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the imx.enet device like this: #define FSL_IMX6_ENET_MAC_1588_IRQ 118 #define FSL_IMX6_ENET_MAC_IRQ 119 According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary, interrupts are as follows. 150 ENET MAC 0 IRQ 151 ENET MAC 0 1588 Timer interrupt where 150 - 32 == 118 151 - 32 == 119 In other words, the vector definitions in the fsl-imx6.h file are reversed. Fixing the interrupts alone causes problems with older Linux kernels: The Ethernet interface will fail to probe with Linux v4.9 and earlier. Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe error handling. This is a Linux kernel problem, not a qemu problem: the Linux kernel only worked by accident since it requested both interrupts. For backward compatibility, generate the Ethernet interrupt on both interrupt lines. This was shown to work from all Linux kernel releases starting with v3.16. Link: https://bugs.launchpad.net/qemu/+bug/1753309 Signed-off-by: Guenter Roeck Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6.h | 4 ++-- hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 3 deletions(-) -- 2.16.2 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index ec6c509d74..06f8aaeda4 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -438,8 +438,8 @@ typedef struct FslIMX6State { #define FSL_IMX6_HDMI_MASTER_IRQ 115 #define FSL_IMX6_HDMI_CEC_IRQ 116 #define FSL_IMX6_MLB150_LOW_IRQ 117 -#define FSL_IMX6_ENET_MAC_1588_IRQ 118 -#define FSL_IMX6_ENET_MAC_IRQ 119 +#define FSL_IMX6_ENET_MAC_IRQ 118 +#define FSL_IMX6_ENET_MAC_1588_IRQ 119 #define FSL_IMX6_PCIE1_IRQ 120 #define FSL_IMX6_PCIE2_IRQ 121 #define FSL_IMX6_PCIE3_IRQ 122 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 9506f9b69f..6e297c5480 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -417,7 +417,33 @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) static void imx_eth_update(IMXFECState *s) { - if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { + /* + * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER + * interrupts swapped. This worked with older versions of Linux (4.14 + * and older) since Linux associated both interrupt lines with Ethernet + * MAC interrupts. Specifically, + * - Linux 4.15 and later have separate interrupt handlers for the MAC and + * timer interrupts. Those versions of Linux fail with versions of QEMU + * with swapped interrupt assignments. + * - In linux 4.14, both interrupt lines were registered with the Ethernet + * MAC interrupt handler. As a result, all versions of qemu happen to + * work, though that is accidental. + * - In Linux 4.9 and older, the timer interrupt was registered directly + * with the Ethernet MAC interrupt handler. The MAC interrupt was + * redirected to a GPIO interrupt to work around erratum ERR006687. + * This was implemented using the SOC's IOMUX block. In qemu, this GPIO + * interrupt never fired since IOMUX is currently not supported in qemu. + * Linux instead received MAC interrupts on the timer interrupt. + * As a result, qemu versions with the swapped interrupt assignment work, + * albeit accidentally, but qemu versions with the correct interrupt + * assignment fail. + * + * To ensure that all versions of Linux work, generate ENET_INT_MAC + * interrrupts on both interrupt lines. This should be changed if and when + * qemu supports IOMUX. + */ + if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & + (ENET_INT_MAC | ENET_INT_TS_TIMER)) { qemu_set_irq(s->irq[1], 1); } else { qemu_set_irq(s->irq[1], 0); From patchwork Mon Mar 19 18:34:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132073 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3052607ljb; Mon, 19 Mar 2018 11:37:21 -0700 (PDT) X-Google-Smtp-Source: AG47ELutLYs1JuJf0xhJQI+cKSUWw91YGfxbgeckDp4STdNUDFDcTvW8X4d69OElovCI/J2Rw993 X-Received: by 10.55.17.34 with SMTP id b34mr8193184qkh.343.1521484640957; Mon, 19 Mar 2018 11:37:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484640; cv=none; d=google.com; s=arc-20160816; b=HXvYWF1SsCi26v5uG8oU2nPUko7EF/2a6FNZx+FiAO6ZOZAZ9UJWU3cQaMkyOOtjHg /yjTlYYkqo6+Goc2PSgJ/I88hK+yD+DCESGwY+OyX+liP+Y6E5eN1QVNRkqwGjMfIVmw faQdW2eHymBh5ATeDio1akwQSMW2L22lYJKs4g2+MwBeBh+NqZFwd9nI9tAUNZOnYF2s xl+L9PYtp0O3wVNEIWWMB/klFawHSkiGxNvMGCjYs13HLwgf+2+ZJkTWaeD+u/uhhcGF 9ZVXUrNm97qnl9EiuDrhQzIJ3LSt7mjYNFtuutU1KeBFlnib0HbsFOi0Qq+wyZIAun+6 ocyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=a6/t8EEwCu99EjeSMM5+I4fD3EtE16iNcXu0t5LskoI=; b=wkJzVqbw3w0PCDkmeRjhNp8Cv9tjpPXT3nMlyfVGyd35DWaDHlOwacLV4CA/ZU2u1t 9OgAI1gAAhuvKTuRch5P3YxK/Cbz5AgtCO28rFBgTfts9jan2D6hx3Bknwwx57Yq9CNn 3W7VspH3QHTtesd7Ajq/khMDH8gAkMk0rjV6mE5FOC5uywimWoI0Z9EPzZ6WKe5W4i/d hfTb+JmOUz22CHT1JmfElMX5j2idmnfSL/004gyK1YfnGddFAf2bdwA36XEwREmHWFWK WJ+eAkPutHDYNs4WPQnbNY8hn9Q2kGoYkF6ns12MpQA8WJGfS76L0tLlDj5j/NTY1xBE cCCg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p30si681674qtl.65.2018.03.19.11.37.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:37:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43365 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzeq-0003bX-33 for patch@linaro.org; Mon, 19 Mar 2018 14:37:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49687) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzbx-0002JX-Ou for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbw-0007dp-TV for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbw-0007bM-LP for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbu-0002zP-Sz for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:18 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:04 +0000 Message-Id: <20180319183415.1976-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Wei Huang For guest kernel that supports KASLR, the load address can change every time when guest VM runs. To find the physical base address correctly, current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=". However this string pattern is only available on x86_64. AArch64 uses a different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure QEMU dump uses the correct string on AArch64. Signed-off-by: Wei Huang Reviewed-by: Marc-André Lureau Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell --- dump.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.16.2 diff --git a/dump.c b/dump.c index 097e60b2b3..6bdb0dbe23 100644 --- a/dump.c +++ b/dump.c @@ -1609,10 +1609,18 @@ static void vmcoreinfo_update_phys_base(DumpState *s) lines = g_strsplit((char *)vmci, "\n", -1); for (i = 0; lines[i]; i++) { - if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) { - if (qemu_strtou64(lines[i] + 18, NULL, 16, + const char *prefix = NULL; + + if (s->dump_info.d_machine == EM_X86_64) { + prefix = "NUMBER(phys_base)="; + } else if (s->dump_info.d_machine == EM_AARCH64) { + prefix = "NUMBER(PHYS_OFFSET)="; + } + + if (prefix && g_str_has_prefix(lines[i], prefix)) { + if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16, &phys_base) < 0) { - warn_report("Failed to read NUMBER(phys_base)="); + warn_report("Failed to read %s", prefix); } else { s->dump_info.phys_base = phys_base; } From patchwork Mon Mar 19 18:34:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132075 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3053076ljb; Mon, 19 Mar 2018 11:37:51 -0700 (PDT) X-Google-Smtp-Source: AG47ELtNJrrX3RjJviMNYQD2tpwRUKSWiE4rMnJ32iyZ0kifY1YW+iZdZmAIywJIMfxTYYA95G0s X-Received: by 10.237.56.105 with SMTP id j96mr4295093qte.258.1521484671071; Mon, 19 Mar 2018 11:37:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484671; cv=none; d=google.com; s=arc-20160816; b=gH3TiuBIfzOLuSvdEDJIFUzBGPSPugwsTTvP63SaUH9LBcLKn3zwgkHcqtwuSqmb+M KAwgFApxD+UT0wS9eq3zT9L8+kxBd0dfIX2+sUkNB+DClYsIroz/bbS421h/G9t9j02A vgEUiV+T+EECNfrk+rEJ0pIZUOJNwbVXvNtX97ZPh7jY0wNJnTrEF3Po2nLQaC/3AzRu KkKrOy9ZNQ+RvH91H0KCCVAaiZ+70fKmgtdbYpsBZhCOWLATDuLH/lKvKIDGLnjBES5m FVukXUvMl+r+xLtYNrSGIyyP2iOpHxQ8ej8/h7YEIeQwvRTbPmIcl2DDSESozolASgbg 1eWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=/gozRclWi5v7Oy+56OKFXskFIkPWhSw4ojXmdRvQApA=; b=PuK/13oaT33FPTDJ6g7+WepJDpLtugSiA4R/1tQe71Eml7AaG4l1Mb3chG1j/3E65/ dx7cfVdok0xYodALYKzLn+GoVpMo4jeTiCpqEnMSPsrmmMyl/B2alwWquxobH1FyiHfl DU62OuS97yi5PxeQUICHxvpS1rVQXJgZpAxNyvqy5dXRxcIijYlyLsph3jO01DTBLZwk 5FqxMqjgL4/H9TqxFeubWnwU1JjeyGk3bcL1XindqVm/ZwMPOOo6oj9ubLoueS6Ogort kDUBt7jHwb5AgyDtNIrtxs8EZPvPjvNdiHzAaV1jdv+lSbmZw77b/ofld0sqvEXxyPfY rqrA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j126si631453qkj.142.2018.03.19.11.37.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:37:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzfK-0004su-Bl for patch@linaro.org; Mon, 19 Mar 2018 14:37:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzbx-0002Jc-RK for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbw-0007dZ-RH for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40456) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbw-0007dJ-K9 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbv-0002zt-Ka for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:19 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:05 +0000 Message-Id: <20180319183415.1976-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrey Smirnov Code of imx_update() is slightly confusing since the "flags" variable doesn't really corespond to anything in real hardware and server as a kitchensink accumulating events normally reported via USR1 and USR2 registers. Change the code to explicitly evaluate state of interrupts reported via USR1 and USR2 against corresponding masking bits and use the to detemine if IRQ line should be asserted or not. NOTE: Check for UTS1_TXEMPTY being set has been dropped for two reasons: 1. Emulation code implements a single character FIFO, so this flag will always be set since characters are trasmitted as a part of the code emulating "push" into the FIFO 2. imx_update() is really just a function doing ORing and maksing of reported events, so checking for UTS1_TXEMPTY should happen, if it's ever really needed should probably happen outside of it. Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: Bill Paul Cc: Peter Maydell Signed-off-by: Andrey Smirnov Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/char/imx_serial.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 2.16.2 diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 70405ccf8b..d1e8586280 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -56,16 +56,24 @@ static const VMStateDescription vmstate_imx_serial = { static void imx_update(IMXSerialState *s) { - uint32_t flags; + uint32_t usr1; + uint32_t usr2; + uint32_t mask; - flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); - if (s->ucr1 & UCR1_TXMPTYEN) { - flags |= (s->uts1 & UTS1_TXEMPTY); - } else { - flags &= ~USR1_TRDY; - } + /* + * Lucky for us TRDY and RRDY has the same offset in both USR1 and + * UCR1, so we can get away with something as simple as the + * following: + */ + usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); + /* + * Bits that we want in USR2 are not as conveniently laid out, + * unfortunately. + */ + mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; + usr2 = s->usr2 & mask; - qemu_set_irq(s->irq, !!flags); + qemu_set_irq(s->irq, usr1 || usr2); } static void imx_serial_reset(IMXSerialState *s) From patchwork Mon Mar 19 18:34:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132071 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3050328ljb; Mon, 19 Mar 2018 11:35:00 -0700 (PDT) X-Google-Smtp-Source: AG47ELvBdtM2/JIJA0Wqv8AKBq4Yz0zvkB+AZScn9BKe/vqSqLKwnOOR6ZtwtulH88fQa5NTGsR+ X-Received: by 10.200.6.6 with SMTP id d6mr18799046qth.112.1521484499973; Mon, 19 Mar 2018 11:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484499; cv=none; d=google.com; s=arc-20160816; b=MAd3tJsJYYBDiOewuuSEgardK6FsHwrpLzmmCdkZD/rNkOC2P9NRolgd95XZl9PWux l7wL5HNthRtE4C+XdxyhE3VKmGA/nORjg1t9IGjuFJHnmcpmBL5AgrX0UJkSojLFYPnQ fXMg2HjjkOYIhjuFw5kxc1tbLPKJqjl9zRNuev0rybsLyQSIR/2tvin5lAKh0/1bIAHg m6l05FjZ8WZo+1pnPWBtCj1iil/1JeZkGT9ynkNwcDGvagQwDaZub6gKyU+j9Rdmiauv DH7dpML97MXziFLUVW44sNckT+mL1x722+22XMaeJJQtOdjriN64dVMogMxWq3S5Flrd E+Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=DU+E3oCrZy2IbrZE19NRenO6K5JolCNgf7fJVZnrDu0=; b=rowmMv+8LnEmA0+Ai79oLenXOzneETE9XlxHTEI56AERrt+ivvFPwqwhCyVJ7GojwH mRDPMXdpdxcemzh/ZjMXVkMmjvw0Ox+rqXAF/gpZit9vL9EtIIN7AfUElqZ2P4Jl6yIQ gpdX53f6BLcJgHDUGfZ+dZH4Fydp2RjGZRVW+Fgi0wo87yNLn5fuvtOgpZVE1hdKVsYY KSULBk94hybLbFHr4B1mv3oNGjMFxtkBD2k6U0VBfwFahQTTV0ltT9/w8Uf92J6bxcV7 Jlp7aNRtWzzBXILrMHvvFEwvciPSxGPmiva6RqP5LYeIWiKhKj+Dpnhs6y1B3HFTRIC+ 7okg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e36si663882qtk.99.2018.03.19.11.34.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:34:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43357 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzcZ-0002Ob-BI for patch@linaro.org; Mon, 19 Mar 2018 14:34:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzbz-0002Kq-95 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbx-0007f3-Px for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40456) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbx-0007dJ-In for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:21 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbw-00030A-DL for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:20 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:06 +0000 Message-Id: <20180319183415.1976-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrey Smirnov Add support for "TX complete"/TXDC interrupt generate by real HW since it is needed to support guests other than Linux. Based on the patch by Bill Paul as found here: https://bugs.launchpad.net/qemu/+bug/1753314 Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: Bill Paul Cc: Peter Maydell Signed-off-by: Bill Paul Signed-off-by: Andrey Smirnov Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/char/imx_serial.h | 3 +++ hw/char/imx_serial.c | 20 +++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) -- 2.16.2 diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index baeec3183f..5b99cee7cf 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -67,6 +67,8 @@ #define UCR2_RXEN (1<<1) /* Receiver enable */ #define UCR2_SRST (1<<0) /* Reset complete */ +#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ + #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5) #define UTS1_TXFULL (1<<4) @@ -95,6 +97,7 @@ typedef struct IMXSerialState { uint32_t ubmr; uint32_t ubrc; uint32_t ucr3; + uint32_t ucr4; qemu_irq irq; CharBackend chr; diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index d1e8586280..1e5540472b 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -37,8 +37,8 @@ static const VMStateDescription vmstate_imx_serial = { .name = TYPE_IMX_SERIAL, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_INT32(readbuff, IMXSerialState), VMSTATE_UINT32(usr1, IMXSerialState), @@ -50,6 +50,7 @@ static const VMStateDescription vmstate_imx_serial = { VMSTATE_UINT32(ubmr, IMXSerialState), VMSTATE_UINT32(ubrc, IMXSerialState), VMSTATE_UINT32(ucr3, IMXSerialState), + VMSTATE_UINT32(ucr4, IMXSerialState), VMSTATE_END_OF_LIST() }, }; @@ -71,6 +72,11 @@ static void imx_update(IMXSerialState *s) * unfortunately. */ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; + /* + * TCEN and TXDC are both bit 3 + */ + mask |= s->ucr4 & UCR4_TCEN; + usr2 = s->usr2 & mask; qemu_set_irq(s->irq, usr1 || usr2); @@ -163,6 +169,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, return s->ucr3; case 0x23: /* UCR4 */ + return s->ucr4; + case 0x29: /* BRM Incremental */ return 0x0; /* TODO */ @@ -191,8 +199,10 @@ static void imx_serial_write(void *opaque, hwaddr offset, * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); s->usr1 &= ~USR1_TRDY; + s->usr2 &= ~USR2_TXDC; imx_update(s); s->usr1 |= USR1_TRDY; + s->usr2 |= USR2_TXDC; imx_update(s); } break; @@ -265,8 +275,12 @@ static void imx_serial_write(void *opaque, hwaddr offset, s->ucr3 = value & 0xffff; break; - case 0x2d: /* UTS1 */ case 0x23: /* UCR4 */ + s->ucr4 = value & 0xffff; + imx_update(s); + break; + + case 0x2d: /* UTS1 */ qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); /* TODO */ From patchwork Mon Mar 19 18:34:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132078 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3056981ljb; Mon, 19 Mar 2018 11:42:27 -0700 (PDT) X-Google-Smtp-Source: AG47ELsHm9kaSRRssALyw9oQVwWauvFonbOQIwrtQzdOtvkjfHxFs6P7U9E1BPTJ1ujcq+uvkAtR X-Received: by 10.237.53.97 with SMTP id b30mr20451072qte.230.1521484947144; Mon, 19 Mar 2018 11:42:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484947; cv=none; d=google.com; s=arc-20160816; b=aco96YD4Fhotsn3nSHotiGfe07u1r/UNZnXLRIx1VjU0G++j8FI8mu6aDD20KKfx30 oR7heUoccOYBc9lsdm2wfQlKp2Bs0dK9h1ZTpdIWyLbpktcmbiEQ9ekba0PVMTfTD/My p6oHMn3tHoAsDEz07eVEsrmtmMs0l7eb5txdgAf+oWz/ZOoiyfo9izMJWxJAJOTkSXWW AA5keJwRSsKqa/L9iIKgI1TYQPROHvqdfDtCb9jdrJ/W1BthMn9uZiZZmzt66aCUklsY IbvCxQkdjffwhylLFDPBRkVs7V3G5uqI3wondt1z3a7lsdoDoZPaT4HRUmtK+1UU7mGn rKVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=yBvwHf1yUpi8VnvN8D2G1KYFfsfunWbBYVh/WATG0R4=; b=LuDSsln9sGZiD/IDEPf2OGhLXac4R8jhskkj/fsuFz/7G9V+c9ifQa5r5ERQ5PBC7j MTJwsVNTaTotDJ/NgbmQeHOAJB++L2jFKW+z+rQMO6Z/q4xHAj3EZxeemQl/aGx8UO9/ JRfsLWMtP7N9ihuXX0DIrUKJRBF4mwxUmeS9qSpr3AAxNMWxuPZGL2A4fnQ5aeanlKIm 5dBaoeF926mVGyvRDt91F/580cjy8iDiARowUbnGXS0d3zEktzB2cCP0hfu7I0Mdga4V zyf2XTkdlLXhIUJJrIBMNSNhgB4hVyxm17OMY/0ED6kQW4wI8yYjh2jb4hhtngZtLgLb nJsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n66si674364qkd.18.2018.03.19.11.42.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:42:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43396 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzjm-0008KZ-JK for patch@linaro.org; Mon, 19 Mar 2018 14:42:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzbz-0002Kh-4d for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzby-0007fV-9e for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzby-0007eR-2p for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbx-00030v-4K for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:21 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:07 +0000 Message-Id: <20180319183415.1976-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the rpi1 and 2 we want to boot the Linux kernel via some custom setup code that makes sure that the SMC instruction acts as a no-op, because it's used for cache maintenance. The rpi3 boots AArch64 kernels, which don't need SMC for cache maintenance and always expect to be booted non-secure. Don't fill in the aarch32-specific parts of the binfo struct. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-2-peter.maydell@linaro.org --- hw/arm/raspi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.16.2 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a37881433c..1ac0737149 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -82,10 +82,19 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) binfo.board_id = raspi_boardid[version]; binfo.ram_size = ram_size; binfo.nb_cpus = smp_cpus; - binfo.board_setup_addr = BOARDSETUP_ADDR; - binfo.write_board_setup = write_board_setup; - binfo.secure_board_setup = true; - binfo.secure_boot = true; + + if (version <= 2) { + /* The rpi1 and 2 require some custom setup code to run in Secure + * mode before booting a kernel (to set up the SMC vectors so + * that we get a no-op SMC; this is used by Linux to call the + * firmware for some cache maintenance operations. + * The rpi3 doesn't need this. + */ + binfo.board_setup_addr = BOARDSETUP_ADDR; + binfo.write_board_setup = write_board_setup; + binfo.secure_board_setup = true; + binfo.secure_boot = true; + } /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { From patchwork Mon Mar 19 18:34:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132077 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3055103ljb; Mon, 19 Mar 2018 11:40:20 -0700 (PDT) X-Google-Smtp-Source: AG47ELu32GEJEQJNQUiMrh5KLsoyjZt8FiLgL6Jve41zRNqhV9hU5QJ73k+9gmAVhSkB3Wmi6zgW X-Received: by 10.200.34.245 with SMTP id g50mr18802011qta.93.1521484820633; Mon, 19 Mar 2018 11:40:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484820; cv=none; d=google.com; s=arc-20160816; b=OLqkXrBcyfYwF+WkPvJAIttvBrP9dToHSv5I0Z/GIIHQAHKd6ChuvovXtwBypU+iZv 17Mba+ib79co3w+JKNmGJ1BBPnXYmGlDPwsXCjqf9NgB3jkwDrk3wrdFm+VhbmA6RMxI PgWCJAOgTDslf68ihq5Aizze9EuKuVS/LOcESWkFrPrLBr83QrydHk+/92/bojQxR8VH shbLmhcNcmOn9VWCXuvVHIhTkbpf/k+nl4dxhK9hAJX+jsj5R3S/O6bKyEBpbX1FkMIy gZZBTUUbcK5e1mmPWUdG2k9V1iOivuxO+iQ8iflOWA9+pUOs0v5/mFxb321ECTSa7WkG zy8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=fnW5g5Rf0REJNUjr7BZvgiPHDCdhrXgoBi2Nzda7/WU=; b=NGrVRcLb5TjLDeGT4xS0wpUGjA/rRKyeMDRnPlu5+MVu4TCoXMx40ktHvYYZPfvOXb F4mPekOzAZwpQ1esDMp1muOrEAYVUNbBlpEFerXXGVj1/0/Z7Qadj/kJbHGHQfJmSqtG L6Wu0viOLiAnZRK+N+6ROL+AH83860gt0eQHm5E0kvaJWdG6kGCaaqiA2borFfRcMsaq jOVdIym1j0qj2GPH/gX59evFsm6PZ2S8N2losWvMyMRyZ8h8WJNYeTFcqqqtnwdS8FWc Xnv5sWUwNi4Lvs5RK8SZiL4hhbLxab6yTTKIHF9CY0MyXNZ4YQb6n/4RTa5+fNYrLHTa ocBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 134si642587qki.271.2018.03.19.11.40.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:40:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzhk-0006B8-1R for patch@linaro.org; Mon, 19 Mar 2018 14:40:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49734) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc0-0002LI-2Q for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbz-0007gg-6q for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzby-0007eR-Vr for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbx-00031A-SY for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:21 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:08 +0000 Message-Id: <20180319183415.1976-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add some assertions that if we're about to boot an AArch64 kernel, the board code has not mistakenly set either secure_boot or secure_board_setup. It doesn't make sense to set secure_boot, because all AArch64 kernels must be booted in non-secure mode. It might in theory make sense to set secure_board_setup, but we don't currently support that, because only the AArch32 bootloader[] code calls this hook; bootloader_aarch64[] does not. Since we don't have a current need for this functionality, just assert that we don't try to use it. If it's needed we'll add it later. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-3-peter.maydell@linaro.org --- hw/arm/boot.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.16.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 196c7fb242..e21a92f972 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -720,6 +720,13 @@ static void do_cpu_reset(void *opaque) } else { env->pstate = PSTATE_MODE_EL1h; } + /* AArch64 kernels never boot in secure mode */ + assert(!info->secure_boot); + /* This hook is only supported for AArch32 currently: + * bootloader_aarch64[] will not call the hook, and + * the code above has already dropped us into EL2 or EL1. + */ + assert(!info->secure_board_setup); } /* Set to non-secure if not a secure boot */ From patchwork Mon Mar 19 18:34:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132081 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3058370ljb; Mon, 19 Mar 2018 11:44:08 -0700 (PDT) X-Google-Smtp-Source: AG47ELu/ZG4I+tXD0PO4Iv2+ft4u5OwSi8tXjW+BSPzD3jYh/dzbBFRjSgF1Pt+xmykvogCYoArJ X-Received: by 10.55.154.139 with SMTP id c133mr19397917qke.76.1521485048412; Mon, 19 Mar 2018 11:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521485048; cv=none; d=google.com; s=arc-20160816; b=X2D8J4rcOV/43UG72A7DmPiYwmrlS1rvSGnbq6Jxmou+57feadgkZKZsM11uCXw6T6 2jDYlKmED2RNhrba1mxpBTJWhUjUeEfnoHyTaAhl61fC1mfEZYm7FaVMbj4macI2G1zW SOM7mHv8xDi8XbKlShCJ5HBfswRXwC7wRTEBwZxoEXY+7Y708gC0mikOtmwAEgFIbMUy j2szvXmuURD5cS5fNGjMTBwkSXvFI760JfS8eZ5MPxx0AktNbDQOPca5H/k1lg3g16FV SO6JfmiK2ITBG7BwElmlESk7m56f47j4kbF/GNqjl6CQ9ipxiBfHcKjnYVr8eaB+NNs7 0G0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=Wfm9F9FyqqrQkSv2KgRVes0YDkj8cTzTrl9onIG0ZsE=; b=uDTn3qqhrZeaEfwCNTEWR2isarkpcDHrOdoX2cgoQZ414kU5trX69whCjV2et4WTlX 7C2sKVLkrxcKV57A6d/K4BVjCl2n9IkgTENyTPcPXY1t1IvPm9O3Ni9gNhj/R7b1M9qv wmJJjFSJLwsciJPvLUxpoaP5b2bnk1XERTGMOkN5Rqt/wbrd9DJakrnJZs5hha4+B+XY mXVL+Psp3yjBeU0j4ZP5KUORdBydvjCqFuCYSyJWjy3krSBMcljKgEsskK+OuwdP6ulv UD15oFZt3t95fA8iKWeofBheiF9FW8gI/2wIlVe0P0LnOEXGVYoAaGwH/bw+xA+asfaY kKmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 38si628253qtg.435.2018.03.19.11.44.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:44:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzlP-0001Tp-Ue for patch@linaro.org; Mon, 19 Mar 2018 14:44:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc0-0002Ll-J0 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzbz-0007h7-Ov for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40460) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzbz-0007gJ-Hl for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzby-00031q-IQ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:09 +0000 Message-Id: <20180319183415.1976-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell Message-id: 20180313153458.26822-4-peter.maydell@linaro.org --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.16.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e21a92f972..9319b12fcd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs != first_cpu || !info->secure_board_setup)) { From patchwork Mon Mar 19 18:34:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132072 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3050341ljb; Mon, 19 Mar 2018 11:35:00 -0700 (PDT) X-Google-Smtp-Source: AG47ELvimxQdvGeYXMhAi92MBo4TcS5+Iq/E64GrkqmjaGnEOmr+WyenX+Z4yhOJL8cpft1dsoSe X-Received: by 10.55.167.23 with SMTP id q23mr3981117qke.329.1521484500656; Mon, 19 Mar 2018 11:35:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484500; cv=none; d=google.com; s=arc-20160816; b=0PNW+xXYFYUxjioAABEWQY9gOvx2bmjf9K6op/tIcv7nOaEHm60rzUkxbsV0T2i3UA YjvxRpIP5bXyXn9XWYDL8SAnmE0LWLlRnSR5UN9yd/+8wMsl7n4275VgmtAEyr7zxcgP J5R+JfyQgQvsKEwdAAP0uSfPwP1RNCW7P0hZGkq9z/+W30BsH5WCPn62D8aFYH363uWY SJjIGDrTS3kJKBQLjGMFUK3M4jYXFlViBY+ZEsJ/gpcxeuwNc522hBG3ceTaeWoO5Woj oLM67ngDfMZUGfHVL3sWACYhTFFXs8mvG8ecgQiVV5bmsz+5SnVO4QjW3jNkO6F90eqx gULg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=sh8KN84537w8DehmLZ/Sny3H98zxh5gKgWzQOAMoaro=; b=aYJ7OhwXLshD2PsDX2yRkDgVkhSTJCP8dxYr6lKDwK89Deg+ytA07Kay9W1ttnincE 4jNAXx8YTz4x/HMuFS1vL88UQEPrEoDV/8d/SyaEtKOS4nzg6nXO69p+r44YALCzIGZa uEsIXkvjtzCm/NhYqfrG8AQ9HgsnH11PMoZBbl8dAO7QBb2+gekA81fyF5B1ctGggdsS VL3sP5hU0LDz2kCvxXp3Ql8B2nWbXykXLNr3RR8JtzXqSfL6+2tKgqV9YqCuuqzFev4r PrXPyNU1C2bkHrkI2aTlcqpw4Vh9hwG9tM93ql2L8D8PDEt+m/Hp08hdNGlRPdJe+la8 WEFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e51si663233qtf.27.2018.03.19.11.35.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:35:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzcZ-0002PX-TF for patch@linaro.org; Mon, 19 Mar 2018 14:34:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc1-0002Mw-HZ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc0-0007iB-MZ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40460) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc0-0007gJ-G5 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzbz-000325-A6 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:23 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:10 +0000 Message-Id: <20180319183415.1976-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The TypeInfo and state struct for bcm2386 disagree about what the parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, but the BCM2386State struct only defines the parent_obj field as DeviceState. This would have caused problems if anything actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't need any of the additional functionality TYPE_SYS_BUS_DEVICE provides. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-5-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.16.2 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 40e8b25a46..9266f27c14 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -165,7 +165,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) static const TypeInfo bcm2836_type_info = { .name = TYPE_BCM2836, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_DEVICE, .instance_size = sizeof(BCM2836State), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, From patchwork Mon Mar 19 18:34:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132080 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3057102ljb; Mon, 19 Mar 2018 11:42:36 -0700 (PDT) X-Google-Smtp-Source: AG47ELuhreTEP3kmLbkk7YNWfbtTJX1B2FnOXe8tRVr6Giw9F7tQuVAx5lc8BeA5PO55xGqwvZHJ X-Received: by 10.55.119.1 with SMTP id s1mr19236928qkc.3.1521484956113; Mon, 19 Mar 2018 11:42:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484956; cv=none; d=google.com; s=arc-20160816; b=UEapKHhgI+r7aWLFZajYwlyfLhwFPkCXz4WGkrEInln8JHm1/pqGLRAOTCMlszNs71 WwSE9QZ8umORRZZWMe6UaQVZn2zHTlY3eYwndYNPsp/9ucUiwvs0x+lJZp6OtHGWBuuS c49z9Ph/o6eqhAVcYJd2xXH8b5leVbfJALeXy3fE9oko4ZhnZ8G/9hzqHKGA8mq6a/wh TvfPG9nBcYRGMZYivR+fSrra6VJZG4vZRz8XeanybRZQ6G4Bv7Yb2dRTJlGu2UF05cvP 6LpLJPkEeKEOM3KzvZAAoY43/lrztoHcvjCPMwd2TNvAiCUTbslOD2IwCTfWC+ffbDxh gR/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=j6+2HyRehjNIg/DTYvlJfEJhH2smMbIctXs3rne3Hdc=; b=AsMesdUhLEwLP227468Sy8P1BpoHWcqXhtv6xly4kjzeCTn7LSt+v6zis0G8vPQHWZ vIMm1M3dOmz8M+lBvRqxpbjk5BZ1QEK5qbO/RKd2bqpEgLgd33Lut/dYivmnIyKKFTiv PXAnaS3YOUNUh512+wUby7Cud9MhYkD+h2Ar5kVpETtFHvobDcSM8Az3MnfMtIMzAclc UNWu8CeNa+DWrLa9wIeAmpRL3KaOqL0sMU9JMO3ASFZkVxVj1UuQ1wL+542kcl4e/Mpx kXgjJ+EwK2o30bCSQ9CHIJDtV5Sy8rdJyGw3BJ/0dRpA4l/k6w3HYqAjjLLmDsTFK87f 05jw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b185si107539qkd.386.2018.03.19.11.42.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:42:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzjv-0008TZ-H3 for patch@linaro.org; Mon, 19 Mar 2018 14:42:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc2-0002Ns-Ey for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc1-0007ib-8k for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40462) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc1-0007hw-0S for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzc0-00032l-1J for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:11 +0000 Message-Id: <20180319183415.1976-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Our BCM2836 type is really a generic one that can be any of the bcm283x family. Rename it accordingly. We change only the names which are visible via the header file to the rest of the QEMU code, leaving private function names in bcm2836.c as they are. This is a preliminary to making bcm283x be an abstract parent class to specific types for the bcm2836 and bcm2837. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-6-peter.maydell@linaro.org --- include/hw/arm/bcm2836.h | 12 ++++++------ hw/arm/bcm2836.c | 17 +++++++++-------- hw/arm/raspi.c | 16 ++++++++-------- 3 files changed, 23 insertions(+), 22 deletions(-) -- 2.16.2 diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 4758b4ae54..9a10a76631 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -15,12 +15,12 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#define TYPE_BCM2836 "bcm2836" -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) +#define TYPE_BCM283X "bcm283x" +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) -#define BCM2836_NCPUS 4 +#define BCM283X_NCPUS 4 -typedef struct BCM2836State { +typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -28,9 +28,9 @@ typedef struct BCM2836State { char *cpu_type; uint32_t enabled_cpus; - ARMCPU cpus[BCM2836_NCPUS]; + ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; -} BCM2836State; +} BCM283XState; #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 9266f27c14..1d1908654b 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,7 +25,7 @@ static void bcm2836_init(Object *obj) { - BCM2836State *s = BCM2836(obj); + BCM283XState *s = BCM283X(obj); object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -44,7 +44,7 @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { - BCM2836State *s = BCM2836(dev); + BCM283XState *s = BCM283X(dev); Object *obj; Error *err = NULL; int n; @@ -52,7 +52,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ obj = OBJECT(dev); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { object_initialize(&s->cpus[n], sizeof(s->cpus[n]), s->cpu_type); object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), @@ -102,7 +102,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ @@ -150,8 +150,9 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, + BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() }; @@ -164,9 +165,9 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) } static const TypeInfo bcm2836_type_info = { - .name = TYPE_BCM2836, + .name = TYPE_BCM283X, .parent = TYPE_DEVICE, - .instance_size = sizeof(BCM2836State), + .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 1ac0737149..58c6e80a17 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -32,7 +32,7 @@ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; typedef struct RasPiState { - BCM2836State soc; + BCM283XState soc; MemoryRegion ram; } RasPiState; @@ -136,7 +136,7 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); @@ -189,9 +189,9 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; mc->ignore_memory_transaction_failures = true; }; @@ -212,9 +212,9 @@ static void raspi3_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; } DEFINE_MACHINE("raspi3", raspi3_machine_init) From patchwork Mon Mar 19 18:34:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132076 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3053149ljb; Mon, 19 Mar 2018 11:37:56 -0700 (PDT) X-Google-Smtp-Source: AG47ELuAvK4HQM+0jAskmLj6eDDLcf1hioNP+mxL+k26W0tHdMhzLQrVOBMX/X0+0e0hOEV+gLhV X-Received: by 10.200.63.6 with SMTP id c6mr20064843qtk.286.1521484676799; Mon, 19 Mar 2018 11:37:56 -0700 (PDT) ARC-Seal: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id j14si625870qkk.201.2018.03.19.11.37.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:37:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzfQ-0004yX-7C for patch@linaro.org; Mon, 19 Mar 2018 14:37:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc3-0002Oh-DE for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc2-0007ju-8Q for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40462) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc1-0007hw-Vw for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzc0-000330-P3 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:12 +0000 Message-Id: <20180319183415.1976-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The bcm2837 is pretty similar to the bcm2836, but it does have some differences. Notably, the MPIDR affinity aff1 values it sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 uses, and if this is wrong Linux will not boot. Rather than trying to have one device with properties that configure it differently for the two cases, create two separate QOM devices for the two SoCs. We use the same approach as hw/arm/aspeed_soc.c and share code and have a data table that might differ per-SoC. For the moment the two types don't actually have different behaviour. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-7-peter.maydell@linaro.org --- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- hw/arm/raspi.c | 3 ++- 3 files changed, 53 insertions(+), 6 deletions(-) -- 2.16.2 diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 9a10a76631..93248399ba 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -20,6 +20,13 @@ #define BCM283X_NCPUS 4 +/* These type names are for specific SoCs; other than instantiating + * them, code using these devices should always handle them via the + * BCM283x base class, so they have no BCM2836(obj) etc macros. + */ +#define TYPE_BCM2836 "bcm2836" +#define TYPE_BCM2837 "bcm2837" + typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; @@ -33,4 +40,16 @@ typedef struct BCM283XState { BCM2835PeripheralState peripherals; } BCM283XState; +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + DeviceClass parent_class; + const BCM283XInfo *info; +} BCM283XClass; + +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1d1908654b..07d2705f96 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -23,6 +23,19 @@ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ #define BCM2836_CONTROL_BASE 0x40000000 +struct BCM283XInfo { + const char *name; +}; + +static const BCM283XInfo bcm283x_socs[] = { + { + .name = TYPE_BCM2836, + }, + { + .name = TYPE_BCM2837, + }, +}; + static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); @@ -156,25 +169,39 @@ static Property bcm2836_props[] = { DEFINE_PROP_END_OF_LIST() }; -static void bcm2836_class_init(ObjectClass *oc, void *data) +static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); - dc->props = bcm2836_props; + bc->info = data; dc->realize = bcm2836_realize; + dc->props = bcm2836_props; } -static const TypeInfo bcm2836_type_info = { +static const TypeInfo bcm283x_type_info = { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, - .class_init = bcm2836_class_init, + .class_size = sizeof(BCM283XClass), + .abstract = true, }; static void bcm2836_register_types(void) { - type_register_static(&bcm2836_type_info); + int i; + + type_register_static(&bcm283x_type_info); + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { + TypeInfo ti = { + .name = bcm283x_socs[i].name, + .parent = TYPE_BCM283X, + .class_init = bcm283x_class_init, + .class_data = (void *) &bcm283x_socs[i], + }; + type_register(&ti); + } } type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 58c6e80a17..f588720138 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -136,7 +136,8 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); + object_initialize(&s->soc, sizeof(s->soc), + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); From patchwork Mon Mar 19 18:34:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132079 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3057054ljb; Mon, 19 Mar 2018 11:42:33 -0700 (PDT) X-Google-Smtp-Source: AG47ELutPN0vT5BWw05FGGxsy97pdvmyDsz1Lr0xxnIrrJniT1qCmx1r+p/G2DrQaMTCYMGSvZd7 X-Received: by 10.55.164.136 with SMTP id n130mr19202135qke.13.1521484952928; Mon, 19 Mar 2018 11:42:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521484952; cv=none; d=google.com; s=arc-20160816; b=i2VKYh8gOCM2S6DzKR6tZxdrZKVJ7WJ4i+oEG2U73E6viZHyCEHiOaor3ttyyGo8Iq g5esFqCwYXPSm+JnvYpDgiWJyp0r2HBEAeOETukwfGQ0Ig6Yxlabkq0ASrQn1tr9lwbc XxDYIHoCYtSvXy6Y/ALs602eBDyavON1JWjz1cAqkWq17bgeru5g33g1xWG3SXaMmmqw /FVgOyKsUEdLPnUwG0v2auCuu3MlNVofUgXEWF8mpZPHQJ2vM1PcfBeQ9bk9Y91/QB6z yG7lyB7RjBcyEDT9yTGQlkXYcDeheSiKe69sd+1wfCFbV0xiJ9P6hGGDIOdSmfH5UpQ4 wn4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=h+dUmkA1hv1t11JeVE4detdh5mLiMfEcVOD7WWjmMn4=; b=AoB8QIzRIPZrVtLfY7KKofJCtE4beq3Ijd62AfmuLzLQ/Z/Y8n8SoC0hyGEgSJgll7 W5IkkNvJqAXVkosbO3zdH4ho98GyNp2+a72LSy64Q40kLxRiukcGvtWxphr7C9IFUInK 7r74fxf9wbfKX5VJvmcBJbQtUlD2BwWtiNi+v1YTI5HUP+HnlRHw3Z8FBbL4AH0nGs7k XVkigZjBGitxX2mUPvhy3EOXTxjDyXWAB1CTTFLyBoDO3zNsTmbhVIP/3nfysn+ckXKC ZGOdRdqm3yXxrtCcIU19zLKBDdrACLpCZFecwh9ccjDqkHlPc2k7acwohBNTWMHRQZH1 7Ucw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o18si671143qtk.140.2018.03.19.11.42.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:42:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzjs-0008RK-8g for patch@linaro.org; Mon, 19 Mar 2018 14:42:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc3-0002Ov-K7 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc2-0007kt-Mu for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40464) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc2-0007jV-GY for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzc1-00033f-Hg for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:13 +0000 Message-Id: <20180319183415.1976-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The BCM2837 sets the Aff1 field of the MPIDR affinity values for the CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it is required for Linux to boot. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-8-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.16.2 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 07d2705f96..d775a33969 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,14 +25,17 @@ struct BCM283XInfo { const char *name; + int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .clusterid = 0xf, }, { .name = TYPE_BCM2837, + .clusterid = 0x0, }, }; @@ -58,6 +61,8 @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); + BCM283XClass *bc = BCM283X_GET_CLASS(dev); + const BCM283XInfo *info = bc->info; Object *obj; Error *err = NULL; int n; @@ -116,10 +121,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); for (n = 0; n < BCM283X_NCPUS; n++) { - /* Mirror bcm2836, which has clusterid set to 0xf - * TODO: this should be converted to a property of ARM_CPU - */ - s->cpus[n].mp_affinity = 0xF00 | n; + /* TODO: this should be converted to a property of ARM_CPU */ + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), From patchwork Mon Mar 19 18:34:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132082 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3059170ljb; Mon, 19 Mar 2018 11:45:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELv+4tSCqZKEuwDa1seWl7JwLQDYptzocED8Zn/63t+83EpZvIC/PnhJgDdV7vBVTkJ6PqNi X-Received: by 10.55.131.1 with SMTP id f1mr18498579qkd.160.1521485106098; Mon, 19 Mar 2018 11:45:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521485106; cv=none; d=google.com; s=arc-20160816; b=jCzYYaNiDKHyfqy3x9t8Wokp00cxOW92kqHub4oxa65N1GjHxBUd9ox5446c7SVJus o4LH+4qIn+UwEZsiJLehfosrANQhTedb0kNQX+per2Klv6aX+SCGIedRAKU+GXZOVE1g enHTE0LctegSeeVJRE1ecJda7P+AnhQkxt32VBjSNH1A0lleK9OE6tXRQJGQ85Oi6qrD d2yCqbuy2i5s4v8jK5FWEOLZvUvzsqN+4BIXGvMKAZho7dTH/mmjPp2vI1UrtvWWELZt R/k6BEhdMQ5alUgXyGayaahOCoZapWX8pcRTH8LuYnoxOXsFRHH7bnv3RoG8xH2zRUiE WxdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=UaH9XOtyuvaTvywKVBDShTBWqmf25C8BPIf4wkRLTsQ=; b=liPh70Az6ADdvn4TbvMFwQ8uYb8soYXK7VoprDPzINVIJDxpqUTAUfScWyPBnI5jBS ylpuJavpn3EqCWzb/lKmS38CyXB5S05SKgk5Wo2ommAW/oNY+oKcFnZEnPmqnc6d0PdB xWpD9U/tQiFCvTQwarqTu2fGatirc2qPJxnhtnWZWJd5qU8BDDhgNQfRi1H+3z211AHh WfyiDfGs7zxSoqsbl1kWgKsY1GopQEqHyV7nHxUrSVjM+AYDjlC5PV0iJN4SNiL3G3I3 Gp8J+03rLRSuUnlqcsfvRrVCz6NSv3GiuBV6U3ZOTOQ3LtwkLb92PvoPR5U0+AUgQgCi CEYw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q189si635547qkb.310.2018.03.19.11.45.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:45:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43419 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzmL-0002er-FP for patch@linaro.org; Mon, 19 Mar 2018 14:45:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc4-0002Q3-OB for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc3-0007lw-MS for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40464) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc3-0007jV-Ee for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzc2-00033u-AN for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:14 +0000 Message-Id: <20180319183415.1976-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we have separate types for BCM2386 and BCM2387, we might as well just hard-code the CPU type they use rather than having it passed through as an object property. This then lets us put the initialization of the CPU object in init rather than realize. Note that this change means that it's no longer possible on the command line to use -cpu to ask for a different kind of CPU than the SoC supports. This was never a supported thing to do anyway; we were just not sanity-checking the command line. This does require us to only build the bcm2837 object on TARGET_AARCH64 configs, since otherwise it won't instantiate due to the missing cortex-a53 device and "make check" will fail. Signed-off-by: Peter Maydell Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-9-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 24 +++++++++++++++--------- hw/arm/raspi.c | 2 -- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.16.2 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index d775a33969..3e7e8ca791 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,23 +25,38 @@ struct BCM283XInfo { const char *name; + const char *cpu_type; int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), .clusterid = 0xf, }, +#ifdef TARGET_AARCH64 { .name = TYPE_BCM2837, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), .clusterid = 0x0, }, +#endif }; static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); + BCM283XClass *bc = BCM283X_GET_CLASS(obj); + const BCM283XInfo *info = bc->info; + int n; + + for (n = 0; n < BCM283X_NCPUS; n++) { + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), + info->cpu_type); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), + &error_abort); + } object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -69,14 +84,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ - obj = OBJECT(dev); - for (n = 0; n < BCM283X_NCPUS; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - s->cpu_type); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", @@ -166,7 +173,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index f588720138..ae15997669 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -150,8 +150,6 @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041; From patchwork Mon Mar 19 18:34:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 132083 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp3062030ljb; Mon, 19 Mar 2018 11:48:37 -0700 (PDT) X-Google-Smtp-Source: AG47ELtHDFvJy1UbXgEN+AS1laICf2mk/3b9aOw/oONHuHZGBHB7DJhhftPk8C/ToC1xLCauX0bN X-Received: by 10.200.61.90 with SMTP id u26mr19319426qtf.168.1521485316951; Mon, 19 Mar 2018 11:48:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521485316; cv=none; d=google.com; s=arc-20160816; b=zZjWaeeJQbS2dgoaCG8P3FUpiTcGAKGDq4dxUiSqiIi0eRAAVm+hKa+bxXmoK9OVZg B9WSfFcwh7Gv6OYBO82wkSvGnXNsWISWHQ2pZeGobqaDj5CR7R+Lrkwo1UnxOrQfSUD6 2xcUusmJ+uNk3FQdcBH6+xSQ2NnUuId92GkrGG9A7/llBAVLOiaAlC1f/NKPK/cAegE6 HLmMjUfRfAL73HYpvGlbjkX0gyRA+dciXbMgCax/rGAv0CawPTE984eio/G0i5vmELPi eenRwNFsDD5bRN/J+3AOgPEpBHgRdqT90CpTnqjvYwRSG1UdfTFr0swdbctgPomjGHl3 4j6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=tz/MiuafIpI9TOT/oG3WeiLsw+BYkt6tRt2NEA3ytUE=; b=cL798shb4N1+gAIjYaHoVbWnSAOL9nT8IsPTwE0quWvxxa+UJXndAnFR/fVL7JXxaT E2CHnV+uiKRPmMx0ik72VtXn/cmxoRisEDtUdKHZw9OxMMPD86MG9w4uYb/WC0CeH1hD L4u5no+8Bc/3GLxET5WtoBEnMrx4qghNiDW1c9xDE+4v6iaSUldv/anbdbf9YE8Rk+Ut R4y8afer2cGNrPzCiZdwLVGwnnC4gvqzyEummOgsn5Ix7brTfL/Pe4Rl7BEEsjhbkm0/ Y43WeRaE1bbcqO+duyhX+7yLPapXTfPK8cgVoPqOmHZFbQ5JJLk43/4LflKyG1MqrKNw hXxA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d58si644465qta.483.2018.03.19.11.48.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 11:48:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzpk-0004k8-Dm for patch@linaro.org; Mon, 19 Mar 2018 14:48:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49808) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1exzc5-0002Qm-CT for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1exzc4-0007mg-8K for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:40466) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1exzc4-0007lN-0R for qemu-devel@nongnu.org; Mon, 19 Mar 2018 14:34:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1exzc3-00034Z-10 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 18:34:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 18:34:15 +0000 Message-Id: <20180319183415.1976-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org> References: <20180319183415.1976-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20180313153458.26822-10-peter.maydell@linaro.org --- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) -- 2.16.2 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index ae15997669..06f1e08ca9 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -27,6 +27,7 @@ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ /* Table of Linux board IDs for different Pi versions */ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; @@ -63,6 +64,40 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) info->smp_loader_start); } +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* Unlike the AArch32 version we don't need to call the board setup hook. + * The mechanism for doing the spin-table is also entirely different. + * We must have four 64-bit fields at absolute addresses + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for + * our CPUs, and which we must ensure are zero initialized before + * the primary CPU goes into the kernel. We put these variables inside + * a rom blob, so that the reset for ROM contents zeroes them for us. + */ + static const uint32_t smpboot[] = { + 0xd2801b05, /* mov x5, 0xd8 */ + 0xd53800a6, /* mrs x6, mpidr_el1 */ + 0x924004c6, /* and x6, x6, #0x3 */ + 0xd503205f, /* spin: wfe */ + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ + 0xb4ffffc4, /* cbz x4, spin */ + 0xd2800000, /* mov x0, #0x0 */ + 0xd2800001, /* mov x1, #0x0 */ + 0xd2800002, /* mov x2, #0x0 */ + 0xd2800003, /* mov x3, #0x0 */ + 0xd61f0080, /* br x4 */ + }; + + static const uint64_t spintables[] = { + 0, 0, 0, 0 + }; + + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR); +} + static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); @@ -99,7 +134,11 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { binfo.smp_loader_start = SMPBOOT_ADDR; - binfo.write_secondary_boot = write_smpboot; + if (version == 2) { + binfo.write_secondary_boot = write_smpboot; + } else { + binfo.write_secondary_boot = write_smpboot64; + } binfo.secondary_cpu_reset_hook = reset_secondary; }