From patchwork Sun Mar 25 11:07:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 132388 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2668845ljb; Sun, 25 Mar 2018 04:08:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELuxkKWJDTENlnVTpLyx+eOzcGKfwJPoEjqyAhxfmYojsoZ8LLh5RiacBPg8otxWcLPlYvPr X-Received: by 10.101.74.15 with SMTP id s15mr25648210pgq.382.1521976086757; Sun, 25 Mar 2018 04:08:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521976086; cv=none; d=google.com; s=arc-20160816; b=1FQyJVOo7/0fVPIZqFYdhk65cxcrF11YMVsFVEztPGz3ru1luTpaRCN72T3VHMiR9D sL0mTXTzg3czBLaQNr1vV9hObpdJwTzuohHK24Z0K3+PngIKl3ZgOCbBXAxx+nLDbzes 7alknsIjYxaPsZIulRWGhYYlV4aLfGZtjnq3scArJPgiYBd9ZSdgR9ybzw5Ox718kH5U e2Rig+3mZu8GuqPH7FioL3U2SbPgTiMLSVS9POvEaOPT94PtpNOI0V43y22jQNYe/dtJ gPG4fMZqPuDziAVjpAFI22D01UpGq6+Yoq6yiLi8INwv8TeIGqMRJaJYElVBzBk3uuDy ettQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5H7RRsVaATT8cCxp+bxpCPwKnlHRMmcG30hhwJ0kUVc=; b=gcHLaKP6jUabsBdMTszPXNj2k5E+/7pIOuY3b5ca85Ywv27l3KGIWXXWOblxtHuBZw xk0THdf1pD8+4BFeHz/DnbUd/guFYk10BeygXvjtDmepn+EhJVLNTKQ6XbaLX6R9MwzU +BDQln3meGGtXGd69QH2N/bZZIyUeLxHjKNxaX2o25Wzbs/8F3z7o7qz+FTo2O0n/7I2 0MHUYB915gwKL/ps0X8NTGHgNywoC/fmsXWGI5TPGhc2kP9Qoy7ISsarXNLLRyJ0vh8Z cMZ3EzG04E1Knkye6Phi4TedPdLwjRK1aQShWkzmglpKyq0jtzAx5Gp8eTLYlxKylEjy CYjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iuQdtX3M; spf=pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-i2c-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f8-v6si13805808pli.445.2018.03.25.04.08.06; Sun, 25 Mar 2018 04:08:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iuQdtX3M; spf=pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-i2c-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751997AbeCYLIF (ORCPT + 3 others); Sun, 25 Mar 2018 07:08:05 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:40041 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751985AbeCYLIF (ORCPT ); Sun, 25 Mar 2018 07:08:05 -0400 Received: by mail-wr0-f196.google.com with SMTP id z8so16101637wrh.7 for ; Sun, 25 Mar 2018 04:08:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5H7RRsVaATT8cCxp+bxpCPwKnlHRMmcG30hhwJ0kUVc=; b=iuQdtX3MnLir7STpPPlVQbGy+DN+daLXmevmJxpggvybproEVoU2kjK9pcSVMSJlra Ab/ifWMmZSw5BoGgAzauO6OygoFlp8IAekOJYV5oeNBNqYrU2V+jDtwCbXTSDUOHATSD yzCn815gCp3B/g1tAQzNzhmMgtclYSjs4wpNw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5H7RRsVaATT8cCxp+bxpCPwKnlHRMmcG30hhwJ0kUVc=; b=HN2tNWgQ26kxD2o0Q8wJtQvwbM7FwO4wPiAmYk9UGO48eseTsyWI2pgQUkIHjCAqlE ozZ1un/6Tv6pDwEcaQky33JcoOUrkAy5p5ro6ftjyIby7p1Fpzb0b49e8W5Kjqmf5BBb qVDesha9/9vN1PapgBy6alDwjKuvtNtPmim75HDY0xNduwU4HE0eozmU65XCF4mPM0Z+ NPIDZoSean4iuY52hKl5KsWlZNIsIteJRvQ6fFXKh/4o+WlC7pgyctxS5uUWFq3qsF0b b8nl+7kOIDUOapo213tUBeKacH5+nLJzt+yxWJ1ceG15wZWsTdMraJmWwSZixtwDMFnx 56MA== X-Gm-Message-State: AElRT7GctJkQhvZG8Hcy+2pWUG1WohIitknnYtJsdbyHB1nLUoV4SKcu nfwqhhyRAsZ/sMGHqmxr87H82w== X-Received: by 10.223.188.1 with SMTP id s1mr29588103wrg.243.1521976084114; Sun, 25 Mar 2018 04:08:04 -0700 (PDT) Received: from localhost.localdomain ([160.105.205.136]) by smtp.gmail.com with ESMTPSA id w134sm14354298wmd.45.2018.03.25.04.08.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Mar 2018 04:08:03 -0700 (PDT) From: Ard Biesheuvel To: wsa@the-dreams.de Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jassisinghbrar@gmail.com, andy.shevchenko@gmail.com, Ard Biesheuvel Subject: [PATCH v6 1/3] dt-bindings: i2c: add binding for Socionext SynQuacer I2C Date: Sun, 25 Mar 2018 12:07:45 +0100 Message-Id: <20180325110747.8852-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180325110747.8852-1-ard.biesheuvel@linaro.org> References: <20180325110747.8852-1-ard.biesheuvel@linaro.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add a binding for the I2C controller that can be found in the Socionext SynQuacer SoC. Signed-off-by: Ard Biesheuvel Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-synquacer.txt | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.15.1 diff --git a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt new file mode 100644 index 000000000000..72f4a2f0fedc --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt @@ -0,0 +1,29 @@ +Socionext SynQuacer I2C + +Required properties: +- compatible : Must be "socionext,synquacer-i2c" +- reg : Offset and length of the register set for the device +- interrupts : A single interrupt specifier +- #address-cells : Must be <1>; +- #size-cells : Must be <0>; +- clock-names : Must contain "pclk". +- clocks : Must contain an entry for each name in clock-names. + (See the common clock bindings.) + +Optional properties: +- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and + Fast modes are supported, possible values are 100000 and + 400000. + +Example : + + i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x51210000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "pclk"; + clocks = <&clk_i2c>; + clock-frequency = <400000>; + }; From patchwork Sun Mar 25 11:07:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 132390 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2668883ljb; Sun, 25 Mar 2018 04:08:10 -0700 (PDT) X-Google-Smtp-Source: AG47ELtJ84ukxhLW2Q1zDPgDN68bd1a4fHbMfE6fU5Vij/PqsKq1xNS9EO2u+VlWL3USFKY8C9m5 X-Received: by 10.98.155.137 with SMTP id e9mr20190132pfk.109.1521976090492; Sun, 25 Mar 2018 04:08:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521976090; cv=none; d=google.com; s=arc-20160816; b=Z6W8m8JZxvHPXAcw1wwFBrdNpVQr0oD1RSV0AXDY0SwPv70SSJGNXQi2BVAh34zRC1 LV6oiwLizSje/HW7AQfGHHUMrXdpCfdA2/iAJIeAPLsdT8hDdmibKwyFBj9pUYX45gfW g+1UhQmVpYOSdtn4pmf4UxMORTpd6GMc85UefW8FZ06oS3AaJgeCxytPPx0mUND3M8Rl +BYS3l3TbQKSjCb3Yb2IdXWay965p9GbvVAcRJrFb5HB53Gpkg69jn7FjcMvNfEQOp+M t4FTS1nsZUB9/5Cc/mlx9jMCjyE46C2dOlYxnvwnds3SukHUoEghLqRA1nUOb9CI0+L9 yANA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kekf3GYatUwFJ99ecFmwh8x/oXVTjmAw/iDpVG1+6dw=; b=j6AKqpYLLnhhCyu5kQqOVLDjRgbLDZvXoXInRTxzNwXoyyOMD9v0Cg05PdGg/Gwg6t d7B3Rc4lSP0Th6DOjezW1d30hzWi9lhZr0EliSFfsi5WFzGmI3szw34fbo+TDUo2pprk ex4n7D9wThafd08Qs4kRgQKY9mEdEYNPgl2XtXhMLL5nXktVdB2dyj2iq/yrcaEH5yIq 3RCZO0ywwT8ZF+VRoXrqaMhVoE+5aq0JdoGF4TGfR/HiaRfK/lozquTb2Wch6Tl36SDU Vn+Y6RWsNz9ZyMhtcyRRz7OgcDC5P2LctB3gC141KNnJIL6f/nfMbrKr/nW8AnbSCZi3 uPgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LYyNHpAt; spf=pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-i2c-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f8-v6si13805808pli.445.2018.03.25.04.08.10; Sun, 25 Mar 2018 04:08:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LYyNHpAt; spf=pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-i2c-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752005AbeCYLIJ (ORCPT + 3 others); Sun, 25 Mar 2018 07:08:09 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:33698 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751985AbeCYLII (ORCPT ); Sun, 25 Mar 2018 07:08:08 -0400 Received: by mail-wr0-f194.google.com with SMTP id z73so16127839wrb.0 for ; Sun, 25 Mar 2018 04:08:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kekf3GYatUwFJ99ecFmwh8x/oXVTjmAw/iDpVG1+6dw=; b=LYyNHpAtG26A55W9twS1+JHLLiSyhSO+/5DiIW3bZnGAraH1kCs0nDNse4v1QrXrWH akjZBOTAUfJDIZWV5wAAIbBBc2XFtpIbRZI07cBh44DSUkpXTczWfuRKSDfvooiiiHR2 2zOJ2900dmsJoLVYvGn1Ls23h5B4aya9qQIq4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kekf3GYatUwFJ99ecFmwh8x/oXVTjmAw/iDpVG1+6dw=; b=qxYfYhZW4ZugyiFfkrAdnivYzgn80Bggz5A8O+zg73RWK0PRYUiMOmGVD2h/WEhUMI uIPEqJxCbKIJDgvifhsbkTo4nL4CPIFAZVBZOy8W71BknY1IK4tW0bVDoYZtXabzOpC0 UY8jaw1hYvjYlH2HGJPIBk3R3MMaAFpqbLwNu5fIs/L/q/z/+KsaOSY2tOw5X1OAJ68s dgSg3hMIst/BNqs15Ro6zgY700J5zLew2gaXOqrH74HCtNyg/pmMmk9s/Ny4xTadWiXo NOJMcHdYIVv34yiQPJLuDbeEFa3cI0XB5eMfzFs3LqkAn7zuDSyqqQXbFUspKs4zD1Xu Fc0w== X-Gm-Message-State: AElRT7GEQDQdVBamyYNV9oQP3EuyieoEOcES20mSU8BDObmsN43Xiyo7 5qD50HYYjSEzwIN4P6Q+sXDLQQ== X-Received: by 10.223.186.75 with SMTP id t11mr21154583wrg.155.1521976086629; Sun, 25 Mar 2018 04:08:06 -0700 (PDT) Received: from localhost.localdomain ([160.105.205.136]) by smtp.gmail.com with ESMTPSA id w134sm14354298wmd.45.2018.03.25.04.08.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Mar 2018 04:08:05 -0700 (PDT) From: Ard Biesheuvel To: wsa@the-dreams.de Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jassisinghbrar@gmail.com, andy.shevchenko@gmail.com, Ard Biesheuvel Subject: [PATCH v6 2/3] i2c: add support for Socionext SynQuacer I2C controller Date: Sun, 25 Mar 2018 12:07:46 +0100 Message-Id: <20180325110747.8852-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180325110747.8852-1-ard.biesheuvel@linaro.org> References: <20180325110747.8852-1-ard.biesheuvel@linaro.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org This is a cleaned up version of the I2C controller driver for the Fujitsu F_I2C IP, which was never supported upstream, and has now been incorporated into the Socionext SynQuacer SoC. Signed-off-by: Ard Biesheuvel Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-synquacer.c | 739 ++++++++++++++++++++ 3 files changed, 750 insertions(+) -- 2.15.1 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index e2954fb86d65..56903952d364 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -997,6 +997,16 @@ config I2C_SUN6I_P2WI This interface is used to connect to specific PMIC devices (like the AXP221). +config I2C_SYNQUACER + tristate "Socionext SynQuacer I2C controller" + depends on ARCH_SYNQUACER || COMPILE_TEST + help + Say Y here to include support for the I2C controller used in some + Fujitsu and Socionext SoCs. + + This driver can also be built as a module. If so, the module + will be called i2c-synquacer. + config I2C_TEGRA tristate "NVIDIA Tegra internal I2C controller" depends on ARCH_TEGRA diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 2ce8576540a2..40ab7bfc3458 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o obj-$(CONFIG_I2C_STM32F7) += i2c-stm32f7.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o +obj-$(CONFIG_I2C_SYNQUACER) += i2c-synquacer.o obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o obj-$(CONFIG_I2C_TEGRA_BPMP) += i2c-tegra-bpmp.o obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o diff --git a/drivers/i2c/busses/i2c-synquacer.c b/drivers/i2c/busses/i2c-synquacer.c new file mode 100644 index 000000000000..800fd7befa1e --- /dev/null +++ b/drivers/i2c/busses/i2c-synquacer.c @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WAIT_PCLK(n, rate) \ + ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10) + +/* I2C register address definitions */ +#define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status +#define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control +#define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control +#define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address +#define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data +#define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS +#define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq +#define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2 + +/* I2C register bit definitions */ +#define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer +#define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address +#define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave +#define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive +#define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit +#define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost +#define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond. +#define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy + +#define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt +#define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable +#define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack. +#define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge +#define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select +#define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont. +#define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable +#define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error + +#define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel. +#define SYNQUACER_I2C_CCR_EN BIT(5) // Enable +#define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select + +#define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel. + +#define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive +#define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive +#define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status +#define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status + +/* PCLK frequency */ +#define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1) + +/* STANDARD MODE frequency */ +#define SYNQUACER_I2C_CLK_MASTER_STD(rate) \ + DIV_ROUND_UP(DIV_ROUND_UP((rate), 100000) - 2, 2) +/* FAST MODE frequency */ +#define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \ + DIV_ROUND_UP((DIV_ROUND_UP((rate), 400000) - 2) * 2, 3) + +/* (clkrate <= 18000000) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \ + ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \ + & SYNQUACER_I2C_CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00 + +/* calculate the value of CS bits in CCR register on fast mode */ +#define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \ + ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \ + & SYNQUACER_I2C_CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00 + +/* (clkrate > 18000000) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \ + ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \ + & SYNQUACER_I2C_CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \ + (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \ + & SYNQUACER_I2C_CSR_CS_MASK) + +/* calculate the value of CS bits in CCR register on fast mode */ +#define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \ + ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \ + & SYNQUACER_I2C_CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \ + (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \ + & SYNQUACER_I2C_CSR_CS_MASK) + +/* min I2C clock frequency 14M */ +#define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000) +/* max I2C clock frequency 200M */ +#define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000) +/* I2C clock frequency 18M */ +#define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000) + +#define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode +#define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode + +enum i2c_state { + STATE_IDLE, + STATE_START, + STATE_READ, + STATE_WRITE +}; + +struct synquacer_i2c { + struct completion completion; + + struct i2c_msg *msg; + u32 msg_num; + u32 msg_idx; + u32 msg_ptr; + + int irq; + struct device *dev; + void __iomem *base; + struct clk *pclk; + u32 pclkrate; + u32 speed_khz; + u32 timeout_ms; + enum i2c_state state; + struct i2c_adapter adapter; + + bool is_suspended; +}; + +static inline int is_lastmsg(struct synquacer_i2c *i2c) +{ + return i2c->msg_idx >= (i2c->msg_num - 1); +} + +static inline int is_msglast(struct synquacer_i2c *i2c) +{ + return i2c->msg_ptr == (i2c->msg->len - 1); +} + +static inline int is_msgend(struct synquacer_i2c *i2c) +{ + return i2c->msg_ptr >= i2c->msg->len; +} + +static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c, + struct i2c_msg *msgs, + int num) +{ + unsigned long bit_count = 0; + int i; + + for (i = 0; i < num; i++, msgs++) + bit_count += msgs->len; + + return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10; +} + +static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret) +{ + /* + * clear IRQ (INT=0, BER=0) + * set Stop Condition (MSS=0) + * Interrupt Disable + */ + writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); + + i2c->state = STATE_IDLE; + + i2c->msg_ptr = 0; + i2c->msg = NULL; + i2c->msg_idx++; + i2c->msg_num = 0; + if (ret) + i2c->msg_idx = ret; + + complete(&i2c->completion); +} + +static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c) +{ + unsigned char ccr_cs, csr_cs; + u32 rt = i2c->pclkrate; + + /* Set own Address */ + writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR); + + /* Set PCLK frequency */ + writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate), + i2c->base + SYNQUACER_I2C_REG_FSR); + + switch (i2c->speed_khz) { + case SYNQUACER_I2C_SPEED_FM: + if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) { + ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt); + csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt); + } else { + ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt); + csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt); + } + + /* Set Clock and enable, Set fast mode */ + writeb(ccr_cs | SYNQUACER_I2C_CCR_FM | + SYNQUACER_I2C_CCR_EN, + i2c->base + SYNQUACER_I2C_REG_CCR); + writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); + break; + case SYNQUACER_I2C_SPEED_SM: + if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) { + ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt); + csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt); + } else { + ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt); + csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt); + } + + /* Set Clock and enable, Set standard mode */ + writeb(ccr_cs | SYNQUACER_I2C_CCR_EN, + i2c->base + SYNQUACER_I2C_REG_CCR); + writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); + break; + default: + WARN_ON(1); + } + + /* clear IRQ (INT=0, BER=0), Interrupt Disable */ + writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); + writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R); +} + +static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c) +{ + /* Disable clock */ + writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR); + writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR); + + WAIT_PCLK(100, i2c->pclkrate); +} + +static int synquacer_i2c_master_start(struct synquacer_i2c *i2c, + struct i2c_msg *pmsg) +{ + unsigned char bsr, bcr; + + writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR); + + dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr); + + /* Generate Start Condition */ + bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); + bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); + dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); + + if ((bsr & SYNQUACER_I2C_BSR_BB) && + !(bcr & SYNQUACER_I2C_BCR_MSS)) { + dev_dbg(i2c->dev, "bus is busy"); + return -EBUSY; + } + + if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */ + dev_dbg(i2c->dev, "Continuous Start"); + writeb(bcr | SYNQUACER_I2C_BCR_SCC, + i2c->base + SYNQUACER_I2C_REG_BCR); + } else { + if (bcr & SYNQUACER_I2C_BCR_MSS) { + dev_dbg(i2c->dev, "not in master mode"); + return -EAGAIN; + } + dev_dbg(i2c->dev, "Start Condition"); + /* Start Condition + Enable Interrupts */ + writeb(bcr | SYNQUACER_I2C_BCR_MSS | + SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE, + i2c->base + SYNQUACER_I2C_REG_BCR); + } + + WAIT_PCLK(10, i2c->pclkrate); + + /* get BSR & BCR registers */ + bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); + bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); + dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); + + if ((bsr & SYNQUACER_I2C_BSR_AL) || + !(bcr & SYNQUACER_I2C_BCR_MSS)) { + dev_dbg(i2c->dev, "arbitration lost\n"); + return -EAGAIN; + } + + return 0; +} + +static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c, + struct i2c_msg *msgs, int num) +{ + unsigned char bsr; + unsigned long timeout; + int ret; + + if (i2c->is_suspended) + return -EBUSY; + + synquacer_i2c_hw_init(i2c); + bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); + if (bsr & SYNQUACER_I2C_BSR_BB) { + dev_err(i2c->dev, "cannot get bus (bus busy)\n"); + return -EBUSY; + } + + reinit_completion(&i2c->completion); + + i2c->msg = msgs; + i2c->msg_num = num; + i2c->msg_ptr = 0; + i2c->msg_idx = 0; + i2c->state = STATE_START; + + ret = synquacer_i2c_master_start(i2c, i2c->msg); + if (ret < 0) { + dev_dbg(i2c->dev, "Address failed: (%d)\n", ret); + return ret; + } + + timeout = wait_for_completion_timeout(&i2c->completion, + msecs_to_jiffies(i2c->timeout_ms)); + if (timeout == 0) { + dev_dbg(i2c->dev, "timeout\n"); + return -EAGAIN; + } + + ret = i2c->msg_idx; + if (ret != num) { + dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); + return -EAGAIN; + } + + /* wait 2 clock periods to ensure the stop has been through the bus */ + udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz)); + + return 0; +} + +static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id) +{ + struct synquacer_i2c *i2c = dev_id; + + unsigned char byte; + unsigned char bsr, bcr; + int ret; + + bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); + bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); + dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); + + if (bcr & SYNQUACER_I2C_BCR_BER) { + dev_err(i2c->dev, "bus error\n"); + synquacer_i2c_stop(i2c, -EAGAIN); + goto out; + } + if ((bsr & SYNQUACER_I2C_BSR_AL) || + !(bcr & SYNQUACER_I2C_BCR_MSS)) { + dev_dbg(i2c->dev, "arbitration lost\n"); + synquacer_i2c_stop(i2c, -EAGAIN); + goto out; + } + + switch (i2c->state) { + + case STATE_START: + if (bsr & SYNQUACER_I2C_BSR_LRB) { + dev_dbg(i2c->dev, "ack was not received\n"); + synquacer_i2c_stop(i2c, -EAGAIN); + goto out; + } + + if (i2c->msg->flags & I2C_M_RD) + i2c->state = STATE_READ; + else + i2c->state = STATE_WRITE; + + if (is_lastmsg(i2c) && i2c->msg->len == 0) { + synquacer_i2c_stop(i2c, 0); + goto out; + } + + if (i2c->state == STATE_READ) + goto prepare_read; + + /* fallthru */ + + case STATE_WRITE: + if (bsr & SYNQUACER_I2C_BSR_LRB) { + dev_dbg(i2c->dev, "WRITE: No Ack\n"); + synquacer_i2c_stop(i2c, -EAGAIN); + goto out; + } + + if (!is_msgend(i2c)) { + writeb(i2c->msg->buf[i2c->msg_ptr++], + i2c->base + SYNQUACER_I2C_REG_DAR); + + /* clear IRQ, and continue */ + writeb(SYNQUACER_I2C_BCR_BEIE | + SYNQUACER_I2C_BCR_MSS | + SYNQUACER_I2C_BCR_INTE, + i2c->base + SYNQUACER_I2C_REG_BCR); + break; + } + if (is_lastmsg(i2c)) { + synquacer_i2c_stop(i2c, 0); + break; + } + dev_dbg(i2c->dev, "WRITE: Next Message\n"); + + i2c->msg_ptr = 0; + i2c->msg_idx++; + i2c->msg++; + + /* send the new start */ + ret = synquacer_i2c_master_start(i2c, i2c->msg); + if (ret < 0) { + dev_dbg(i2c->dev, "restart error (%d)\n", ret); + synquacer_i2c_stop(i2c, -EAGAIN); + break; + } + i2c->state = STATE_START; + break; + + case STATE_READ: + byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR); + if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */ + i2c->msg->buf[i2c->msg_ptr++] = byte; + else /* address */ + dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte); + +prepare_read: + if (is_msglast(i2c)) { + writeb(SYNQUACER_I2C_BCR_MSS | + SYNQUACER_I2C_BCR_BEIE | + SYNQUACER_I2C_BCR_INTE, + i2c->base + SYNQUACER_I2C_REG_BCR); + break; + } + if (!is_msgend(i2c)) { + writeb(SYNQUACER_I2C_BCR_MSS | + SYNQUACER_I2C_BCR_BEIE | + SYNQUACER_I2C_BCR_INTE | + SYNQUACER_I2C_BCR_ACK, + i2c->base + SYNQUACER_I2C_REG_BCR); + break; + } + if (is_lastmsg(i2c)) { + /* last message, send stop and complete */ + dev_dbg(i2c->dev, "READ: Send Stop\n"); + synquacer_i2c_stop(i2c, 0); + break; + } + dev_dbg(i2c->dev, "READ: Next Transfer\n"); + + i2c->msg_ptr = 0; + i2c->msg_idx++; + i2c->msg++; + + ret = synquacer_i2c_master_start(i2c, i2c->msg); + if (ret < 0) { + dev_dbg(i2c->dev, "restart error (%d)\n", ret); + synquacer_i2c_stop(i2c, -EAGAIN); + } else { + i2c->state = STATE_START; + } + break; + default: + dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state); + break; + } + +out: + WAIT_PCLK(10, i2c->pclkrate); + return IRQ_HANDLED; +} + +static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct synquacer_i2c *i2c; + int retry; + int ret; + + i2c = i2c_get_adapdata(adap); + i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num); + + dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms); + + for (retry = 0; retry < adap->retries; retry++) { + + ret = synquacer_i2c_doxfer(i2c, msgs, num); + if (ret != -EAGAIN) + return ret; + + dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); + + synquacer_i2c_hw_reset(i2c); + } + return -EIO; +} + +static u32 synquacer_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm synquacer_i2c_algo = { + .master_xfer = synquacer_i2c_xfer, + .functionality = synquacer_i2c_functionality, +}; + +static int synquacer_i2c_get_scl(struct i2c_adapter *adap) +{ + struct synquacer_i2c *i2c = i2c_get_adapdata(adap); + u8 bc2r = readb(i2c->base + SYNQUACER_I2C_REG_BC2R); + + return !!(bc2r & SYNQUACER_I2C_BC2R_SCLS); +} + +static void synquacer_i2c_set_scl(struct i2c_adapter *adap, int val) +{ + struct synquacer_i2c *i2c = i2c_get_adapdata(adap); + u8 bc2r = readb(i2c->base + SYNQUACER_I2C_REG_BC2R); + + bc2r &= SYNQUACER_I2C_BC2R_SDAL; + if (!val) + bc2r |= SYNQUACER_I2C_BC2R_SCLL; + writeb(bc2r, i2c->base + SYNQUACER_I2C_REG_BC2R); +} + +static int synquacer_i2c_get_sda(struct i2c_adapter *adap) +{ + struct synquacer_i2c *i2c = i2c_get_adapdata(adap); + u8 bc2r = readb(i2c->base + SYNQUACER_I2C_REG_BC2R); + + return !!(bc2r & SYNQUACER_I2C_BC2R_SDAS); +} + +static struct i2c_bus_recovery_info synquacer_i2c_recovery_info = { + .recover_bus = i2c_generic_scl_recovery, + .get_scl = synquacer_i2c_get_scl, + .set_scl = synquacer_i2c_set_scl, + .get_sda = synquacer_i2c_get_sda, +}; + +static struct i2c_adapter synquacer_i2c_ops = { + .owner = THIS_MODULE, + .name = "synquacer_i2c-adapter", + .algo = &synquacer_i2c_algo, + .retries = 5, +}; + +static int synquacer_i2c_probe(struct platform_device *pdev) +{ + struct synquacer_i2c *i2c; + struct resource *r; + u32 bus_speed; + int ret; + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + bus_speed = i2c_acpi_find_bus_speed(&pdev->dev); + if (!bus_speed) + device_property_read_u32(&pdev->dev, "clock-frequency", + &bus_speed); + + device_property_read_u32(&pdev->dev, "socionext,pclk-rate", + &i2c->pclkrate); + + i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(i2c->pclk) && PTR_ERR(i2c->pclk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (!IS_ERR_OR_NULL(i2c->pclk)) { + dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk); + + ret = clk_prepare_enable(i2c->pclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable clock (%d)\n", + ret); + return ret; + } + i2c->pclkrate = clk_get_rate(i2c->pclk); + } + + if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE || + i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) { + dev_err(&pdev->dev, "PCLK missing or out of range (%d)\n", + i2c->pclkrate); + return -EINVAL; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(i2c->base)) + return PTR_ERR(i2c->base); + + i2c->irq = platform_get_irq(pdev, 0); + if (i2c->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource found\n"); + return -ENODEV; + } + + ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr, + 0, dev_name(&pdev->dev), i2c); + if (ret < 0) { + dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); + return ret; + } + + i2c->state = STATE_IDLE; + i2c->dev = &pdev->dev; + i2c->adapter = synquacer_i2c_ops; + i2c_set_adapdata(&i2c->adapter, i2c); + i2c->adapter.dev.parent = &pdev->dev; + i2c->adapter.nr = pdev->id; + i2c->adapter.bus_recovery_info = &synquacer_i2c_recovery_info; + init_completion(&i2c->completion); + + if (bus_speed < 400000) + i2c->speed_khz = SYNQUACER_I2C_SPEED_SM; + else + i2c->speed_khz = SYNQUACER_I2C_SPEED_FM; + + synquacer_i2c_hw_init(i2c); + + ret = i2c_add_numbered_adapter(&i2c->adapter); + if (ret) { + dev_err(&pdev->dev, "failed to add bus to i2c core\n"); + return ret; + } + + platform_set_drvdata(pdev, i2c); + + dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n", + dev_name(&i2c->adapter.dev)); + + return 0; +} + +static int synquacer_i2c_remove(struct platform_device *pdev) +{ + struct synquacer_i2c *i2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c->adapter); + if (!IS_ERR(i2c->pclk)) + clk_disable_unprepare(i2c->pclk); + + return 0; +}; + +static int __maybe_unused synquacer_i2c_suspend(struct device *dev) +{ + struct synquacer_i2c *i2c = dev_get_drvdata(dev); + + i2c_lock_adapter(&i2c->adapter); + i2c->is_suspended = true; + i2c_unlock_adapter(&i2c->adapter); + + if (!IS_ERR(i2c->pclk)) + clk_disable_unprepare(i2c->pclk); + + return 0; +} + +static int __maybe_unused synquacer_i2c_resume(struct device *dev) +{ + struct synquacer_i2c *i2c = dev_get_drvdata(dev); + int ret = 0; + + i2c_lock_adapter(&i2c->adapter); + + if (!IS_ERR(i2c->pclk)) + ret = clk_prepare_enable(i2c->pclk); + if (!ret) + i2c->is_suspended = false; + + i2c_unlock_adapter(&i2c->adapter); + + return ret; +} + +static SIMPLE_DEV_PM_OPS(synquacer_i2c_pm, synquacer_i2c_suspend, + synquacer_i2c_resume); + +static const struct of_device_id synquacer_i2c_dt_ids[] = { + { .compatible = "socionext,synquacer-i2c" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id synquacer_i2c_acpi_ids[] = { + { "SCX0003" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids); +#endif + +static struct platform_driver synquacer_i2c_driver = { + .probe = synquacer_i2c_probe, + .remove = synquacer_i2c_remove, + .driver = { + .name = "synquacer_i2c", + .of_match_table = of_match_ptr(synquacer_i2c_dt_ids), + .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids), + .pm = &synquacer_i2c_pm, + }, +}; +module_platform_driver(synquacer_i2c_driver); + +MODULE_AUTHOR("Fujitsu Semiconductor Ltd"); +MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Mar 25 11:07:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 132389 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2668896ljb; Sun, 25 Mar 2018 04:08:11 -0700 (PDT) X-Google-Smtp-Source: AG47ELvygi/9DChNL1B5XgC+mAp3OcmH72MIUF/UIoo6WFz8WbcnfbePm5Di4Om8nOkfJfmcZWCW X-Received: by 2002:a17:902:a607:: with SMTP id u7-v6mr36156661plq.367.1521976091241; Sun, 25 Mar 2018 04:08:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521976091; cv=none; d=google.com; s=arc-20160816; b=08065x47+LdrioxfFqbV6uE/aPjfTVop/2nuW9za14edX/tOydETBi/Av4F8U4cq2o gdp0csIX8TYrJDTM8S0k3EvzwseifD8EeGSe0cKlNM3WJWdWF+VRo5Xpqs7NYmp9FEsn qjqcqO5GvRaT1crdbxcMbQBad/AJO21YjRCeAj+JdmoACJgCB6bFRzSVj9ALQDBx7Z/G Mjn3qU9JcQh3W3TKJHprBgUPHes3MAqdRPcSrgsb+KxJMLV6DcDjSqZPnZjlGFZud9cN fGBERXpF+OU/bv4TRncApQtKOw/a30byWy+bw9OKUDFgEMVNTEDJvFsMkQya22EGXoli zATQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id f8-v6si13805808pli.445.2018.03.25.04.08.11; Sun, 25 Mar 2018 04:08:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aVS1m1Hv; spf=pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-i2c-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751985AbeCYLIK (ORCPT + 3 others); Sun, 25 Mar 2018 07:08:10 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:43080 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752004AbeCYLIJ (ORCPT ); Sun, 25 Mar 2018 07:08:09 -0400 Received: by mail-wr0-f193.google.com with SMTP id p53so8594720wrc.10 for ; Sun, 25 Mar 2018 04:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kGj4/oEIkuazlnX5YejmpjLpijkWPrArUlhRaD8hL8M=; b=aVS1m1HvdwAyXXpBXPHaDt7Zy/ahJNgOD7qVmasaxKFGzGN+Jaw5Bl+/ZSPeTd5RRE 10E3rW0yTnzuArUbLHD2QJuUgc5NDyE0qphVvrwdh/7J9zLNAs3uD1fFBB8UNarT5fXn xTj6biBHJZdpYYdrwqwhWJt3aCmRkWeS1OB3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kGj4/oEIkuazlnX5YejmpjLpijkWPrArUlhRaD8hL8M=; b=Bv1EZV4WMlQ0U+KsjlxhgsAxOSMSBnR2O7DejAfu01gEhpstvNf7l5LDPNssoovodQ v61actv8J80Gk/Zn3V4TBSXrMzeoQSn9F0yiqIcx5kE/hxjcYv78dKJV/XtaFk5DmeGX 21p8pWMnA6k8eTWGHgtjrS8656fRM33rcTEK5p2A9hEGwOGHxBviiJ31oiZnV+iksGuE 4Ug6FELWYOugdPhjXyGSblCmO24P0AMBMbO/H31TuFVHMhxUXqYqewjNisfbFWWmcE8q POwV64BAR+ntCtsYSR3fJJs1mZlqnA3VTo7YT753qMJeAzQCiLsQKb+k+V8uIFX0LRzv +2bA== X-Gm-Message-State: AElRT7GFKyhZXVrppKKTLu6G6/ltupAV0JBnylZo4DJ6Q9oGe4S9RT5p etq0ud6q1mevutBVJmwD/YhsdGE5HhI= X-Received: by 10.223.158.6 with SMTP id u6mr17730554wre.142.1521976088440; Sun, 25 Mar 2018 04:08:08 -0700 (PDT) Received: from localhost.localdomain ([160.105.205.136]) by smtp.gmail.com with ESMTPSA id w134sm14354298wmd.45.2018.03.25.04.08.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Mar 2018 04:08:07 -0700 (PDT) From: Ard Biesheuvel To: wsa@the-dreams.de Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jassisinghbrar@gmail.com, andy.shevchenko@gmail.com, Ard Biesheuvel Subject: [PATCH v6 3/3] i2c: add param sanity check to i2c_transfer() Date: Sun, 25 Mar 2018 12:07:47 +0100 Message-Id: <20180325110747.8852-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180325110747.8852-1-ard.biesheuvel@linaro.org> References: <20180325110747.8852-1-ard.biesheuvel@linaro.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org The API docs describe i2c_transfer() as taking a pointer to an array of i2c_msg containing at least 1 entry, but leaves it to the individual drivers to sanity check the msgs and num parameters. Let's do this in core code instead. Signed-off-by: Ard Biesheuvel --- drivers/i2c/i2c-core-base.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.15.1 diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index c8bfe008f208..dfc549cf0ac2 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -1845,6 +1845,9 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) unsigned long orig_jiffies; int ret, try; + if (!msgs || num < 1) + return -EINVAL; + if (adap->quirks && i2c_check_for_quirks(adap, msgs, num)) return -EOPNOTSUPP;