From patchwork Fri Mar 30 07:02:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 132589 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2693759ljb; Fri, 30 Mar 2018 00:03:16 -0700 (PDT) X-Google-Smtp-Source: AIpwx4++4KuFkPirUL63pkbDQ5JJ2ovNQ6l9SJ55WenMpY7dJU3UQLLYZjqW1olirWRq7HM43lRl X-Received: by 2002:a17:902:30f:: with SMTP id 15-v6mr11427781pld.365.1522393396154; Fri, 30 Mar 2018 00:03:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522393396; cv=none; d=google.com; s=arc-20160816; b=sPsuaWDNSYt1dMUtDtnGd0rmn7x/1sX9PjVXfkud81neWvOLksGQReVIcR/bEwdZRs m7vuAFvlt9k1jrDWaQl4gpim23geUf1EIem6wdOQRTqPUw1F2dHxJOlBrRU1TEJroWIf PKGk8IiMeG/qsXtxnf/wb4n2xo2RUMmYznEHEVlqRFvTCy1MwX535QxuDTq2Ndm/nnqP eWLYEqhp8+W5rIlaeioOneff1i79jhZORWbzLCiKWxJsrnmsKBTcR9kMS6qPDksIHXB5 4a4Eo5eRTy+/WOahQiLicJ7FpPoibgOLhPJxO6cS+0sC7Bs0m8wXXwgRxxlBYUym9j+3 Du3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=PSEl7qh3kQPQ+JnbeX1oK03evRIx+I2dDNQehd8i8m0=; b=i6mc7/SZbAhYM13dG4ghNnLCqiSp6Un8owvqdxL6M6rD21KL8a0zoQH7dkHBf7mTZo f3FkbyLXsd5SLFgNmAVhn8S+sqb7UTE2Gx1DfnaX0JNtndVFrHi1BQ/f5CCL70eJTefU YL9HU1Iy8RJfwL2hzDRFTVMpy+9QEhrHlJRviV8RkX3UpuSm4Qk+E5662/0nrmSb6cG5 IpO8wbNNQduzDtsHOjr+g7oP1i8H1OODMZynzbDBBTI2dsT+tPKyizdzZNky6hUAXq2J GhhocPamBxEHx99tGAzwBLQfAurWwQ32PjAtjEGJLyxZPKUk2IFRF3newX/te80Sn5uz bNSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VJzAAFD7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l62si480816pga.740.2018.03.30.00.03.15; Fri, 30 Mar 2018 00:03:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VJzAAFD7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751256AbeC3HDM (ORCPT + 29 others); Fri, 30 Mar 2018 03:03:12 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:38680 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750741AbeC3HDK (ORCPT ); Fri, 30 Mar 2018 03:03:10 -0400 Received: by mail-pg0-f65.google.com with SMTP id a15so4601206pgn.5 for ; Fri, 30 Mar 2018 00:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=PSEl7qh3kQPQ+JnbeX1oK03evRIx+I2dDNQehd8i8m0=; b=VJzAAFD7WZqlskZejY78eWXZTjnmyI2aXX9oMbwfJ51f4KvMkpcftGScYbLejs9Mlg hGSHFznWy4HUVP+w0iy9GNtIgiUJDFti9fSIxN73aRFE1m8sKnBS6u9DQ93wESt94AoQ 0b/NddDipeRHt4Jh4eUnDtSO+qCvat0LFaix8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=PSEl7qh3kQPQ+JnbeX1oK03evRIx+I2dDNQehd8i8m0=; b=ICn9Gy2Fn7pBeHPXnnq7dVHFdrZqyqIuApr9TCgobWHD9qnWOuFOxCz6TJkLHxkHH4 Vdc7s1+xPvbNUGOW06VU2SajNbwxprdJ2SqFBWjIErn7nm2HY4J18pZ96ZAenSXe2hej lQnxuhG/KfwMNsYO8ZBLVugeylMK2NVnyeIgj/F74n4Saiuw+txCPcU+jZ3cJ2tbK/qK rVs5Npv6s25Ym+VwTcrRe8oIVc7ry7o18K6leQ530RyNUy9PWN2SX3ZzmtaLcEhfQYmk jdWijUW7GI9CnXQlmAiIATxqNfnMu6fjvBhCOQkFvq52FQZw0ZHMBnyGGaJMfZ0bdoq8 tc+A== X-Gm-Message-State: AElRT7F9qAWuJQTtaB0BN/Y2U1DNBMzhKZANQJNRh45RGCTcglkchIk1 3dHdL3NrhoBkiXRcQId24hkxWQ== X-Received: by 10.98.157.6 with SMTP id i6mr9007207pfd.52.1522393390072; Fri, 30 Mar 2018 00:03:10 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id x3sm12628898pgv.86.2018.03.30.00.03.07 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Mar 2018 00:03:09 -0700 (PDT) From: Baolin Wang To: linus.walleij@linaro.org Cc: andy.shevchenko@gmail.com, broonie@kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, baolin.wang@linaro.org Subject: [PATCH 1/2] gpio: eic: Add edge trigger emulation for EIC Date: Fri, 30 Mar 2018 15:02:37 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Spreadtrum debounce EIC and latch EIC can not support edge trigger, but most GPIO users (like gpio-key driver) only use the edge trigger, thus the EIC driver need add some support to emulate the edge trigger to satisfy this requirement. Signed-off-by: Baolin Wang --- drivers/gpio/gpio-eic-sprd.c | 73 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 1.7.9.5 diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c index de7dd93..e0d6a0a 100644 --- a/drivers/gpio/gpio-eic-sprd.c +++ b/drivers/gpio/gpio-eic-sprd.c @@ -300,6 +300,7 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) struct gpio_chip *chip = irq_data_get_irq_chip_data(data); struct sprd_eic *sprd_eic = gpiochip_get_data(chip); u32 offset = irqd_to_hwirq(data); + int state; switch (sprd_eic->type) { case SPRD_EIC_DEBOUNCE: @@ -310,6 +311,17 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) case IRQ_TYPE_LEVEL_LOW: sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_EDGE_BOTH: + state = sprd_eic_get(chip, offset); + if (state) + sprd_eic_update(chip, offset, + SPRD_EIC_DBNC_IEV, 0); + else + sprd_eic_update(chip, offset, + SPRD_EIC_DBNC_IEV, 1); + break; default: return -ENOTSUPP; } @@ -324,6 +336,17 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) case IRQ_TYPE_LEVEL_LOW: sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_EDGE_BOTH: + state = sprd_eic_get(chip, offset); + if (state) + sprd_eic_update(chip, offset, + SPRD_EIC_LATCH_INTPOL, 0); + else + sprd_eic_update(chip, offset, + SPRD_EIC_LATCH_INTPOL, 1); + break; default: return -ENOTSUPP; } @@ -405,6 +428,55 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) return 0; } +static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, + unsigned int offset) +{ + struct sprd_eic *sprd_eic = gpiochip_get_data(chip); + struct irq_data *data = irq_get_irq_data(irq); + u32 trigger = irqd_get_trigger_type(data); + int state, post_state; + + /* + * The debounce EIC and latch EIC can only support level trigger, so we + * can toggle the level trigger to emulate the edge trigger. + */ + if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && + sprd_eic->type != SPRD_EIC_LATCH) || + !(trigger & IRQ_TYPE_EDGE_BOTH)) + return; + + sprd_eic_irq_mask(data); + state = sprd_eic_get(chip, offset); + +retry: + switch (sprd_eic->type) { + case SPRD_EIC_DEBOUNCE: + if (state) + sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); + else + sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); + break; + case SPRD_EIC_LATCH: + if (state) + sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); + else + sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); + break; + default: + sprd_eic_irq_unmask(data); + return; + } + + post_state = sprd_eic_get(chip, offset); + if (state != post_state) { + dev_warn(chip->parent, "EIC level was changed.\n"); + state = post_state; + goto retry; + } + + sprd_eic_irq_unmask(data); +} + static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data) { enum sprd_eic_type type = *(enum sprd_eic_type *)data; @@ -448,6 +520,7 @@ static void sprd_eic_handle_one_type(struct gpio_chip *chip) bank * SPRD_EIC_PER_BANK_NR + n); generic_handle_irq(girq); + sprd_eic_toggle_trigger(chip, girq, n); } } } From patchwork Fri Mar 30 07:02:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 132590 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2693847ljb; Fri, 30 Mar 2018 00:03:22 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/sa+PTLODUQTjdHHaO1RIytC/l+aFdUMPHDrnzr4dhwANVvk/YV1dIut94fVhUJkozv/i9 X-Received: by 10.99.117.17 with SMTP id q17mr7645242pgc.451.1522393401835; Fri, 30 Mar 2018 00:03:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522393401; cv=none; d=google.com; s=arc-20160816; b=mHXWgfYGLUZB3Lu6XWHJp4BAf7cRyKFdgyWe7qN2n4BH+plvYmUOZKWFz9ETJaGW1y 22FjfA9V91EEMGRRVa49Pm4pzKRYJpl5E3AqmzVOAxkm7gGOaivXVPvzjF1gSar1r5s8 giaK3fk1+YPiCxnmHcLCbgtX/NLasgX2UbJ677satBdS2rA00XJrX3Yq4cNlAHZ4+38P QAL2kv/F2UV9Oc0+/gWnV3H7JJjCMzqkClw87Z5ho1/PQe0+SnmFRlpZw2dYnmriYNfm TBPUDNqTEMHYR1I/P3PfsTCLYGO5TrvLwOl4xvuKM3xNT753iQBTNuB4/Iv1uOvfpXAq TN2g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id u10-v6si8007044plu.343.2018.03.30.00.03.21; Fri, 30 Mar 2018 00:03:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ap/k2eF9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751282AbeC3HDR (ORCPT + 29 others); Fri, 30 Mar 2018 03:03:17 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45093 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751258AbeC3HDN (ORCPT ); Fri, 30 Mar 2018 03:03:13 -0400 Received: by mail-pf0-f195.google.com with SMTP id l27so4907946pfk.12 for ; Fri, 30 Mar 2018 00:03:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=hDAEMbNsPuPohDK+erzhgn4W7ci4ENrMwKABdg0hePE=; b=Ap/k2eF98q1siaD/ACvPRbWhTJaHrs14pFplpV11xfx3B+QViyuWkqPH00HT1IW0BL GgTlHUzWjBfhgU1p6IjIX0x0i/kGc86RLz7Sup4rJAh8JY3nz4Cq0kcx3dDQsXLzRHnU TTedNlt+gk7uTA2d9W/VTMbKUui9tuF1U+Yso= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=hDAEMbNsPuPohDK+erzhgn4W7ci4ENrMwKABdg0hePE=; b=EPwPh7r9dTd+VXZ4Cj+4QMIM7Ym0AF0UPKewMzbP3XgrHzMe+0XGKD9IYOvohydgte q/PDJEvCnT4rZzKGQvPY6N0h7cjgagg1vAhC3vBmoFctBJA31z/H3izE3OPtbkH8nuc3 aH7DaxU69VHTDzV7RgNHrg3XCyAimLg6Qo3AaFDCz1pHz2t7a3+bRDRiwwtpgmM4FIIL nbmuq7laekzqyEVMMmFTV+6cK8r9rfiEuBpzRxjjt1uV5owXFOHBzWlOwW3Kg9l5GozA BylRGc6ngreM5c5sBKJoARQTUfkCad3nwXj0vPry4s9bDoESY4AVD9CcdyMBtfnEncsN z23g== X-Gm-Message-State: AElRT7E4Xar5N5Ww02RMLH7qfyErJ7OWTcForI9eQS7kUBIZQL+zp2L8 0Me6UrOmJafPT1R2Y2GlXqG/QpzQ9sA= X-Received: by 10.98.15.195 with SMTP id 64mr8835845pfp.63.1522393392460; Fri, 30 Mar 2018 00:03:12 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id x3sm12628898pgv.86.2018.03.30.00.03.10 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Mar 2018 00:03:12 -0700 (PDT) From: Baolin Wang To: linus.walleij@linaro.org Cc: andy.shevchenko@gmail.com, broonie@kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, baolin.wang@linaro.org Subject: [PATCH 2/2] gpio: pmic_eic: Add edge trigger emulation for PMIC EIC Date: Fri, 30 Mar 2018 15:02:38 +0800 Message-Id: <7bac44aef748c61863fd9651ef3c52b4e51c511a.1522392153.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch will toggle the EIC level to emulate the edge trigger to support PMIC EIC egdge trigger function, which is required by gpio-keys driver. Signed-off-by: Baolin Wang --- drivers/gpio/gpio-pmic-eic-sprd.c | 58 +++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) -- 1.7.9.5 diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c index 66d68d9..29e044f 100644 --- a/drivers/gpio/gpio-pmic-eic-sprd.c +++ b/drivers/gpio/gpio-pmic-eic-sprd.c @@ -178,6 +178,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data, case IRQ_TYPE_LEVEL_LOW: pmic_eic->reg[REG_IEV] = 0; break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_EDGE_BOTH: + /* + * Will set the trigger level according to current EIC level + * in irq_bus_sync_unlock() interface, so here nothing to do. + */ + break; default: return -ENOTSUPP; } @@ -197,11 +205,22 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data) { struct gpio_chip *chip = irq_data_get_irq_chip_data(data); struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); + u32 trigger = irqd_get_trigger_type(data); u32 offset = irqd_to_hwirq(data); + int state; /* Set irq type */ - sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, - pmic_eic->reg[REG_IEV]); + if (trigger & IRQ_TYPE_EDGE_BOTH) { + state = sprd_pmic_eic_get(chip, offset); + if (state) + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); + else + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); + } else { + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, + pmic_eic->reg[REG_IEV]); + } + /* Set irq unmask */ sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, pmic_eic->reg[REG_IE]); @@ -212,6 +231,35 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data) mutex_unlock(&pmic_eic->buslock); } +static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip, + unsigned int irq, unsigned int offset) +{ + u32 trigger = irq_get_trigger_type(irq); + int state, post_state; + + if (!(trigger & IRQ_TYPE_EDGE_BOTH)) + return; + + state = sprd_pmic_eic_get(chip, offset); +retry: + if (state) + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); + else + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); + + post_state = sprd_pmic_eic_get(chip, offset); + if (state != post_state) { + dev_warn(chip->parent, "PMIC EIC level was changed.\n"); + state = post_state; + goto retry; + } + + /* Set irq unmask */ + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1); + /* Generate trigger start pulse for debounce EIC */ + sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1); +} + static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data) { struct sprd_pmic_eic *pmic_eic = data; @@ -233,6 +281,12 @@ static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data) girq = irq_find_mapping(chip->irq.domain, n); handle_nested_irq(girq); + + /* + * The PMIC EIC can only support level trigger, so we can + * toggle the level trigger to emulate the edge trigger. + */ + sprd_pmic_eic_toggle_trigger(chip, girq, n); } return IRQ_HANDLED;