From patchwork Tue Apr 3 13:00:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 132745 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3777816ljb; Tue, 3 Apr 2018 06:01:50 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/ZxontN+5vxLFI3DdSHIFELC3h35Arg8HtOTaC9FnrLxATa0fj1rkdTbmhVmRPtPVan81l X-Received: by 2002:a17:902:64cf:: with SMTP id y15-v6mr14318758pli.49.1522760510401; Tue, 03 Apr 2018 06:01:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522760510; cv=none; d=google.com; s=arc-20160816; b=ck21FIeTwzmjG7UcOU1HH4/hy4/gyysUvmgGXeayh3FxQDB/b1IF/HJj8Ts7AN9+mI 2BWPC1zaCqjnCiLnR24yUBLwSV0qaWuesOgUuNDtUITPGdsduQTmVDov48mckjhEujyQ EMQD1kWxFp99J9Szg0qGDZhawN38qMA8+zcE8xGhHxu7AGih41OI5WPA55mkap97IsNv mUl1IZSYwRmzP+tTH7tTsZdz/xeeTIpH73tPjLKPQRqrZCAWMkO4Tcx2rQ4cXCpf6zC5 GSQwpR1wRlrn/dKIUsQCjIFQY/t21+jv8/BANuEXxsYZKEDPSUL5gV8ze0CfCr8Pe0dq UZpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pDcP4ElhtzDFczJG+YXCmWM3XKWZyX2bCfMk6R4DPCw=; b=AAc5GjAvxWKJl/D05zYG6GPG+YmUUxKkBOERrX+OOzNgHgfg6QsCSdnUyGBuTJUzEa XYjpX7WQJGmNjKarpNp9yf+W11q9y5Ob1ncwKcuNfnKYE8bRYy23WsK9AKqD8uXbcLzj ZgkHUuxg71yU2BnPHq88HDPMHt+twA9Rxw7OWOCw9mcYYPs5QxTy+uLCcuOjV/kjmX7E cMhILwlZMBdCy3fjySKuOF4YcmjTGZWSGtapnV3iQyYf2ZjKLBi9Y6V4d1RPnMPt29i/ 9wXwvfQxBxWutGwYWJ+3WrSFHZmWUzZLFWPCb58DzKX/EYxeAQ5XvX3/A9/c+iwxRfw9 PCpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PdtQhwnN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si503995plf.78.2018.04.03.06.01.50; Tue, 03 Apr 2018 06:01:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PdtQhwnN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932214AbeDCNBq (ORCPT + 29 others); Tue, 3 Apr 2018 09:01:46 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:38338 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932130AbeDCNBp (ORCPT ); Tue, 3 Apr 2018 09:01:45 -0400 Received: by mail-wm0-f68.google.com with SMTP id i3so11258282wmf.3 for ; Tue, 03 Apr 2018 06:01:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pDcP4ElhtzDFczJG+YXCmWM3XKWZyX2bCfMk6R4DPCw=; b=PdtQhwnNesP0fYEk6cjJxW68SJyJbkievvAs9zjY+miuWoGgAwGAzZgOZDAPKv9/f1 v0Ktc+jQg5JEYkKM+e9q3Vket63z52K8NxY3LKSkig2lD3Kw5pTCtIoGrbAsGnyvV7yL 9pTbAB1oLS2sFGyVtgJvRZ7jt3o2ZAK8oNHKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pDcP4ElhtzDFczJG+YXCmWM3XKWZyX2bCfMk6R4DPCw=; b=PNeoemxCVy6+lFtyt1jNYWzuDQR6zyLpMWn+v8DFDFycMOd/rsTIvzkRTK8sHVcaLb RzhG37QrzxB3frSDgx/ygpiC7Jap+kBWaCuqZ18DFYRxM5ho5kH77qnvtqm8DIRN3tJo AnvghGPtNNNJWOezuVWvW+UzuB+Vq8aEyYMdIb+LlJHdAN5lj1DrqUGrx2bAsosQBQeU fDro2U80lk34Sdtrg1OIU7iLFhsXhMTzCZjFxtdK1/g0u0Js/PgguDxKMtdwTXf6tbZF OuMX338EiDTdXBYsNiIkLahF2bmNU5X/XCVQFW8d6An/O1Doy7EX79ueyDlkf31Q96hF Aonw== X-Gm-Message-State: ALQs6tBfsO3pTiEf1W7OzBwyuxrnIRJwi0nibvGUTimiZyJ3OBx04kSM 2GdiQWc7u2LEwARNKxysliG/LA== X-Received: by 10.28.71.77 with SMTP id u74mr4489370wma.149.1522760503751; Tue, 03 Apr 2018 06:01:43 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c10:b60f:70d4:5b8c]) by smtp.gmail.com with ESMTPSA id j76sm857047wmd.17.2018.04.03.06.01.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Apr 2018 06:01:43 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Tomer Maimon , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 1/6] dt-binding: timer: document NPCM7xx timer DT bindings Date: Tue, 3 Apr 2018 15:00:25 +0200 Message-Id: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tomer Maimon Added device tree binding documentation for Nuvoton NPCM7xx timer. Signed-off-by: Tomer Maimon Acked-by: Rob Herring Reviewed-by: Brendan Higgins Signed-off-by: Daniel Lezcano --- .../bindings/timer/nuvoton,npcm7xx-timer.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt new file mode 100644 index 0000000..ea22dfe --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt @@ -0,0 +1,21 @@ +Nuvoton NPCM7xx timer + +Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit +timer counters. + +Required properties: +- compatible : "nuvoton,npcm750-timer" for Poleg NPCM750. +- reg : Offset and length of the register set for the device. +- interrupts : Contain the timer interrupt with flags for + falling edge. +- clocks : phandle of timer reference clock (usually a 25 MHz clock). + +Example: + +timer@f0008000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = ; + reg = <0xf0008000 0x50>; + clocks = <&clk NPCM7XX_CLK_TIMER>; +}; + From patchwork Tue Apr 3 13:00:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 132746 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3777959ljb; Tue, 3 Apr 2018 06:01:55 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+SULMvyPkAZEBp7D3g8dnqFO9IeRp5kl9Wml0dQ8HGHLijdDy3AsBRsEwS7IupVGUB/UyZ X-Received: by 2002:a17:902:8ec8:: with SMTP id x8-v6mr14396662plo.179.1522760515045; Tue, 03 Apr 2018 06:01:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522760515; cv=none; d=google.com; s=arc-20160816; b=uWX0CkxB54Kmy/bQdG1uk6a47qDRoCUtLpVwD3gQLYOA/zdewmSvgxfM0RoihkhQcM iVu3rwppg0tAKO8LYsNveX48Ls8absbrXgTHswOTAXdaRJHWBO4y1CaGHjzh3I/XwTtX 8+O205uxZlryPTq81eimTWGEtIX+NCnnLN6WSYYBwb6QuY0R/B5mQ2JUsN5jdE8jz4Ve /5pGUUl5OELDSQxGICKBnNuWbiuwg422q6l6+BllF9LSUne0G8nJtdc/ghzX+jMeYefL Gn4hGAdU4efRnzZYDLS8zTPTWQfHTY/f6tKQjSha5JVVN1vObTJyjZ/IJthWf0I1PHZE YrQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GPNtoNNe14x+4+6xjiYnoEmlN+eauyI0/9rIl3LfTHM=; b=fs/hKP3wIBL4vkAIOqBrgzeQ1oU2oWAsN8vxrta+9HCvprPUd1V0PPwPjYn6iDT4O4 BPFZcKVRBiIFKTNYLSlc8TyXX6x7Rirs8M7Q1Ze6jlhZw9NEpg/QTUaxC+ueibxZxnpS GR8VlTVn+um7QF3WdYUG1zx+O5siBE5Q4cOI3Y23rAHjakU4VBOFCuz+qCctcPohsD3V dwoCvvGobX3Wx5H2VqvUsna1Dm30FFKn4MGP2lfavSsxmbv3lfQ1Lf+27AivBIoVcgDc aM7eNbTIQVEKN+cLuHJLeMYfG6Ui/5vFEmKJmlwdbZc7Zi5qHPDFxCxPfrE2+Zo2n0e4 XX3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kc7g8hFW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si503995plf.78.2018.04.03.06.01.54; Tue, 03 Apr 2018 06:01:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kc7g8hFW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932242AbeDCNBw (ORCPT + 29 others); Tue, 3 Apr 2018 09:01:52 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:46314 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932130AbeDCNBs (ORCPT ); Tue, 3 Apr 2018 09:01:48 -0400 Received: by mail-wr0-f195.google.com with SMTP id d1so18642383wrj.13 for ; Tue, 03 Apr 2018 06:01:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GPNtoNNe14x+4+6xjiYnoEmlN+eauyI0/9rIl3LfTHM=; b=kc7g8hFWAH41PgFiSYagWF59ftv0fTJ8cTiJlzC7fGSIVFimAmTyM24TJ+yHhHYeof yCiN6t9VI58UO3kAe6BTfiKLOX3ykCTkUque18eN1v2hy0pulBCMvolP2xosR2Il8EDh 37iyi+j2q857r5pF44EQ73uVf5Bekct5pYbBI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GPNtoNNe14x+4+6xjiYnoEmlN+eauyI0/9rIl3LfTHM=; b=UUkAWMG5hEc4szCR8yfa3mQDwkQopLuY3iFzO0Duo1wMKhOkJOzRGkf52sJAjvgXAj GI1IgOeatuyTdzpgecEfmMal50aHrMJuC0S5fmZjLR43CmSOn0ctORG1BoZL+jdT4TQW MouiBWPCQpRLaEObwEoiEXbsYsZJtqO6nO1Z62EE02w5BLLI3hLcKEd6rdc7dV9c+jke DHz1n9VeTfN40J/NFgCz8+tzF95rqiGRFULa5sxhFmGK0wtLNqWOl0oJmnJWZwqQMbTd tw7shfM4Thkl4ieYzwCkvOY2SjPUesneXyPMvtxtwh2R4ksUVH7FyoazipKK9+++4y2W KZMw== X-Gm-Message-State: AElRT7FZIXPWzuz0U2BAXOzO7rzJ9ND9cP2Rr7UEP3N+D7scrkQjzZUa iSLAwRfimuICW6yEKVGo9o5SPg== X-Received: by 10.223.209.194 with SMTP id m2mr10482522wri.214.1522760507015; Tue, 03 Apr 2018 06:01:47 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c10:b60f:70d4:5b8c]) by smtp.gmail.com with ESMTPSA id j76sm857047wmd.17.2018.04.03.06.01.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Apr 2018 06:01:46 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH 2/6] clocksource/drivers/npcm: Add NPCM7xx timer driver Date: Tue, 3 Apr 2018 15:00:26 +0200 Message-Id: <1522760432-32048-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> References: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tomer Maimon Add Nuvoton BMC NPCM7xx timer driver. The clocksource Enable 24-bit TIMER0 and TIMER1 counters, while TIMER0 serve as clockevent and TIMER1 serve as clocksource. Signed-off-by: Tomer Maimon Reviewed-by: Brendan Higgins Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-npcm7xx.c | 215 ++++++++++++++++++++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 drivers/clocksource/timer-npcm7xx.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index b3b4ed9..76194bc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -130,6 +130,14 @@ config VT8500_TIMER help Enables support for the VT8500 driver. +config NPCM7XX_TIMER + bool "NPCM7xx timer driver" if COMPILE_TEST + depends on HAS_IOMEM + select CLKSRC_MMIO + help + Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture, + While TIMER0 serves as clockevent and TIMER1 serves as clocksource. + config CADENCE_TTC_TIMER bool "Cadence TTC timer driver" if COMPILE_TEST depends on COMMON_CLK diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index d6dec44..7438787 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += owl-timer.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o +obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c new file mode 100644 index 0000000..7a9bb55 --- /dev/null +++ b/drivers/clocksource/timer-npcm7xx.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com + * All rights reserved. + * + * Copyright 2017 Google, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +/* Timers registers */ +#define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */ +#define NPCM7XX_REG_TICR0 0x8 /* Timer 0 Initial Count Register */ +#define NPCM7XX_REG_TCSR1 0x4 /* Timer 1 Control and Status Register */ +#define NPCM7XX_REG_TICR1 0xc /* Timer 1 Initial Count Register */ +#define NPCM7XX_REG_TDR1 0x14 /* Timer 1 Data Register */ +#define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */ + +/* Timers control */ +#define NPCM7XX_Tx_RESETINT 0x1f +#define NPCM7XX_Tx_PERIOD BIT(27) +#define NPCM7XX_Tx_INTEN BIT(29) +#define NPCM7XX_Tx_COUNTEN BIT(30) +#define NPCM7XX_Tx_ONESHOT 0x0 +#define NPCM7XX_Tx_OPER GENMASK(3, 27) +#define NPCM7XX_Tx_MIN_PRESCALE 0x1 +#define NPCM7XX_Tx_TDR_MASK_BITS 24 +#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF +#define NPCM7XX_T0_CLR_INT 0x1 +#define NPCM7XX_Tx_CLR_CSR 0x0 + +/* Timers operating mode */ +#define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \ + NPCM7XX_Tx_INTEN | \ + NPCM7XX_Tx_MIN_PRESCALE) + +#define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \ + NPCM7XX_Tx_INTEN | \ + NPCM7XX_Tx_MIN_PRESCALE) + +#define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \ + NPCM7XX_Tx_MIN_PRESCALE) + +#define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE) + +static int npcm7xx_timer_resume(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + u32 val; + + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val |= NPCM7XX_Tx_COUNTEN; + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); + + return 0; +} + +static int npcm7xx_timer_shutdown(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + u32 val; + + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val &= ~NPCM7XX_Tx_COUNTEN; + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); + + return 0; +} + +static int npcm7xx_timer_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + u32 val; + + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val &= ~NPCM7XX_Tx_OPER; + + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val |= NPCM7XX_START_ONESHOT_Tx; + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); + + return 0; +} + +static int npcm7xx_timer_periodic(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + u32 val; + + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val &= ~NPCM7XX_Tx_OPER; + + writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); + val |= NPCM7XX_START_PERIODIC_Tx; + + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); + + return 0; +} + +static int npcm7xx_clockevent_set_next_event(unsigned long evt, + struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val; + + writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0); + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); + val |= NPCM7XX_START_Tx; + writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); + + return 0; +} + +static irqreturn_t npcm7xx_timer0_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); + + writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of npcm7xx_to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "npcm7xx-timer0", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = npcm7xx_clockevent_set_next_event, + .set_state_shutdown = npcm7xx_timer_shutdown, + .set_state_periodic = npcm7xx_timer_periodic, + .set_state_oneshot = npcm7xx_timer_oneshot, + .tick_resume = npcm7xx_timer_resume, + .rating = 300, + }, + + .of_irq = { + .handler = npcm7xx_timer0_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static void __init npcm7xx_clockevents_init(void) +{ + writel(NPCM7XX_DEFAULT_CSR, + timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0); + + writel(NPCM7XX_Tx_RESETINT, + timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR); + + npcm7xx_to.clkevt.cpumask = cpumask_of(0); + clockevents_config_and_register(&npcm7xx_to.clkevt, + timer_of_rate(&npcm7xx_to), + 0x1, NPCM7XX_Tx_MAX_CNT); +} + +static void __init npcm7xx_clocksource_init(void) +{ + u32 val; + + writel(NPCM7XX_DEFAULT_CSR, + timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); + writel(NPCM7XX_Tx_MAX_CNT, + timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1); + + val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); + val |= NPCM7XX_START_Tx; + writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); + + clocksource_mmio_init(timer_of_base(&npcm7xx_to) + + NPCM7XX_REG_TDR1, + "npcm7xx-timer1", timer_of_rate(&npcm7xx_to), + 200, (unsigned int)NPCM7XX_Tx_TDR_MASK_BITS, + clocksource_mmio_readl_down); +} + +static int __init npcm7xx_timer_init(struct device_node *np) +{ + int ret; + + ret = timer_of_init(np, &npcm7xx_to); + if (ret) + return ret; + + /* Clock input is divided by PRESCALE + 1 before it is fed */ + /* to the counter */ + npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate / + (NPCM7XX_Tx_MIN_PRESCALE + 1); + + npcm7xx_clocksource_init(); + npcm7xx_clockevents_init(); + + pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ", + timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to)); + + return 0; +} + +TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init); + From patchwork Tue Apr 3 13:00:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 132749 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3778684ljb; Tue, 3 Apr 2018 06:02:21 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/liTh1TtJTwgGlVHdrRSLhjHZEL78zhJ9PF//eiRjXvc3W8mCtKvG5G+mYxXNSoxU5TX6V X-Received: by 10.101.100.212 with SMTP id t20mr9275985pgv.112.1522760541766; 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Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 21bffdc..3f97d49 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -179,7 +179,7 @@ static int __init tpm_timer_init(struct device_node *np) ipg = of_clk_get_by_name(np, "ipg"); per = of_clk_get_by_name(np, "per"); if (IS_ERR(ipg) || IS_ERR(per)) { - pr_err("tpm: failed to get igp or per clk\n"); + pr_err("tpm: failed to get ipg or per clk\n"); ret = -ENODEV; goto err_clk_get; } From patchwork Tue Apr 3 13:00:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 132747 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3778039ljb; Tue, 3 Apr 2018 06:01:57 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/TUMdaDxWBbNABHCqFTc/HZJ/dt1jQ5ViDTEqWbjGqy2MXgyR5K6CdG6gWDct115KWTWPv X-Received: by 10.167.130.26 with SMTP id k26mr10534428pfi.77.1522760517634; Tue, 03 Apr 2018 06:01:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522760517; cv=none; d=google.com; s=arc-20160816; b=HZRRnrEmWwxBkn+S4j5RqqGdZT9S4Vt2XSK28aExXWQHiD+QtzQZ16TypB4JnygrYh 7VLzsaJBnGC6+zxjUEjqK+hg7QXgzyD+BzxIkdRkUrDgy836Ahh8w7RjIJoTj8cKfCBH m3qusW6jhE3FfnVu3+p+I9Ai6z5HLWwuTCCcsVbH25lfumyAgaOghmEUEKIpVVcW8/Ml ZcHAq99SEgAjJ+xFNhLg9n4iWbD+JcoXVTcoMI6v3slzJj/ipqWSCEtUp5c3so5iGibJ 3Ojy9j9JcS6Fo5SRE3XT9056vh/ZMjB4PpO1KAR1A21mLcTTWtsdQs/gjBucjgVF7tTU I4XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4LPdMv2rGw8Z2OBcuXa+Ybzax2iPi2UiwBiUSSp20zI=; b=Oum86UDGDCHiTNY1jl7n73qq7fT8p5CsRmGc9/vHsup6yti6UIn3nmXtY5OnjhGc0d Hmykqai6sI/EVht4DGBgkBvxj0hU4sCbsMc/b7lyI7yQ0H6GORiMPZ8w2M9ce/Kv5yzB KCAybZpVaRaXxFmSO+/WI6TLPyPIxZd3fDWRCqQ4gRUVZhbFHWN0ypzs3FMqEO6+nKZs 2xi4EbotS1pEA+n/fbR2lCQrNThE9Xp/GWw2I7tXfP+NRlxbsavBVbCuySdWQO2+0AGx Czmk7CNQBf4nUw/osqL90WQrlZfuX7shh9qWr/pLdTh6r5niOkRbapsgW7irNlAcNNXi w/2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gZSJQ7xB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 03 Apr 2018 06:01:51 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:2c10:b60f:70d4:5b8c]) by smtp.gmail.com with ESMTPSA id j76sm857047wmd.17.2018.04.03.06.01.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Apr 2018 06:01:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang Subject: [PATCH 5/6] clocksource/drivers/imx-tpm: Correct some registers operation flow Date: Tue, 3 Apr 2018 15:00:29 +0200 Message-Id: <1522760432-32048-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> References: <1522760432-32048-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang According to i.MX7ULP reference manual, TPM_SC_CPWMS can ONLY be written when counter is disabled, TPM_SC_TOF is write-1-clear, TPM_C0SC_CHF is also write-1-clear, correct these registers initialization flow; Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 3f97d49..7403e49 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -20,6 +20,7 @@ #define TPM_SC 0x10 #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) #define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_SC_TOF_MASK (0x1 << 7) #define TPM_CNT 0x14 #define TPM_MOD 0x18 #define TPM_STATUS 0x1c @@ -29,6 +30,7 @@ #define TPM_C0SC_MODE_SHIFT 2 #define TPM_C0SC_MODE_MASK 0x3c #define TPM_C0SC_MODE_SW_COMPARE 0x4 +#define TPM_C0SC_CHF_MASK (0x1 << 7) #define TPM_C0V 0x24 static void __iomem *timer_base; @@ -205,9 +207,13 @@ static int __init tpm_timer_init(struct device_node *np) * 4) Channel0 disabled * 5) DMA transfers disabled */ + /* make sure counter is disabled */ writel(0, timer_base + TPM_SC); + /* TOF is W1C */ + writel(TPM_SC_TOF_MASK, timer_base + TPM_SC); writel(0, timer_base + TPM_CNT); - writel(0, timer_base + TPM_C0SC); + /* CHF is W1C */ + writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC); /* increase per cnt, div 8 by default */ writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, From patchwork Tue Apr 3 13:00:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 132748 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3778147ljb; Tue, 3 Apr 2018 06:02:01 -0700 (PDT) X-Google-Smtp-Source: AIpwx48+XUFnJgEU2t6NUnNeDwmvNcRrzxPQyZ/2/EWLSiMROtYbIjP0WO7dnx++sZVRxF0z6hKe X-Received: by 2002:a17:902:2be4:: with SMTP id l91-v6mr14427692plb.102.1522760521760; Tue, 03 Apr 2018 06:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522760521; cv=none; d=google.com; s=arc-20160816; b=xXGx0McV7W4G532nMDO8tZoJ/XUAWGVDOwbFFCSEDqgvCbT3Z/tk+AWqkr7j2oIyny 1gSK4TfZ+y93usNm5AyGCoI7YLOvw+HCNGgx8XkZDYI9st4MOAq3MmmTsa8W0r1CF0r4 tg31WD3+NznKTOOf8gwU9+qA+Ubu2Iv6F8zIxmcuEaBAm0lAou/dITF6LYMc3P0AvhhQ opaUvle5s5/WCmADskcnbt58JEplBhtC9QZvDpfKlXvJsDCeVQEpvP4BpMtxAqar35F7 GZExhmA7BCR7U83k3NraZ1TimbY3mSStEpshbiMOmYGsQ9dkgXHaAfRDHkbPZhI8ZVvb fh3A== ARC-Message-Signature: i=1; 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Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 7403e49..05d97a6 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -17,9 +17,13 @@ #include #include +#define TPM_PARAM 0x4 +#define TPM_PARAM_WIDTH_SHIFT 16 +#define TPM_PARAM_WIDTH_MASK (0xff << 16) #define TPM_SC 0x10 #define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) #define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_SC_CMOD_DIV_MAX 0x7 #define TPM_SC_TOF_MASK (0x1 << 7) #define TPM_CNT 0x14 #define TPM_MOD 0x18 @@ -33,6 +37,8 @@ #define TPM_C0SC_CHF_MASK (0x1 << 7) #define TPM_C0V 0x24 +static int counter_width; +static int rating; static void __iomem *timer_base; static struct clock_event_device clockevent_tpm; @@ -85,10 +91,11 @@ static int __init tpm_clocksource_init(unsigned long rate) tpm_delay_timer.freq = rate; register_current_timer_delay(&tpm_delay_timer); - sched_clock_register(tpm_read_sched_clock, 32, rate); + sched_clock_register(tpm_read_sched_clock, counter_width, rate); return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", - rate, 200, 32, clocksource_mmio_readl_up); + rate, rating, counter_width, + clocksource_mmio_readl_up); } static int tpm_set_next_event(unsigned long delta, @@ -141,7 +148,6 @@ static struct clock_event_device clockevent_tpm = { .set_state_oneshot = tpm_set_state_oneshot, .set_next_event = tpm_set_next_event, .set_state_shutdown = tpm_set_state_shutdown, - .rating = 200, }; static int __init tpm_clockevent_init(unsigned long rate, int irq) @@ -151,10 +157,11 @@ static int __init tpm_clockevent_init(unsigned long rate, int irq) ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "i.MX7ULP TPM Timer", &clockevent_tpm); + clockevent_tpm.rating = rating; clockevent_tpm.cpumask = cpumask_of(0); clockevent_tpm.irq = irq; - clockevents_config_and_register(&clockevent_tpm, - rate, 300, 0xfffffffe); + clockevents_config_and_register(&clockevent_tpm, rate, 300, + GENMASK(counter_width - 1, 1)); return ret; } @@ -199,6 +206,11 @@ static int __init tpm_timer_init(struct device_node *np) goto err_per_clk_enable; } + counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK) + >> TPM_PARAM_WIDTH_SHIFT; + /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ + rating = counter_width == 0x20 ? 200 : 150; + /* * Initialize tpm module to a known state * 1) Counter disabled @@ -215,12 +227,17 @@ static int __init tpm_timer_init(struct device_node *np) /* CHF is W1C */ writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC); - /* increase per cnt, div 8 by default */ - writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, + /* + * increase per cnt, + * div 8 for 32-bit counter and div 128 for 16-bit counter + */ + writel(TPM_SC_CMOD_INC_PER_CNT | + (counter_width == 0x20 ? + TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX), timer_base + TPM_SC); /* set MOD register to maximum for free running mode */ - writel(0xffffffff, timer_base + TPM_MOD); + writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD); rate = clk_get_rate(per) >> 3; ret = tpm_clocksource_init(rate);