From patchwork Wed Feb 24 16:58:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 386870 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp533031jap; Wed, 24 Feb 2021 09:04:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJzA158868F7HQjYMKmKrEDUkBTlXVqXUrl16Q7mF01FJXYBJtwcg7wpJ9UlZ6powC3JcqGw X-Received: by 2002:a4a:d8d8:: with SMTP id c24mr23387952oov.14.1614186243113; Wed, 24 Feb 2021 09:04:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614186243; cv=none; d=google.com; s=arc-20160816; b=eFhUh13Q4Y2MLRmDENOk9KarqB2VmueKXahF/kPcfAy7vysKeGQA5ZAQDHYT6s7FlE Rn6mEVpOlOX4/LvFgPDibJ1Th0V0GiewqOia/YeIcGUAhJ0JJ4/mgMlDxMzVd/Wlw3UU drnkMTcDE7oB5/22qOPRIYxD/oTyLD/Y+2q+r6p7cUotrEubOFLqj+WeERcWjueNDTzD 53uMIamcdJ/nh73kEE6R8Dhnw7mBiN43o9zjAbglDwhuatRbQfIvbYeVLTZI1onLDyHh ySWrZlnMGadGxc6ibJPwguPmX3u7SYBu2VpdbMviziQVHmFmF5uaBn5fweHU/Txy6sSx 0DhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AwSqA5g84lGAhAL1w2zSXZBGJIZPg/hYExK6AypbDmU=; b=qgv2tXjycF3dH5knJ/pmRqWWkbEjqO4t06Tz0Y1aCTc6BxubSNSTxwG8v7vTP3SGuU QUkdQ2LGjYTXHbNv8dPG2HOAV6ROSlHZSZBnzOFJi6J2alzX8rqHcAPIgXczduVXXkt4 coEmljSvlYxynmlbW5NHkNUhIU609heBvjKHCqyf0mY2CENKdrEaUJC3Sw6dBibxpE75 kZjsqYDB/H3QODTLUQWd6Fn18FhvFmrryxjPjUSUKQh8Tjy2A8dJif0gPUMXuC2FKYJf HGwerkMqoChaZKpdqcOsMXEFiwXCld8sRlTpts8MK0jQW3AC6UkYjujbb/LLMoZ9qnTW O4EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JIroZYon; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h205si651635oia.194.2021.02.24.09.04.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Feb 2021 09:04:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JIroZYon; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lExZy-00071J-EA for patch@linaro.org; Wed, 24 Feb 2021 12:04:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lExUU-0003HL-Oo for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:24 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:53261) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lExUN-00072g-MU for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:22 -0500 Received: by mail-wm1-x32e.google.com with SMTP id x16so2381861wmk.3 for ; Wed, 24 Feb 2021 08:58:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AwSqA5g84lGAhAL1w2zSXZBGJIZPg/hYExK6AypbDmU=; b=JIroZYon6oOABliT3VnssgHgpzb0aXrMsoYARFHKPdWe8I7MwMnOmcXEVejPamlAoE IjXcU0E9ULHHIZPdxytl59yS/il3RimpmD8u5tvhU2tlTbezR7YEUfbwdvxQ27u+EPjY Gp9TqNT3RWP6XlQ5LjrLBBL4nujg31uThuNrfH2aAxyn0ljChX0jl8JfuIpzM/2mlzD2 TIjAlnIdJKsFHpydU7S8ivqZBqyguWWNapOF0vRVQ4NqdIKrl+6JB4p7g/455pQflYjv uX5g+ZZ7lASMcjkPIDi4KjLZDNoQjkr/ZAA2rQxiRvZT+LafX2H9qA/XhA60E4rDXTlW 1OEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AwSqA5g84lGAhAL1w2zSXZBGJIZPg/hYExK6AypbDmU=; b=ltGNUhDoxz3dzKYEP9eyzTpt9EWIvMsJaaz5wEgQbcHU8latml3kApVTWlWVNA5+R5 h0w0mlQb/zcLKOFiZGiIHcsgFU6XANWSw3XOLlA8uaguuGlbOxXU2l9KpusXV0YbLzy2 FAdplRVv8vE16DkM4xTLRZeA7Loo0SGGwoul32tLzVO+QEl3E62BOxtfKW7G/e2eG7rQ hzdSSy9sxL8FJA5lcIeL1fRg99+A5PWwW+Zasu0kjat+UUpvHw/e6ENzgeN40m/VgwSW yuEBz2T1/mLDKkryy75DcFmjug5Yn+NQXjD456g5FTrWZjmRMjA+ndAwi7mqU1IjNbTq xwHA== X-Gm-Message-State: AOAM530bknZwrYYQzGuvL0TylGO53kk4Glh6sZm2J59D2vEx8UQP0lOe 8/4iOhiGWVLFH57t/xy2yJlvVA== X-Received: by 2002:a1c:c903:: with SMTP id f3mr4548876wmb.69.1614185893103; Wed, 24 Feb 2021 08:58:13 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g63sm4150970wma.40.2021.02.24.08.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 08:58:12 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7721D1FF87; Wed, 24 Feb 2021 16:58:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Subject: [RFC PATCH 1/5] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction Date: Wed, 24 Feb 2021 16:58:07 +0000 Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210224165811.11567-1-alex.bennee@linaro.org> References: <20210224165811.11567-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , cota@braap.org, =?utf-8?q?Alex_Be?= =?utf-8?b?bm7DqWU=?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having a function return either and valid TB and some system state seems excessive. It will make the subsequent re-factoring easier if we lookup the current state where we are. Signed-off-by: Alex Bennée --- include/exec/tb-lookup.h | 18 ++++++++---------- accel/tcg/cpu-exec.c | 10 ++++++++-- accel/tcg/tcg-runtime.c | 4 +++- 3 files changed, 19 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9cf475bb03..62a509535d 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -17,30 +17,28 @@ #include "exec/tb-hash.h" /* Might cause an exception, so have a longjmp destination ready */ -static inline TranslationBlock * -tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base, - uint32_t *flags, uint32_t cf_mask) +static inline TranslationBlock * tb_lookup(CPUState *cpu, + target_ulong pc, target_ulong cs_base, + uint32_t flags, uint32_t cf_mask) { - CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; uint32_t hash; - cpu_get_tb_cpu_state(env, pc, cs_base, flags); - hash = tb_jmp_cache_hash_func(*pc); + hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); cf_mask &= ~CF_CLUSTER_MASK; cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; if (likely(tb && - tb->pc == *pc && - tb->cs_base == *cs_base && - tb->flags == *flags && + tb->pc == pc && + tb->cs_base == cs_base && + tb->flags == flags && tb->trace_vcpu_dstate == *cpu->trace_dstate && (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) { return tb; } - tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask); + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); if (tb == NULL) { return NULL; } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd..ef96b312a1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -245,6 +245,7 @@ static void cpu_exec_exit(CPUState *cpu) void cpu_exec_step_atomic(CPUState *cpu) { + CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -258,7 +259,9 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running = true; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); @@ -418,11 +421,14 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit, uint32_t cf_mask) { + CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + + tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d736f4ff55..05e3d52c2f 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -152,7 +152,9 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) target_ulong cs_base, pc; uint32_t flags; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + + tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags()); if (tb == NULL) { return tcg_code_gen_epilogue; } From patchwork Wed Feb 24 16:58:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 386868 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp529448jap; Wed, 24 Feb 2021 09:00:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJzNmEh/sV7qAo/Z7tJvk50RI1T0S26lz0fLG17rO21ve2koZ10KHa2EFqgZom3LpIpCZOd0 X-Received: by 2002:a92:d312:: with SMTP id x18mr13578909ila.70.1614186013468; Wed, 24 Feb 2021 09:00:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614186013; cv=none; d=google.com; s=arc-20160816; b=qQs42TzJ3R4yckcHgw8ZRAbGvZGIANzXm4dJ7RlPWe466MWcL+vE8TMeWL5gsfUo+Z 2XjQl9+6p9WrHxMa9bQ7sYLizk+bSmQ4RzoZNQBmzrYsDTiWyIKgjaO2a3Uxy10ssB+n uMW/eZKkj2SZSZJZzbeEaQC6aEDt4B6YawMRNlSei0MidNYumf7Urbt5C6ucLFsYF1yB XUzG0+8Q4mUtOtB8kS8tXTBvVuCwSkRXc329bkWo5W4rwN9r6pkPZhTG2+RUyppstWUQ V6Tywe3cDiKFdciT+eC98duxFWc6P6Aq3mOMq3sOK7nqQq+VtUttr4qSvijVtFamakDC Mkfg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id y12si2457548ilv.132.2021.02.24.09.00.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Feb 2021 09:00:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=z4Twsl1g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lExWG-0003KH-PV for patch@linaro.org; Wed, 24 Feb 2021 12:00:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lExUW-0003Ho-QM for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:24 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:36433) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lExUP-000748-Ne for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:24 -0500 Received: by mail-wm1-x329.google.com with SMTP id k66so2469466wmf.1 for ; Wed, 24 Feb 2021 08:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5tflN3q79KkPgu1AfUv+9Ai33YagcdoNXpl6kgnHQ88=; b=z4Twsl1gqeIe/EEbGMuM5b4V0pKi6+P+BW8EsYTsPf16XwGkVUf2i2Mafqce7kSwwE 9WBhYblXsWfdBhK6+ygiXyu3a6ySOGUf9gT5lwGWJyuZ3Li0vp+89BAz8lsFz4SkyUko UzVfKeFKJVb21vYpeeNuJni7V19a8VJ1wtE/wn4WxvfBQQlc9IrKPwlIZokFpzlCjWvj IK19bqJRTs77vk4rhw+oDp/QHRcjtV+2+2IIPYn/XVPM8JTCwt3tJhN6vwYNXKyCu7Ba AOPoH75fO5W7dt1NIl3F1p9olzZJQ3A4vDhlsIZSB5Ai2ktma+TqEVKMPrdlhNX9nNis 6Tww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5tflN3q79KkPgu1AfUv+9Ai33YagcdoNXpl6kgnHQ88=; b=Q8Yxlmx869fIjhcKyquInWcobFxt+ESMZuQgEv5/Ne2NjAsEJrhEAnQSwQZgCVxwj0 tEXZYCYSBQ/GqG/nni1HESE5rOuXlD42qeLJAZMXxoAMRC6JV8RFX8Oy5nVtLI9ITY3Q Pwd4mEFAufS0w0h4KvwMRnSW9+w4Db9krL/Yva8NPO5/ToHIWrvjpWh4GqQi/sA1IEu1 F4ZayeG5z0+2j+6xYezjwOVba2DP2uR9iMdlllRI7YYp0SjKOioixl23eePvYwKa6ZJV 5hFdXsDdhnfoxwxWHWdIq1HCE4PZoTsTIZrOmTfqjFEN3XNkRgFR228O7cJyXRVaSYjY 71gA== X-Gm-Message-State: AOAM532/JyppIR20/HMZuNCQBZAJtmryXvnWZYob/qTDMqjrUwLT+JpY lxNCDY3DjWn2majlN+SWqDSzyA== X-Received: by 2002:a7b:c957:: with SMTP id i23mr4502790wml.32.1614185896330; Wed, 24 Feb 2021 08:58:16 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 2sm5001720wre.24.2021.02.24.08.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 08:58:12 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9C0561FF8C; Wed, 24 Feb 2021 16:58:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Subject: [RFC PATCH 2/5] accel/tcg: move CF_CLUSTER calculation to curr_cflags Date: Wed, 24 Feb 2021 16:58:08 +0000 Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210224165811.11567-1-alex.bennee@linaro.org> References: <20210224165811.11567-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , cota@braap.org, =?utf-8?q?Alex_Be?= =?utf-8?b?bm7DqWU=?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing special about this compile flag that doesn't mean we can't just compute it with curr_cflags() which we should be using when building a new set. Signed-off-by: Alex Bennée --- include/exec/exec-all.h | 8 +++++--- include/exec/tb-lookup.h | 3 --- accel/tcg/cpu-exec.c | 9 ++++----- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 6 +++--- softmmu/physmem.c | 2 +- 6 files changed, 14 insertions(+), 16 deletions(-) -- 2.20.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b7b3c0ef12..1a69c07add 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -519,10 +519,12 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb) } /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(void) +static inline uint32_t curr_cflags(CPUState *cpu) { - return (parallel_cpus ? CF_PARALLEL : 0) - | (icount_enabled() ? CF_USE_ICOUNT : 0); + uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index); + cflags |= parallel_cpus ? CF_PARALLEL : 0; + cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; + return cflags; } /* TranslationBlock invalidate API */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 62a509535d..b2247d458b 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -27,9 +27,6 @@ static inline TranslationBlock * tb_lookup(CPUState *cpu, hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); - cf_mask &= ~CF_CLUSTER_MASK; - cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; - if (likely(tb && tb->pc == pc && tb->cs_base == cs_base && diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef96b312a1..45286dc4b3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -249,8 +249,7 @@ void cpu_exec_step_atomic(CPUState *cpu) TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - uint32_t cflags = 1; - uint32_t cf_mask = cflags & CF_HASH_MASK; + uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1; int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { @@ -260,7 +259,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running = true; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); @@ -497,7 +496,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_has_exception() && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ - cpu->cflags_next_tb = (curr_cflags() & ~CF_USE_ICOUNT) | 1; + cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | 1; } #endif return false; @@ -794,7 +793,7 @@ int cpu_exec(CPUState *cpu) have CF_INVALID set, -1 is a convenient invalid value that does not require tcg headers for cpu_common_reset. */ if (cflags == -1) { - cflags = curr_cflags(); + cflags = curr_cflags(cpu); } else { cpu->cflags_next_tb = -1; } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 05e3d52c2f..99403e3eb3 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -154,7 +154,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags()); + tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); if (tb == NULL) { return tcg_code_gen_epilogue; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbd919a393..f29b47f090 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2194,7 +2194,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } @@ -2362,7 +2362,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); return true; } #endif @@ -2438,7 +2438,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * operations only (which execute after completion) so we don't * double instrument the instruction. */ - cpu->cflags_next_tb = curr_cflags() | CF_MEMI_ONLY | CF_LAST_IO | n; + cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n; qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "cpu_io_recompile: rewound execution of TB to " diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 19e0aa9836..7e8b0fab89 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -937,7 +937,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu_loop_exit_restore(cpu, ra); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); mmap_unlock(); if (ra) { cpu_restore_state(cpu, ra, true); From patchwork Wed Feb 24 16:58:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 386871 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp535385jap; Wed, 24 Feb 2021 09:06:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJxyKa8Cilp1mfqgFJ52vN/bNq56Jvj+Sl/L0pUocjbqRE/75rePvCXm+c8Khs4zBUYpTEiX X-Received: by 2002:a05:6e02:103:: with SMTP id t3mr21273703ilm.102.1614186408584; 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[209.51.188.17]) by mx.google.com with ESMTPS id k23si2198746ios.16.2021.02.24.09.06.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Feb 2021 09:06:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="e/E81CVc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lExcd-0001U8-Uw for patch@linaro.org; Wed, 24 Feb 2021 12:06:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lExUX-0003IC-1D for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:25 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:51455) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lExUT-00075L-Gc for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:24 -0500 Received: by mail-wm1-x332.google.com with SMTP id j187so2396462wmj.1 for ; Wed, 24 Feb 2021 08:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ijUHy5f8z4m3eStoJmSo8NsJPN9+rPCEGdu4/3Xebsg=; b=e/E81CVcf+WoBZaFlPzK8MY1sYSXbQK/p4YBNi6joPiZc4+L3e/MGOp1lGOwo8TckW 4xm8LPgEyNX5hCPpF3TRvaPuOJy2YHk2ynV5fpMFGXkkaUqVt1hz6CfIC88k6VxLnqt/ 06uo4iCW885BqMMjV5zsT7fRl/izdKLRpOrF+VQWOnfSaw3FkJRMvd+OwlZg6zOvGqdt 2wVJNLXdYAIyb7Xd6wrXPhlg/aE3NUkfHZ3+ZwZF60yz7WN1Tydh/O86JF/u4stMqJTa htrM1GhAN1p3NH95mY2VX9+eFevQeEJ/+x/tV7xx4iAcCTvgVV7rstRTsO8aDaczQ5e7 i3iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijUHy5f8z4m3eStoJmSo8NsJPN9+rPCEGdu4/3Xebsg=; b=owi36V4P6yAYjrmi7emlWVDu51NHJ9sjk9i0XoBogctyWz2beisH9qFxtodOHxB+tw ntmFObVj8kQDmHBphZl/egIUB0glWmDTP1+4gZiSmQ3vtSOk45oP9g/C0Vx8+YvJPAjT u6446M0HIFktR2Mov/LIpGCNHkHYBdumzdmlTQsK+ncEiluB4zEbb226GTAjW5sdSdsz ydzJxu2uuw9jyAiftEKvxwFrppiega+pkI5U9/chsswGDn+2AeU2UBZZEJwdjTxdX1YL jQvug37mXqcuRefnRS3MATaFg00HF954M2fhj0kYrj7w2LEkwZEpW7nItxGuglO+awAT qG+g== X-Gm-Message-State: AOAM532wNh3OcAasAKU4/TPVhTeUmv8AFR01VW7YjRlZvP+WRBLPS0Jo Po1n2QQv5lKwAKuiKsAHYtE2NA== X-Received: by 2002:a7b:ca49:: with SMTP id m9mr4393004wml.89.1614185899386; Wed, 24 Feb 2021 08:58:19 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q15sm4909769wrr.58.2021.02.24.08.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 08:58:16 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B9D251FF8F; Wed, 24 Feb 2021 16:58:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Subject: [RFC PATCH 3/5] accel/tcg: drop the use of CF_HASH_MASK and rename params Date: Wed, 24 Feb 2021 16:58:09 +0000 Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210224165811.11567-1-alex.bennee@linaro.org> References: <20210224165811.11567-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , cota@braap.org, =?utf-8?q?Alex_Be?= =?utf-8?b?bm7DqWU=?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We don't really deal in cf_mask most of the time. The one time it's relevant is when we want to remove an invalidated TB from the QHT lookup. Everywhere else we should be looking up things without CF_INVALID set. Signed-off-by: Alex Bennée --- include/exec/exec-all.h | 4 +--- include/exec/tb-lookup.h | 9 ++++++--- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 8 +++++--- 5 files changed, 21 insertions(+), 18 deletions(-) -- 2.20.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 1a69c07add..acf66ab692 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -460,8 +460,6 @@ struct TranslationBlock { #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 -/* cflags' mask for hashing/comparison, basically ignore CF_INVALID */ -#define CF_HASH_MASK (~CF_INVALID) /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; @@ -538,7 +536,7 @@ void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, - uint32_t cf_mask); + uint32_t cflags); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); /* GETPC is the true target of the return instruction that we'll execute. */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index b2247d458b..7b70412fae 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -19,11 +19,14 @@ /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock * tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, - uint32_t flags, uint32_t cf_mask) + uint32_t flags, uint32_t cflags) { TranslationBlock *tb; uint32_t hash; + /* we should never be trying to look up an INVALID tb */ + tcg_debug_assert(!(cflags & CF_INVALID)); + hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); @@ -32,10 +35,10 @@ static inline TranslationBlock * tb_lookup(CPUState *cpu, tb->cs_base == cs_base && tb->flags == flags && tb->trace_vcpu_dstate == *cpu->trace_dstate && - (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) { + tb_cflags(tb) == cflags)) { return tb; } - tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { return NULL; } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 45286dc4b3..931da96c2b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -307,7 +307,7 @@ struct tb_desc { CPUArchState *env; tb_page_addr_t phys_page1; uint32_t flags; - uint32_t cf_mask; + uint32_t cflags; uint32_t trace_vcpu_dstate; }; @@ -321,7 +321,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) tb->cs_base == desc->cs_base && tb->flags == desc->flags && tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && - (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) { + tb_cflags(tb) == desc->cflags) { /* check next page if needed */ if (tb->page_addr[1] == -1) { return true; @@ -341,7 +341,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, - uint32_t cf_mask) + uint32_t cflags) { tb_page_addr_t phys_pc; struct tb_desc desc; @@ -350,7 +350,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, desc.env = (CPUArchState *)cpu->env_ptr; desc.cs_base = cs_base; desc.flags = flags; - desc.cf_mask = cf_mask; + desc.cflags = cflags; desc.trace_vcpu_dstate = *cpu->trace_dstate; desc.pc = pc; phys_pc = get_page_addr_code(desc.env, pc); @@ -358,7 +358,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, return NULL; } desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; - h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); + h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } @@ -418,7 +418,7 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, - int tb_exit, uint32_t cf_mask) + int tb_exit, uint32_t cflags) { CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; @@ -427,10 +427,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu, cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); - tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask); + tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup */ qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 99403e3eb3..49f5de37e8 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,10 +27,10 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" #include "tcg/tcg.h" +#include "exec/tb-lookup.h" /* 32-bit helpers */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f29b47f090..0b0bfd35ab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1311,7 +1311,7 @@ static bool tb_cmp(const void *ap, const void *bp) return a->pc == b->pc && a->cs_base == b->cs_base && a->flags == b->flags && - (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) && + (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && a->trace_vcpu_dstate == b->trace_vcpu_dstate && a->page_addr[0] == b->page_addr[0] && a->page_addr[1] == b->page_addr[1]; @@ -1616,6 +1616,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) PageDesc *p; uint32_t h; tb_page_addr_t phys_pc; + uint32_t orig_cflags = tb_cflags(tb); assert_memory_lock(); @@ -1626,7 +1627,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) /* remove the TB from the hash list */ phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK, + h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1793,6 +1794,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, uint32_t h; assert_memory_lock(); + tcg_debug_assert(!(tb->cflags & CF_INVALID)); /* * Add the TB to the page list, acquiring first the pages's locks. @@ -1811,7 +1813,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, } /* add in the hash table */ - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK, + h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, tb->trace_vcpu_dstate); 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[209.51.188.17]) by mx.google.com with ESMTPS id x19si2328414jat.82.2021.02.24.09.03.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Feb 2021 09:03:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JnfwqPtZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lExZs-0005gL-LE for patch@linaro.org; Wed, 24 Feb 2021 12:03:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lExUT-0003GF-S6 for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:21 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:40041) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lExUR-00074j-CK for qemu-devel@nongnu.org; Wed, 24 Feb 2021 11:58:21 -0500 Received: by mail-wm1-x336.google.com with SMTP id l13so2454574wmg.5 for ; Wed, 24 Feb 2021 08:58:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z5aRHBbMC4Mouk4nv3EKL6EACIbK+IoheJgxjehumZ4=; b=JnfwqPtZLP8NBpJI1qfu8vTCF8uTHPoQmTSJPaCz0RtOH3N4PhxCVBJ4Uj5aWu2qly G7SaZSOZDIfYkNw2t6BG9n/3M9VEkEKCzla7fsQrJm2biRnFJYYzeS7a+rQ9wi2111Bb 4i2DTxPXBDvk/DhpD5f9uMT7gDNiKNYhg913fo3xZWzabuesz3HOxbt6LjLLlG4NZNo5 mb3SJnhy6vvcI/6iMD4z3m+Vp7XkfOKL4eUbv+5avoO92v9W1oKI0HSQULS3g8fAJ59A G2rPG8/foSZNbozq3scIO24jpt/j9f100Mkx3rPkKB6NJitg0VpmvP4Y6B5P9eEzjxJ/ 6lnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z5aRHBbMC4Mouk4nv3EKL6EACIbK+IoheJgxjehumZ4=; b=moXEHOr63Gf6QWI1xW1DeM9PaJ1j7EPBGuW9rBF5kqnoe1OyCtkmpFpW1ya/0e0Zoi rW6CE7sr48pHTL0OPWO3tKe4DTd2j1gXfgzHxOk8MI3MpQdnA4kH7GCrYfIqA90s07Gc rsExrbAKJmDMGaRk97CU3hdAaxF4e5Ch46m0QliyV97TGG9H+RMAVQAuHbO8L4GgprTR FFaroY66uZjmqU0gxHYkskJestZw/H2iTtTYO7XOu0esQCILSnqtMSjkkuMxO2yJEzsE QW2WB/SKatOplS4BOl6V/fFztl/vQIPouqPO+pJdErL97HXP2yOsQhjnrADE/8OXtKUh ZrEQ== X-Gm-Message-State: AOAM532Xi69GqBJsVzNxumzYGhhxConQAxAaMjTvigL0/A/iSiEJ8bQI lG5766QHCsv+3/mXcH+ObSWPfw== X-Received: by 2002:a1c:23c2:: with SMTP id j185mr4614005wmj.96.1614185897355; Wed, 24 Feb 2021 08:58:17 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id o10sm4246718wrx.5.2021.02.24.08.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 08:58:16 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D06111FF90; Wed, 24 Feb 2021 16:58:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Subject: [RFC PATCH 4/5] include/exec: lightly re-arrange TranslationBlock Date: Wed, 24 Feb 2021 16:58:10 +0000 Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210224165811.11567-1-alex.bennee@linaro.org> References: <20210224165811.11567-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , cota@braap.org, =?utf-8?q?Alex_Be?= =?utf-8?b?bm7DqWU=?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Lets make sure all the flags we compare when looking up blocks are together in the same place. Signed-off-by: Alex Bennée --- include/exec/exec-all.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index acf66ab692..75f8c3981a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -448,9 +448,6 @@ struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was generated */ - uint16_t size; /* size of target code for this block (1 <= - size <= TARGET_PAGE_SIZE) */ - uint16_t icount; uint32_t cflags; /* compile flags */ #define CF_COUNT_MASK 0x00007fff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ @@ -464,6 +461,11 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; + /* Above fields used for comparing */ + uint16_t size; /* size of target code for this block (1 <= + size <= TARGET_PAGE_SIZE) */ + uint16_t icount; + struct tb_tc tc; /* first and second physical page containing code. The lower bit From patchwork Wed Feb 24 16:58:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 386872 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp538688jap; Wed, 24 Feb 2021 09:11:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJwruTzUcPaL1oAqHiDN8eRx82in2Leg7mNTUyV+aqmIw1IlPCcDE0n3RYG2KVm242P93U5A X-Received: by 2002:a5d:9c8a:: with SMTP id p10mr25638123iop.182.1614186663713; Wed, 24 Feb 2021 09:11:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614186663; cv=none; d=google.com; s=arc-20160816; b=IRwTHiV2b42ccKx4u4ncOBQDY7L1E0CE2vDTnd2HufZHOF9ceZhbyhTtb2dXWx1Yol zcrSsZYaz+7SrAiEWoGZuxaS0UhUb4NH2EzcVD4PmDhrxxzrk3EjPxaQoZnqxv4toWLR wFu0DBK0cv4DRDwiCDLD7kMqZUAVqpgqKjQRBo1TZW/NKXzasReXCE++GXlSeV8eKRa+ NgR9SZ+rXqdZxYSFABWt3Csnb9Ggku3X0m9INCcDMB5aORxNqnQuSPfKWKYasHCL/aGe rSqJI6LeYJRqEe4MiQ7Wk6GKhm/r2DXQtffT15jmT+5cTqe2p3/aZZJ8FglMMRIpkrkv nj2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wBGoBkcvwiIvW/STPkt2r5KSBRzV20ncmjwyfXsyDe0=; b=ay/wQUtW68GHDIElev2gE6w/uQnkXYzpbswzW/clHHJcSy+EdzlzS97tCmUOeRx3Sm nv8fdxGwvoGcL1VfbdolOcDFlSSR2Ls0vV2IoKx1iARLm0bf3MkD7PFhRQTtXJ9wjsVk lsWMb6RdeEB0vEERuO5yRrTVreFUI61qvp7kvixFzGu5TjVIHJKG89POYWiNNRj8X1kF 6mmQnkya4qcGLZIfYPPsS5+yT7Poa5/POI8PixcWnvkcqi4jU7cEefT78TYjNZt6KPlQ oa25nk7E3sFgDKRTS41GAZFcrf9Rt77KF3/+noPTRBnAYd6lAiA8Dw3Fp9qTmUg7W3tG vy+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ahQG4IMb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[AJB: looking at perf I can't see much change. Basically the hotspot seems to be the initial load of the TB parameters. If this reflects the stall of the memory bus loading TB fields I guess this means there isn't much more to be squeezed out here: helper_lookup_tb_ptr() /home/alex/lsrc/qemu.git/builds/arm.all/qemu-system-aarch64 Event: cycles:ppp Percent Disassembly of section .text: 0000000000809c40 : helper_lookup_tb_ptr(): { return ctpop64(arg); } const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { 4.14 push %r13 1.32 push %r12 env_cpu(): * * Return the CPUState associated with the environment. */ static inline CPUState *env_cpu(CPUArchState *env) { return &env_archcpu(env)->parent_obj; 0.47 lea -0x9dc0(%rdi),%r12 helper_lookup_tb_ptr(): 0.80 push %rbp 0.40 mov %rdi,%rbp 0.90 push %rbx 1.59 sub $0x28,%rsp 1.95 mov %fs:0x28,%rax 2.28 mov %rax,0x18(%rsp) 0.51 xor %eax,%eax CPUState *cpu = env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); 0.98 lea 0x4(%rsp),%rcx 0.66 lea 0x8(%rsp),%rdx 1.09 lea 0x10(%rsp),%rsi 2.08 → callq cpu_get_tb_cpu_state tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); 1.19 mov 0x10(%rsp),%rsi 1.03 mov 0x4(%rsp),%r9d deposit32(): uint32_t fieldval) { uint32_t mask; assert(start >= 0 && length > 0 && length <= 32 - start); mask = (~0U >> (32 - length)) << start; return (value & ~mask) | ((fieldval << start) & mask); 2.53 mov -0x1b24(%rbp),%r8d 0.55 lea parallel_cpus,%rdx tb_jmp_cache_hash_func(): } static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) { target_ulong tmp; tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); 0.09 mov %rsi,%rdi deposit32(): 0.62 shl $0x18,%r8d curr_cflags(): /* current cflags for hashing/comparison */ static inline uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index); cflags |= parallel_cpus ? CF_PARALLEL : 0; 1.80 mov %r8d,%eax 0.92 or $0x80000,%eax 1.45 cmpb $0x0,(%rdx) 0.84 lea use_icount,%rdx 3.13 cmovne %eax,%r8d cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; 0.62 mov (%rdx),%ecx helper_lookup_tb_ptr(): 0.60 mov 0x8(%rsp),%rdx 1.95 mov %r8d,%eax 0.60 or $0x20000,%eax 0.45 test %ecx,%ecx 3.70 cmovne %eax,%r8d tb_jmp_cache_hash_func(): 0.47 lea target_page,%rax 0.55 mov 0x4(%rax),%ecx 0.55 sub $0x6,%ecx 3.17 shr %cl,%rdi 0.53 xor %rsi,%rdi return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) 1.74 mov %rdi,%rax | (tmp & TB_JMP_ADDR_MASK)); 0.50 and $0x3f,%edi return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) 2.85 shr %cl,%rax 0.31 and $0xfc0,%eax | (tmp & TB_JMP_ADDR_MASK)); 0.36 or %edi,%eax tb_lookup(): /* we should never be trying to look up an INVALID tb */ tcg_debug_assert(!(cflags & CF_INVALID)); hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); 2.26 lea 0x210(%r12,%rax,8),%r13 5.86 mov 0x0(%r13),%rbx if (likely(tb)) { 0.38 test %rbx,%rbx 0.00 ↓ je e7 uint64_t bits = tb->pc ^ pc; 6.77 mov (%rbx),%rax bits |= tb->cs_base ^ cs_base; 0.75 mov 0x8(%rbx),%rcx uint64_t bits = tb->pc ^ pc; 1.67 xor %rsi,%rax bits |= tb->cs_base ^ cs_base; 0.83 xor %rdx,%rcx 0.95 or %rax,%rcx bits |= tb->flags ^ flags; 0.05 mov %r9d,%eax 1.63 xor 0x10(%rbx),%eax 2.26 or %rax,%rcx bits |= tb->trace_vcpu_dstate ^ *cpu->trace_dstate; 0.08 mov 0x18(%rbx),%eax 0.55 xor -0x1b38(%rbp),%rax 2.45 or %rcx,%rax tb_cflags(): return qatomic_read(&tb->cflags); 0.13 mov 0x14(%rbx),%ecx tb_lookup(): bits |= tb_cflags(tb) ^ cflags; 0.22 xor %r8d,%ecx if (!bits) { 3.34 or %rax,%rcx 3.69 ↓ je fe return tb; } } tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); 0.21 e7: mov %r9d,%ecx mov %r12,%rdi 0.20 → callq tb_htable_lookup 0.00 mov %rax,%rbx if (tb == NULL) { 0.02 test %rax,%rax ↓ je 130 return NULL; } qatomic_set(&cpu->tb_jmp_cache[hash], tb); 0.10 mov %rax,0x0(%r13) helper_lookup_tb_ptr(): if (tb == NULL) { return tcg_code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, 0.40 fe: lea qemu_loglevel,%rax 0.16 testb $0x20,(%rax) 0.14 ↓ jne 140 "Chain %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx "/%#x] %s\n", cpu->cpu_index, tb->tc.ptr, cs_base, pc, flags, lookup_symbol(pc)); return tb->tc.ptr; 1.69 10a: mov 0x20(%rbx),%rax } 0.18 10e: mov 0x18(%rsp),%rsi 0.34 xor %fs:0x28,%rsi 0.50 ↓ jne 188 4.48 add $0x28,%rsp 0.27 pop %rbx 0.10 pop %rbp 0.30 pop %r12 4.56 pop %r13 0.20 ← retq nop return tcg_code_gen_epilogue; 130: lea tcg_code_gen_epilogue,%rax mov (%rax),%rax ↑ jmp 10e nop qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, 140: mov 0x10(%rsp),%rdi → callq qemu_log_in_addr_range test %al,%al ↑ je 10a mov 0x10(%rsp),%rdi → callq lookup_symbol sub $0x8,%rsp mov 0x20(%rbx),%rdx mov -0x1b28(%rbp),%esi push %rax mov 0x14(%rsp),%r9d lea __PRETTY_FUNCTION__.30436+0x10,%rdi xor %eax,%eax mov 0x20(%rsp),%r8 mov 0x18(%rsp),%rcx → callq qemu_log pop %rax pop %rdx ↑ jmp 10a } 188: → callq __stack_chk_fail@plt ] Signed-off-by: Alex Bennée --- include/exec/tb-lookup.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 7b70412fae..3140abebc2 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -30,13 +30,15 @@ static inline TranslationBlock * tb_lookup(CPUState *cpu, hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); - if (likely(tb && - tb->pc == pc && - tb->cs_base == cs_base && - tb->flags == flags && - tb->trace_vcpu_dstate == *cpu->trace_dstate && - tb_cflags(tb) == cflags)) { - return tb; + if (likely(tb)) { + uint64_t bits = tb->pc ^ pc; + bits |= tb->cs_base ^ cs_base; + bits |= tb->flags ^ flags; + bits |= tb->trace_vcpu_dstate ^ *cpu->trace_dstate; + bits |= tb_cflags(tb) ^ cflags; + if (!bits) { + return tb; + } } tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) {