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Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++++++++++++++++++ .../devicetree/bindings/mtd/qcom_nandc.txt | 142 ------------- 2 files changed, 196 insertions(+), 142 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/qcom,nandc.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml new file mode 100644 index 000000000000..84ad7ff30121 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm NAND controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - qcom,ipq806x-nand + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand + + reg: + maxItems: 1 + + clocks: + items: + - description: Core Clock + - description: Always ON Clock + + clock-names: + items: + - const: core + - const: aon + + "#address-cells": true + "#size-cells": true + +patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-bus-width: + const: 8 + + nand-ecc-strength: + enum: [1, 4, 8] + + nand-ecc-step-size: + enum: + - 512 + +allOf: + - $ref: "nand-controller.yaml#" + + - if: + properties: + compatible: + contains: + const: qcom,ipq806x-nand + then: + properties: + dmas: + items: + - description: rxtx DMA channel + + dma-names: + items: + - const: rxtx + + qcom,cmd-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain the ADM command type CRCI block instance number + specified for the NAND controller on the given platform + + qcom,data-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain the ADM data type CRCI block instance number + specified for the NAND controller on the given platform + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand + + then: + properties: + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot-nand"; + reg = <0 0x58a0000>; + }; + + partition@58a0000 { + label = "fs-nand"; + reg = <0x58a0000 0x4000000>; + }; + }; + }; + }; + + #include + nand-controller@79b0000 { + compatible = "qcom,ipq4019-nand"; + reg = <0x79b0000 0x1000>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpicbam 0>, + <&qpicbam 1>, + <&qpicbam 2>; + dma-names = "tx", "rx", "cmd"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot-nand"; + reg = <0 0x58a0000>; + }; + + partition@58a0000 { + label = "fs-nand"; + reg = <0x58a0000 0x4000000>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt deleted file mode 100644 index 5647913d8837..000000000000 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ /dev/null @@ -1,142 +0,0 @@ -* Qualcomm NAND controller - -Required properties: -- compatible: must be one of the following: - * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x - SoC and it uses ADM DMA - * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in - IPQ4019 SoC and it uses BAM DMA - * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in - IPQ6018 SoC and it uses BAM DMA - * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in - IPQ8074 SoC and it uses BAM DMA - * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in - SDX55 SoC and it uses BAM DMA - -- reg: MMIO address range -- clocks: must contain core clock and always on clock -- clock-names: must contain "core" for the core clock and "aon" for the - always on clock - -EBI2 specific properties: -- dmas: DMA specifier, consisting of a phandle to the ADM DMA - controller node and the channel number to be used for - NAND. Refer to dma.txt and qcom_adm.txt for more details -- dma-names: must be "rxtx" -- qcom,cmd-crci: must contain the ADM command type CRCI block instance - number specified for the NAND controller on the given - platform -- qcom,data-crci: must contain the ADM data type CRCI block instance - number specified for the NAND controller on the given - platform - -QPIC specific properties: -- dmas: DMA specifier, consisting of a phandle to the BAM DMA - and the channel number to be used for NAND. Refer to - dma.txt, qcom_bam_dma.txt for more details -- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" -- #address-cells: <1> - subnodes give the chip-select number -- #size-cells: <0> - -* NAND chip-select - -Each controller may contain one or more subnodes to represent enabled -chip-selects which (may) contain NAND flash chips. Their properties are as -follows. - -Required properties: -- reg: a single integer representing the chip-select - number (e.g., 0, 1, 2, etc.) -- #address-cells: see partition.txt -- #size-cells: see partition.txt - -Optional properties: -- nand-bus-width: see nand-controller.yaml -- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will - be used according to chip requirement and available - OOB size. - -Each nandcs device node may optionally contain a 'partitions' sub-node, which -further contains sub-nodes describing the flash partition mapping. See -partition.txt for more detail. - -Example: - -nand-controller@1ac00000 { - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; - - dmas = <&adm_dma 3>; - dma-names = "rxtx"; - qcom,cmd-crci = <15>; - qcom,data-crci = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; - -nand-controller@79b0000 { - compatible = "qcom,ipq4019-nand"; - reg = <0x79b0000 0x1000>; - - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpicbam 0>, - <&qpicbam 1>, - <&qpicbam 2>; - dma-names = "tx", "rx", "cmd"; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; From patchwork Thu Feb 25 14:08:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 387214 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp342226jap; Thu, 25 Feb 2021 06:09:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJxNs5fv1yzxdez795DhgZFH37r38/iLSKGa19KsiT13WuQTZMyn/NuPirdmCZeNCafXAKrc X-Received: by 2002:ac8:4554:: with SMTP id z20mr2535115qtn.269.1614262183391; Thu, 25 Feb 2021 06:09:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614262183; cv=none; d=google.com; s=arc-20160816; b=sMSO7fGjQo3Qm1AR33acnzsqXl7xoxT1xS30a3Mn8qr26JR9dZF5Usxn1gImmCI8EK NVZC7U51d1ZjG9tDcnZc2oDTrXtT+FZGHnZQRlqV6lCd0tjIFKRrSIQXmEKj0RBXUarB 7625axlhmhfYOI40lEEjDavx/1ruVLi5ILZqRQkZPp6/jTvb8CW3wigWTFqSyLb8IED/ Z126vXsMEea0fj4SJw8vf7u3qzuKbqmQOq+6Ve8RBwUDX0UC2auLKeMxeT6+xvRh/VNB y9oo1GTh57uLlh7BpjGvurjVCY6WUDOZbuhdT0VDxELN54XEHn7LQvpr8eGiX1QCYmxw PTyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:dkim-signature; bh=kGA34IiC07gMaNpvWZ3SlVzmO+WkpIR6wst1MR+hnk0=; b=drN1GfnRehrDWtMdymqGm6SSqGhfTUBmMi5fYtkpgn/7DI8RcB/R3OHjIY1xnXOt7I vTZKb99gHYX+YxQddBoRMoK/63Q5s3JqB03J+AY9YgVSA4xA7wezxc2cucnk8jixMw7s cQDmEKOivcfWIBuSrqByTd7ggAx18IY5xMvJoLwxIB9/tJxaw+q7YBlJAAlfvT/53sHQ ph75qgKcctcMQCPkwyEDpq3MHVyAZm0pC8T78+fLMLAqK1OIlVo7NrDx5gCh/xuWyOZ7 DhJ9dZxIP1ngT5PUGzUHiQiOYCCKDW9g4cKxR3B5hFegeAjekP3cXY/+LPqCzHvcSn4G uDAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lists.infradead.org header.s=merlin.20170209 header.b=QAAEAAIe; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QQq9Hyp6; spf=pass (google.com: best guess record for domain of linux-mtd-bounces+patch=linaro.org@lists.infradead.org designates 2001:8b0:10b:1231::1 as permitted sender) smtp.mailfrom="linux-mtd-bounces+patch=linaro.org@lists.infradead.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from merlin.infradead.org (merlin.infradead.org. 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Thu, 25 Feb 2021 06:09:20 -0800 (PST) Received: from localhost.localdomain ([103.66.79.45]) by smtp.gmail.com with ESMTPSA id f3sm6228918pfe.25.2021.02.25.06.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 06:09:19 -0800 (PST) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Subject: [PATCH v3 2/3] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Date: Thu, 25 Feb 2021 19:38:41 +0530 Message-Id: <20210225140842.66927-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210225140842.66927-1-manivannan.sadhasivam@linaro.org> References: <20210225140842.66927-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210225_090922_478490_327CF57C X-CRM114-Status: GOOD ( 12.52 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [103.66.79.45 listed in dnsbl.sorbs.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:530 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Daniele.Palmas@telit.com, Manivannan Sadhasivam , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+patch=linaro.org@lists.infradead.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). So let's add a property for declaring such secure regions so that the drivers can skip touching them. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index d0e422f4b3e0..acc7dfd6ef28 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -143,6 +143,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. + secure-regions: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Regions in the NAND chip which are protected using a secure element + like Trustzone. This property contains the start address and size of + the secure regions present. + required: - reg From patchwork Thu Feb 25 14:08:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 387215 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp342350jap; Thu, 25 Feb 2021 06:09:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJzBHidi1bx82lGgzY20wHGH+RhlyKkbmAxnWox5f0bO4j9FKCsktTBgj9HtdLuoTe4Ht8c4 X-Received: by 2002:a05:622a:18d:: with SMTP id s13mr2548186qtw.52.1614262190454; Thu, 25 Feb 2021 06:09:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614262190; cv=none; d=google.com; s=arc-20160816; b=H208mYO/m1BiK0U0nm9kdbiCFucf8cH2PVW4QOR5CXdTAzK1tEoLuzEApsF/BXnIDK Ye/MCWMCjoCUmf5ayHfjw/N56aCG4+9Uty+9RHvzwDoNVpYNEP7rxOzfMZtciUxcdMdz APwo6dR0jNUkIqVmHFhgWEL6OkSEr5hnk9x0vib1qdTGknAeyi2qQtY0t577FLkXMCQQ dJH/7DCVSp9IkGVewWiwdlBtwvf9DH4c72dV0vSF4HVooXpOtkww9E6xd29kB5KcPKAN /aq0kj4GFY/f5WDwyH2fJPnIJhqoYVc26tk0Ly8okAoCfu1s7pq/kKGUy4nF+kr4qgho +sfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:dkim-signature; bh=MvpQ65JTBMNEFTz/lKZrOyFnXHGTRA7jybNfoSL7nPk=; b=LG8mr8n6HJqChK6cwnWT+uXARwvYd6nQPumMCE5PPZTFurQOzL8A11G0CcExaqHy+A uLUTYQFfvIR2pBNpX1wkzpTZULiL1lt5w8bPe1aV8CWPnUTEfW5f+1f9qoxAQrHfFQ+z YW6vnDKtuBEvxNoGexX6Fzm54iX8VRlCKvWtUFwqKSRvPmB+iRd3aYlFBUq23ee5n5sw ed+6i2+CZ97rRyUg+/sYy+bnCW2tYwrRGvRfergDppX56XFxtDyxNPQakPqnYXllP3FO 1rOk51RFPjKjUfgNszHU9A/t/mnQNW2GiCHUubficMpr/CXRSeOB8K2RvTuCHbfwN9WP Fb3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lists.infradead.org header.s=merlin.20170209 header.b=ygIPboaJ; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=wTckrcgu; spf=pass (google.com: best guess record for domain of linux-mtd-bounces+patch=linaro.org@lists.infradead.org designates 2001:8b0:10b:1231::1 as permitted sender) smtp.mailfrom="linux-mtd-bounces+patch=linaro.org@lists.infradead.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from merlin.infradead.org (merlin.infradead.org. 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Thu, 25 Feb 2021 06:09:25 -0800 (PST) Received: from localhost.localdomain ([103.66.79.45]) by smtp.gmail.com with ESMTPSA id f3sm6228918pfe.25.2021.02.25.06.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 06:09:24 -0800 (PST) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Subject: [PATCH v3 3/3] mtd: rawnand: qcom: Add support for secure regions in NAND memory Date: Thu, 25 Feb 2021 19:38:42 +0530 Message-Id: <20210225140842.66927-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210225140842.66927-1-manivannan.sadhasivam@linaro.org> References: <20210225140842.66927-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210225_090927_678279_C84A8204 X-CRM114-Status: GOOD ( 20.19 ) X-Spam-Score: 1.3 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [103.66.79.45 listed in dnsbl.sorbs.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:629 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Daniele.Palmas@telit.com, Manivannan Sadhasivam , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+patch=linaro.org@lists.infradead.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). The regions are declared using a NAND chip DT property, "secure-regions". So let's make use of this property and skip access to the secure regions present in a system. Signed-off-by: Manivannan Sadhasivam --- drivers/mtd/nand/raw/qcom_nandc.c | 72 +++++++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 9 deletions(-) -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index fd4c318b520f..d43a6d8b8779 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -431,6 +431,11 @@ struct qcom_nand_controller { * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for * ecc/non-ecc mode for the current nand flash * device + * + * @sec_regions: Array representing the secure regions in the + * NAND chip + * + * @nr_sec_regions: Number of secure regions in the NAND chip */ struct qcom_nand_host { struct nand_chip chip; @@ -453,6 +458,9 @@ struct qcom_nand_host { u32 ecc_bch_cfg; u32 clrflashstatus; u32 clrreadstatus; + + u32 *sec_regions; + u8 nr_sec_regions; }; /* @@ -662,16 +670,27 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, } /* helper to configure address register values */ -static void set_address(struct qcom_nand_host *host, u16 column, int page) +static int set_address(struct qcom_nand_host *host, u16 column, int page) { struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + u32 offs = page << chip->page_shift; + int i, j; + + /* Skip touching the secure regions if present */ + for (i = 0, j = 0; i < host->nr_sec_regions; i++, j += 2) { + if (offs >= host->sec_regions[j] && + (offs <= host->sec_regions[j] + host->sec_regions[j + 1])) + return -EIO; + } if (chip->options & NAND_BUSWIDTH_16) column >>= 1; nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); + + return 0; } /* @@ -1491,13 +1510,13 @@ static void qcom_nandc_command(struct nand_chip *chip, unsigned int command, WARN_ON(column != 0); host->use_ecc = true; - set_address(host, 0, page_addr); + ret = set_address(host, 0, page_addr); update_rw_regs(host, ecc->steps, true); break; case NAND_CMD_SEQIN: WARN_ON(column != 0); - set_address(host, 0, page_addr); + ret = set_address(host, 0, page_addr); break; case NAND_CMD_PAGEPROG: @@ -1615,7 +1634,10 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, host->use_ecc = false; clear_bam_transaction(nandc); - set_address(host, host->cw_size * cw, page); + ret = set_address(host, host->cw_size * cw, page); + if (ret) + return ret; + update_rw_regs(host, 1, true); config_nand_page_read(nandc); @@ -1943,7 +1965,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) /* prepare a clean read buffer */ memset(nandc->data_buffer, 0xff, size); - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, true); config_nand_single_cw_page_read(nandc, host->use_ecc); @@ -2005,12 +2030,16 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret; clear_read_regs(nandc); clear_bam_transaction(nandc); host->use_ecc = true; - set_address(host, 0, page); + ret = set_address(host, 0, page); + if (ret) + return ret; + update_rw_regs(host, ecc->steps, true); return read_page_ecc(host, NULL, chip->oob_poi, page); @@ -2188,7 +2217,10 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, 0, mtd->oobavail); - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, false); config_nand_page_write(nandc); @@ -2267,7 +2299,10 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs) /* prepare write */ host->use_ecc = false; - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, false); config_nand_page_write(nandc); @@ -2830,7 +2865,8 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, struct nand_chip *chip = &host->chip; struct mtd_info *mtd = nand_to_mtd(chip); struct device *dev = nandc->dev; - int ret; + struct property *prop; + int ret, length, nr_elem; ret = of_property_read_u32(dn, "reg", &host->cs); if (ret) { @@ -2872,6 +2908,24 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, /* set up initial status value */ host->status = NAND_STATUS_READY | NAND_STATUS_WP; + /* + * Look for secure regions in the NAND chip. These regions are supposed + * to be protected by a secure element like Trustzone. So the read/write + * accesses to these regions will be blocked in the runtime by this + * driver. + */ + prop = of_find_property(dn, "secure-regions", &length); + if (prop) { + nr_elem = length / sizeof(u32); + host->nr_sec_regions = nr_elem / 2; + + host->sec_regions = devm_kcalloc(dev, nr_elem, sizeof(u32), GFP_KERNEL); + if (!host->sec_regions) + return -ENOMEM; + + of_property_read_u32_array(dn, "secure-regions", host->sec_regions, nr_elem); + } + ret = nand_scan(chip, 1); if (ret) return ret;