From patchwork Thu Apr 6 13:16:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96963 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726462qgd; Thu, 6 Apr 2017 06:16:25 -0700 (PDT) X-Received: by 10.99.168.77 with SMTP id i13mr36394495pgp.148.1491484585657; Thu, 06 Apr 2017 06:16:25 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a124si1854401pgc.127.2017.04.06.06.16.25; Thu, 06 Apr 2017 06:16:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934685AbdDFNQY (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:24 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:33989 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934669AbdDFNQX (ORCPT ); Thu, 6 Apr 2017 09:16:23 -0400 Received: by mail-pg0-f42.google.com with SMTP id 21so36266598pgg.1 for ; Thu, 06 Apr 2017 06:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2qzTIGFs3L0mztVJdTVFkEpOYYzGyqGXntBjbBY9I+I=; b=ZFTDxttmwtRn0VV0FyqZiB+VZxa1ySPlixIp5DSBU9rt/FsYbiub065FmnkqA7tLO4 cW1JmRZoYkLedqFGSgduOa59e4WrGD+xs3bEntc+9KSBTQ6Q9rtBorktk1ovHLZMSV7i hviGzodH4YASVZV/nxsXrZVu2Lu8urusMW/b4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2qzTIGFs3L0mztVJdTVFkEpOYYzGyqGXntBjbBY9I+I=; b=Mh1fzCVHsBnKPBM3eakhCCxkoBrv7X5hhjf/6cFHMGRtdFvAyMTyNTS4Xj4v+nJrdn 3S5BAPf8prw2HhVWx88sBzd1vn8lOGLE/uGC4hHy8WbKCOCB5najGyJVAsn2+jlPTehn uG7p1KQG9Kwg59sfWcF49bLBezumgribBjM2eZEmHj2nnSCeUIPS8oPWeVOyEz4bfc4D F+umZO/DRBZCap5GvhPQcO2Xnc8wzDuKESvEr7ikE4k9l/X9xuJi8luTqT8ZwVvzE6MF X4awS3jF5SJsf3aaNGvje+BJXUa1pTbQ1w98jtnRsEj1rneonAJNXYrFX4cKEYIyd4zg deVg== X-Gm-Message-State: AFeK/H0F8l1J/gnOQ0RhNFRJLoD18pjAXiW2RTNOR7AOHaqZkHpONZpaHuvJnesa6cwodPWa X-Received: by 10.84.209.236 with SMTP id y99mr4120740plh.57.1491484582761; Thu, 06 Apr 2017 06:16:22 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:22 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paolo Bonzini , Chris Metcalf , Petr Mladek , Paul Burton , Aaron Tomlin , Andrew Morton , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH for-4.9 1/7] MIPS: Introduce irq_stack Date: Thu, 6 Apr 2017 18:46:07 +0530 Message-Id: <1491484573-6228-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn Allocate a per-cpu irq stack for use within interrupt handlers. Also add a utility function on_irq_stack to determine if a given stack pointer is within the irq stack for that cpu. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: Paolo Bonzini Cc: Chris Metcalf Cc: Petr Mladek Cc: James Hogan Cc: Paul Burton Cc: Aaron Tomlin Cc: Andrew Morton Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14740/ Signed-off-by: Ralf Baechle (cherry picked from commit fe8bd18ffea5327344d4ec2bf11f47951212abd0) Signed-off-by: Amit Pundir --- arch/mips/include/asm/irq.h | 12 ++++++++++++ arch/mips/kernel/asm-offsets.c | 1 + arch/mips/kernel/irq.c | 11 +++++++++++ 3 files changed, 24 insertions(+) -- 2.7.4 diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 6bf10e7..956db6e 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -17,6 +17,18 @@ #include +#define IRQ_STACK_SIZE THREAD_SIZE + +extern void *irq_stack[NR_CPUS]; + +static inline bool on_irq_stack(int cpu, unsigned long sp) +{ + unsigned long low = (unsigned long)irq_stack[cpu]; + unsigned long high = low + IRQ_STACK_SIZE; + + return (low <= sp && sp <= high); +} + #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) { diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index fae2f94..4be2763 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -102,6 +102,7 @@ void output_thread_info_defines(void) OFFSET(TI_REGS, thread_info, regs); DEFINE(_THREAD_SIZE, THREAD_SIZE); DEFINE(_THREAD_MASK, THREAD_MASK); + DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); BLANK(); } diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index f25f7ea..2b0a371 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -25,6 +25,8 @@ #include #include +void *irq_stack[NR_CPUS]; + /* * 'what should we do if we get a hw irq event on an illegal vector'. * each architecture has to answer this themselves. @@ -58,6 +60,15 @@ void __init init_IRQ(void) clear_c0_status(ST0_IM); arch_init_irq(); + + for_each_possible_cpu(i) { + int irq_pages = IRQ_STACK_SIZE / PAGE_SIZE; + void *s = (void *)__get_free_pages(GFP_KERNEL, irq_pages); + + irq_stack[i] = s; + pr_debug("CPU%d IRQ stack at 0x%p - 0x%p\n", i, + irq_stack[i], irq_stack[i] + IRQ_STACK_SIZE); + } } #ifdef CONFIG_DEBUG_STACKOVERFLOW From patchwork Thu Apr 6 13:16:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96964 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726550qgd; Thu, 6 Apr 2017 06:16:35 -0700 (PDT) X-Received: by 10.84.129.195 with SMTP id b61mr43630402plb.83.1491484595673; Thu, 06 Apr 2017 06:16:35 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12si1842368pgf.225.2017.04.06.06.16.35; Thu, 06 Apr 2017 06:16:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934716AbdDFNQe (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:34 -0400 Received: from mail-pg0-f53.google.com ([74.125.83.53]:34020 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934703AbdDFNQ2 (ORCPT ); Thu, 6 Apr 2017 09:16:28 -0400 Received: by mail-pg0-f53.google.com with SMTP id 21so36268278pgg.1 for ; Thu, 06 Apr 2017 06:16:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QpTm2mstFzN49P7nRdltjahGOnEa2B/xZtj+f3QSx/o=; b=Ly/tn45M0o8Pik9a+w+9BjkjP9iOScMSkpBHBY40Sci3ZzNkGgOT7+oi/k/IO7d2GF gIeEDeV49ocRbojvPyXhrKHmfQLPhtmkAf4+6l7AeYPiywhlqJms7SiXYRkYcAM3GAzJ Kv/seSI/yw2jur2PHsnGgZxoCxXDJVrUTEVWI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QpTm2mstFzN49P7nRdltjahGOnEa2B/xZtj+f3QSx/o=; b=qmg+XE5YODqrl1StKCwZGzgjntrt26nXUwhKthBHT2eIaFJ378TXDlYKDxm6U8hLkt QqJMExNTW2EcgFqXwzAtXOL5ILZpl02y+zFv8lM+hxpwDgK/1ymV5cOfCdwXM4MgzrQG 18HMsHhT3ralmnCMSBFJZ2nqMG+MZci55zw/x2PN9W5cFy3I7br/3VRB5mGrhiTjIilQ C0680W200Cgkk/yc/DPPXZuc6KlwxDuLmkqMtOGDiBHastmP5wTZOVN4X02VgBeLCPAB G4aNyjM4K5kfvS8Z8QpTgFLdUdmvy7bWppbxP5BsWZxLrQy1lPHgn0kVSsXmQlYDeuDV tu9g== X-Gm-Message-State: AFeK/H1FkSToDipn+eeniMLlYGGawPbK5aGyR67u+VsEYRKsWMZZpY6yukw5FWoLD9O8oPYa X-Received: by 10.98.192.151 with SMTP id g23mr35345892pfk.254.1491484587051; Thu, 06 Apr 2017 06:16:27 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:26 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Adam Buchbinder , "Maciej W . Rozycki" , Marcin Nowakowski , Chris Metcalf , Paul Burton , Jiri Slaby , Andrew Morton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.9 2/7] MIPS: Stack unwinding while on IRQ stack Date: Thu, 6 Apr 2017 18:46:08 +0530 Message-Id: <1491484573-6228-3-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn Within unwind stack, check if the stack pointer being unwound is within the CPU's irq_stack and if so use that page rather than the task's stack page. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: Adam Buchbinder Cc: Maciej W. Rozycki Cc: Marcin Nowakowski Cc: Chris Metcalf Cc: James Hogan Cc: Paul Burton Cc: Jiri Slaby Cc: Andrew Morton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14741/ Signed-off-by: Ralf Baechle (cherry picked from commit d42d8d106b0275b027c1e8992c42aecf933436ea) Signed-off-by: Amit Pundir --- arch/mips/kernel/process.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 1652f36..fbbf5fc 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -556,7 +557,19 @@ EXPORT_SYMBOL(unwind_stack_by_address); unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, unsigned long pc, unsigned long *ra) { - unsigned long stack_page = (unsigned long)task_stack_page(task); + unsigned long stack_page = 0; + int cpu; + + for_each_possible_cpu(cpu) { + if (on_irq_stack(cpu, *sp)) { + stack_page = (unsigned long)irq_stack[cpu]; + break; + } + } + + if (!stack_page) + stack_page = (unsigned long)task_stack_page(task); + return unwind_stack_by_address(stack_page, sp, pc, ra); } #endif From patchwork Thu Apr 6 13:16:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96965 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726706qgd; Thu, 6 Apr 2017 06:16:57 -0700 (PDT) X-Received: by 10.84.142.133 with SMTP id 5mr43892291plx.129.1491484616940; Thu, 06 Apr 2017 06:16:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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If an exception occurs while executing user code, the stack is switched to the kernel's stack for the current task, and register $28 is switched to point to the current_thread_info, which is at the bottom of the stack region. If the exception occurs while executing kernel code, the stack is left, and this change ensures that register $28 is not updated. This is the correct behaviour when the kernel can be executing on the separate irq stack, because the thread_info will not be at the base of it. With this change, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14742/ Signed-off-by: Ralf Baechle (cherry picked from commit 510d86362a27577f5ee23f46cfb354ad49731e61) Signed-off-by: Amit Pundir --- arch/mips/include/asm/stackframe.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index eebf395..2f182bd 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + + /* Set thread_info if we're coming from user mode */ + mfc0 k0, CP0_STATUS + sll k0, 3 /* extract cu0 bit */ + bltz k0, 9f + ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif +9: .set pop .endm From patchwork Thu Apr 6 13:16:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96969 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726901qgd; Thu, 6 Apr 2017 06:17:20 -0700 (PDT) X-Received: by 10.98.204.195 with SMTP id j64mr35440877pfk.213.1491484640812; Thu, 06 Apr 2017 06:17:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si1840150pgy.279.2017.04.06.06.17.20; Thu, 06 Apr 2017 06:17:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934737AbdDFNQx (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:53 -0400 Received: from mail-pg0-f53.google.com ([74.125.83.53]:34921 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934703AbdDFNQg (ORCPT ); Thu, 6 Apr 2017 09:16:36 -0400 Received: by mail-pg0-f53.google.com with SMTP id 81so36235510pgh.2 for ; Thu, 06 Apr 2017 06:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zkEK7Hz/6Jx2FI/7DJ9OkhDFntzd88aX40uGZLyfgX4=; b=YiDoRxmOsJqupK0Wln6lL4Kd4/LV9WMWHKD4aXOzKjJabOHP8bNzD534Yp3IBaZqAj qXvezbRmGNfmURvzcXtMYHfUv0cb9uBZsa4mEao2V98mCtKsFx210BPAARZuRZrGNiYo A88mT257R33I6d27lcDPzZl48bCO76Nday43Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zkEK7Hz/6Jx2FI/7DJ9OkhDFntzd88aX40uGZLyfgX4=; b=a8+7KgGaDV/U1RFwiQZqINS1dHNL+adEwDuyhmtADFI2pQhjm4x+TwOmbWBoxDH5Im vZb373SQ6YywAeqSS5WwD+tOH+ZYe3HLxZxSfJeLzByzLrVXgD5OU82A6bSs2eMG9t58 AjM0HZ5TEjLcVUm2ZzZ6t1OZ08HtLdqDuinK/JNWOSJxwI1ad3tim/MdlYLfiOGZPBmJ cTTwFrIyoBO4O8b032Zd0zrNGpmYQly49XvCz+i2ewCBNADoJHs/tvVzD6KojueWPien 2uGAgRfzwc+v4R8bO2cD/cI1e4YGEQeTIHsGmxnIvrhw6cIO7xHB7iyZiADSBOmrcOHe lAug== X-Gm-Message-State: AFeK/H1n4TTAaEJ6K8cyrGkt69M+tAvec5kNJB8JYox7yeBdaiNpWBK0oL5l6woLTIQz1/pw X-Received: by 10.98.68.199 with SMTP id m68mr34806899pfi.31.1491484595899; Thu, 06 Apr 2017 06:16:35 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:35 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.9 5/7] MIPS: Select HAVE_IRQ_EXIT_ON_IRQ_STACK Date: Thu, 6 Apr 2017 18:46:11 +0530 Message-Id: <1491484573-6228-6-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn Since do_IRQ is now invoked on a separate IRQ stack, we select HAVE_IRQ_EXIT_ON_IRQ_STACK so that softirq's may be invoked directly from irq_exit(), rather than requiring do_softirq_own_stack. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14744/ Signed-off-by: Ralf Baechle (cherry picked from commit 3cc3434fd6307d06b53b98ce83e76bf9807689b9) Signed-off-by: Amit Pundir --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b3c5bde..80832aa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -9,6 +9,7 @@ config MIPS select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE + select HAVE_IRQ_EXIT_ON_IRQ_STACK select HAVE_OPROFILE select HAVE_PERF_EVENTS select PERF_USE_VMALLOC From patchwork Thu Apr 6 13:16:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96966 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726711qgd; Thu, 6 Apr 2017 06:16:57 -0700 (PDT) X-Received: by 10.84.225.146 with SMTP id u18mr42720423plj.86.1491484617555; Thu, 06 Apr 2017 06:16:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o64si1864890pga.16.2017.04.06.06.16.57; Thu, 06 Apr 2017 06:16:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934632AbdDFNQt (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:49 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:34112 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933859AbdDFNQo (ORCPT ); Thu, 6 Apr 2017 09:16:44 -0400 Received: by mail-pg0-f42.google.com with SMTP id 21so36272981pgg.1 for ; Thu, 06 Apr 2017 06:16:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6iuvPjq2NXkmKqRP2BZ1DmT9HI2WCfJmxi+d3PpC3NE=; b=BxNMu/0F6n33curQFFtLZoknm6Pjs1p4aFu4evV7Y19dT9U4h2ezWL4P3JHVYGVPsy l2G+woUVoEEVHXoy5eCOvSYzSVqZT4gyCH7Lo9sHq2FYQiI9vV75lTMblrBViDFN/sj5 hR2TcH/dD1pb+mpu5+1c6pveA0ZAW3Gs27RsY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6iuvPjq2NXkmKqRP2BZ1DmT9HI2WCfJmxi+d3PpC3NE=; b=dhT3niwh3I7BCaq8jqutG4bF2rib+enw5iQqfyRXB5IH3ruDITfx5AETGV0rT8t8ry svk/LWQBuIfBFhgEjxL/mdPX9cvHw4RFYryYQM1WVjL4PKwobomMOrOf0YSoTWscx7Ba zr1pyGnpfQ1/2/Pn1Ve2007sFFNhPA0oK9pMg8av2fvj2eYSbJLPFRd20RIIu3pDBI2V Jku4ewTdp+Vs5PHDRBdAm/orPrx0XvHL3c2RDVEJVHtGgBZ8M88WtNnJjrZB2qPjScIy 5jV4Hvh+8JMluPNrrvU1NZenstItmqy7VRzx6peMt8jUbZPsJyRtosxgQxZackx5rrhz fv5g== X-Gm-Message-State: AFeK/H1qP+xy7gWFpVdAeXgB6/l/xq0eGjUIJvhX8iL9mWG5X4VJM7tnV6n1s0vvu4ep1eUo X-Received: by 10.98.76.140 with SMTP id e12mr34742844pfj.82.1491484598502; Thu, 06 Apr 2017 06:16:38 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:38 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Ralf Baechle , Paul Burton , linux-mips@linux-mips.org Subject: [PATCH for-4.9 6/7] MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch Date: Thu, 6 Apr 2017 18:46:12 +0530 Message-Id: <1491484573-6228-7-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn Commit dda45f701c9d ("MIPS: Switch to the irq_stack in interrupts") changed both the normal and vectored interrupt handlers. Unfortunately the vectored version, "except_vec_vi_handler", was incorrectly modified to unconditionally jal to plat_irq_dispatch, rather than doing a jalr to the vectored handler that has been set up. This is ok for many platforms which set the vectored handler to plat_irq_dispatch anyway, but will cause problems with platforms that use other handlers. Fixes: dda45f701c9d ("MIPS: Switch to the irq_stack in interrupts") Signed-off-by: Matt Redfearn Cc: Ralf Baechle Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15110/ Signed-off-by: James Hogan (cherry picked from commit c25f8064c1d5731a2ce5664def890140dcdd3e5c) Signed-off-by: Amit Pundir --- arch/mips/kernel/genex.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 0a7ba4b..7ec9612 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -329,7 +329,7 @@ NESTED(except_vec_vi_handler, 0, sp) PTR_ADD sp, t0, t1 2: - jal plat_irq_dispatch + jalr v0 /* Restore sp */ move sp, s1 From patchwork Thu Apr 6 13:16:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96967 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726715qgd; Thu, 6 Apr 2017 06:16:57 -0700 (PDT) X-Received: by 10.98.142.26 with SMTP id k26mr21536775pfe.30.1491484617827; Thu, 06 Apr 2017 06:16:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o64si1864890pga.16.2017.04.06.06.16.57; Thu, 06 Apr 2017 06:16:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934735AbdDFNQv (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:51 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:34967 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934359AbdDFNQm (ORCPT ); Thu, 6 Apr 2017 09:16:42 -0400 Received: by mail-pg0-f42.google.com with SMTP id 81so36237711pgh.2 for ; Thu, 06 Apr 2017 06:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bty6R6DYul67AKn+issoCh5QE2qoeZmvASm1stWPxWQ=; b=Q2x+CS5oznW/3A2GkWtTcWj95Q4jcPF2abeVqG6EeX0QwTcnVzW46IoknxOQBFl9/V 9dnxq2HISI3w/vE92wotAnlMCijbppmkIxTBoJOr/oS2jUHDRrsJKP3X/b8SOUASA8NU kjeeW/W+YwCb2eSZh1lLkMrnPF7MHs2n1QWUM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bty6R6DYul67AKn+issoCh5QE2qoeZmvASm1stWPxWQ=; b=pU4RkA8HrIVBMicwlT4vpOoq6oVhf8+nBOyQWxVmJ1HFxwN63J0pF503uPBDDwzKri oGD0rRsYPDGoVL+CoVTH0uPQWwEdF6XpGCakrPKkJf4z27gUiJbkj0sV6k3yag2Vy7gk Ox/tgY63OjKYASvutVB6ORydOs1rqlh/CVUbzoekI9/s5VHg/3v49Jgac07tA7vrQq6g z6Do97IbtGKLNgvuRPphOMNK1FCVzjF1zfKFkuVfsp3lQEkybeU2YJMVl/Maa5vMmlz/ WgBJr5dt7VgKg7TzoNpxykNPY20i00ZE863BFFcjRuZesJRjf5iakb4j1w1JJGshUuTk skDg== X-Gm-Message-State: AFeK/H2XRJz7B9KgX/5jQJtiFg3QpI6BEbslOYWJjFM68yq0XPPo5uLtp9+jX2lU49+YgVG6 X-Received: by 10.99.170.2 with SMTP id e2mr36412663pgf.0.1491484600952; Thu, 06 Apr 2017 06:16:40 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:40 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Felix Fietkau , linux-mips@linux-mips.org Subject: [PATCH for-4.9 7/7] MIPS: Lantiq: Fix cascaded IRQ setup Date: Thu, 6 Apr 2017 18:46:13 +0530 Message-Id: <1491484573-6228-8-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Felix Fietkau With the IRQ stack changes integrated, the XRX200 devices started emitting a constant stream of kernel messages like this: [ 565.415310] Spurious IRQ: CAUSE=0x1100c300 This is caused by IP0 getting handled by plat_irq_dispatch() rather than its vectored interrupt handler, which is fixed by commit de856416e714 ("MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch"). Fix plat_irq_dispatch() to handle non-vectored IPI interrupts correctly by setting up IP2-6 as proper chained IRQ handlers and calling do_IRQ for all MIPS CPU interrupts. Signed-off-by: Felix Fietkau Acked-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15077/ [james.hogan@imgtec.com: tweaked commit message] Signed-off-by: James Hogan (cherry picked from commit 6c356eda225e3ee134ed4176b9ae3a76f793f4dd) Signed-off-by: Amit Pundir --- arch/mips/lantiq/irq.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 8ac0e59..0ddf369 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -269,6 +269,11 @@ static void ltq_hw5_irqdispatch(void) DEFINE_HWx_IRQDISPATCH(5) #endif +static void ltq_hw_irq_handler(struct irq_desc *desc) +{ + ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); +} + #ifdef CONFIG_MIPS_MT_SMP void __init arch_init_ipiirq(int irq, struct irqaction *action) { @@ -313,23 +318,19 @@ static struct irqaction irq_call = { asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - - if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - for (i = 0; i < MAX_IM; i++) { - if (pending & (CAUSEF_IP2 << i)) { - ltq_hw_irqdispatch(i); - goto out; - } - } + int irq; + + if (!pending) { + spurious_interrupt(); + return; } - pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); -out: - return; + pending >>= CAUSEB_IP; + while (pending) { + irq = fls(pending) - 1; + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + pending &= ~BIT(irq); + } } static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) @@ -354,11 +355,6 @@ static const struct irq_domain_ops irq_domain_ops = { .map = icu_map, }; -static struct irqaction cascade = { - .handler = no_action, - .name = "cascade", -}; - int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; @@ -390,7 +386,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) mips_cpu_irq_init(); for (i = 0; i < MAX_IM; i++) - setup_irq(i + 2, &cascade); + irq_set_chained_handler(i + 2, ltq_hw_irq_handler); if (cpu_has_vint) { pr_info("Setting up vectored interrupts\n");