From patchwork Mon Mar 1 12:58:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 388633 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3325979jap; Mon, 1 Mar 2021 04:59:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJwtbXLquGq/ptqsbE0oXtTBztpqVw38ZpFrjdJW0rYtU7USqiuCI1LI+j9DG5W1bq/m0ik0 X-Received: by 2002:aa7:c609:: with SMTP id h9mr16622814edq.256.1614603562672; Mon, 01 Mar 2021 04:59:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614603562; cv=none; d=google.com; s=arc-20160816; b=Sr7z6qqyYgA6t8lxcvNRcHn+83f8xB3WURvb9JzVlm47Lu/jitpMQZwx386aEmOSF5 0hJmHNtJ2Kvi/+XJtgOIN7fGdSNem2Ma4Kks40Ny6zFQqRgXcPzkipv72DBU7vWJmkp6 2lAhoCAdnqigrnFA5YfYpNmS2hTt7WTJDo6VkMfp9vGfX5delmhYUBV9oqvFny0K9LPN nlys9gJ1GvCGSRz052B9bwVk3OCEDLAlgIud9HH/VkMjaowUwAhxAjvd5kPEt39H3U/M 3l5az09rQZDXmb/bpsBnvhgrb5LDtM9tTYgQYKoAtndtZAiV5gQlF5xzDUHXeEXxi1lM AZxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=9lmQQarDiOeQNGHSIKw8ruGZvi5J3DnxZbTYAOHgN44=; b=bdTppSzFM28YsqANvLcOOBzDVuH+m0UxtlPy6kOEMh4rjZrGb3Y7OE7LQfysp9P7DH fSBQUTk8BGPKfaJbn+EBkgKx61yUvyK00ah1G1kKSZzOVUz24qzZzxDGMksIel4b/TNS uVn2eZVv3hRct7B7KHaoU85cY6prnUmGueYZYhcOa8+DUr54JJSW+IK7J7inpCTFT9VQ V2zyfQ5qJPoUyr7Cr5OG0m/oEZO39LtQJy/3NDh7siCNLTVYARB8fhjDPS4VqqS5SVaf oC1EnMoxmJPZQLN6YjL4ecPXoD4tEVuPFwZIDs22aabAulkJv+ETeYaJIvXJuWKguF+w z+MQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i24si7931ejf.53.2021.03.01.04.59.22; Mon, 01 Mar 2021 04:59:22 -0800 (PST) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235230AbhCAM7L (ORCPT + 13 others); Mon, 1 Mar 2021 07:59:11 -0500 Received: from foss.arm.com ([217.140.110.172]:57486 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235117AbhCAM7G (ORCPT ); Mon, 1 Mar 2021 07:59:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7911B1FB; Mon, 1 Mar 2021 04:58:20 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A847C3F70D; Mon, 1 Mar 2021 04:58:19 -0800 (PST) From: Suzuki K Poulose To: stable@vger.kernel.org Cc: suzuki.poulose@arm.com, gregkh@linuxfoundation.org, will@kernel.org, catalin.marinas@arm.com Subject: [PATCH v2] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 Date: Mon, 1 Mar 2021 12:58:15 +0000 Message-Id: <20210301125815.3047065-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210301125459.3046861-1-suzuki.poulose@arm.com> References: <20210301125459.3046861-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However we apply the work around for r0p0 - r1p0. Unfortunately this won't be fixed for the future revisions for the CPU. Thus extend the work around for all versions of A55, to cover for r2p0 and any future revisions. Cc: stable@vger.kernel.org # v5.4- Cc: Catalin Marinas Cc: Will Deacon Cc: James Morse Cc: Kunihiko Hayashi Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com [will: Update Kconfig help text] Signed-off-by: Will Deacon Signed-off-by: Suzuki K Poulose --- Changes in v2: - Match the Kconfig text to the original commit "versions" => "revisions" arch/arm64/Kconfig | 2 +- arch/arm64/kernel/cpufeature.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.24.1 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a0bc9bbb92f3..9c8ea5939865 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -489,7 +489,7 @@ config ARM64_ERRATUM_1024718 help This option adds a workaround for ARM Cortex-A55 Erratum 1024718. - Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect + Affected Cortex-A55 cores (all revisions) could cause incorrect update of the hardware dirty bit when the DBM/AP bits are updated without a break-before-make. The workaround is to disable the usage of hardware DBM locally on the affected cores. CPUs not affected by diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f2ec84540414..79caab15ccbf 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1092,7 +1092,7 @@ static bool cpu_has_broken_dbm(void) /* List of CPUs which have broken DBM support. */ static const struct midr_range cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_1024718 - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), #endif {}, };