From patchwork Mon Mar 1 16:25:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388643 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3485261jap; Mon, 1 Mar 2021 08:20:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJxRtktLfD3B2LnizbwoQacz4vObZH8AaApMQ4UYmRBeiIz531VfuM2RUlRi5nxFye6kCC2L X-Received: by 2002:a17:906:f896:: with SMTP id lg22mr16220193ejb.124.1614615603717; Mon, 01 Mar 2021 08:20:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614615603; cv=none; d=google.com; s=arc-20160816; b=ijMMjCQcaaR+NtthAyhjJRo8K3+CKAon0j7CfB7v/yx/erIWNGKCKhsvRRJM8ifcf3 9i7AUWVVMGbb7Q+NsH5+LMg4RB6/L2ez81ITxoBS4BFkH3Q9eC+AQ144YSoXfEcgfG8R sh/91ob7HZq8maU+OZPU+f7Du/i2fn8OSOY/ovY2Z6K4NJWOKxre42MjvJooqb4UajIB kxaqBgEdXLC0iI12tlmLaGFiX8iyRqUIxn0pBkCXMGXAk4ZQ3lfG5V6/3L4r+/PptYy5 VR4qLW4h9zRoC0zdmCMquFxBkW7Nh/y78y4vkZwq1qtBbD9IZ4JlV+z+gF8H48E8BEvE yeUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=vaQb7S7VE33lCI9REO8er+62IGQEtBq+HCe1GdHTW2Q=; b=pU+HyG7UPixpjmZwKUAUmsJ3gqIFfINx744MtAgzGthAFNJSuywVNApRERncIB1kUL tGk+SZETG6vuzyBabiVIz8bANu8YLiktc0wPBLLKA2F3REude+Ev+dzvWP/tgf9yneye CtjRJ1R+osi7c+fJnrodmyBA6Wlev3a0kpEFPhqy1Lz1FT+M8VObB9z/JACblvMeLw6m 4AgIkILdoR0hrgISkDBmZg6Q1LFUDrVLRFWtoHuZOp+QTQugo9OeyU6d0ymDtvDqACyX WlA0maibtsrsY2i2T7YqzqlFKk3DmIw+lHs9wMFRiQLwUlzCYvNtUtnEsnDT9RtAuovy zsRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCiWAkcu; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b24si3522385edr.415.2021.03.01.08.20.03; Mon, 01 Mar 2021 08:20:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCiWAkcu; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237703AbhCAQSo (ORCPT + 16 others); Mon, 1 Mar 2021 11:18:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237620AbhCAQRq (ORCPT ); Mon, 1 Mar 2021 11:17:46 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FC7CC061756 for ; Mon, 1 Mar 2021 08:16:59 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id n4so16786582wrx.1 for ; Mon, 01 Mar 2021 08:16:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=vaQb7S7VE33lCI9REO8er+62IGQEtBq+HCe1GdHTW2Q=; b=iCiWAkcuYHDNc6+4whGvEdBgSekAIeuNVCFXT5tFks48JfgS8ew1fyMNss/HjoVnkS iTXiT4Wqg08i/b3fNKqMUiOSlC0jm/SigjF9btXJjxryv83u5hyI7/OfZrbuDLqHBmo4 5iUUHKlYW1EzYiJkLMRMeQis1jWiYVu+D0F8DOKSCwlwA2/yDX4SWF/osyic6w/hSXSC luJ/8takMKvrlDeoli9iNK9V/n3emYWEzbH9az0GNRy5XrG8GqBT2l8egl1S18NoPJxV RjHWMEoDmm1Jo604XR2pOdcnYHn7p14vJMlCgm+xzuecb2A6f/szXYbRQkCwh3w8ei+u VN3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vaQb7S7VE33lCI9REO8er+62IGQEtBq+HCe1GdHTW2Q=; b=qKpjWvBHOavMuAUSEVfL30iYWgS1HOdzePom/Mq4jmSaibOhEmqYs3cubcqm/ltleW WgIdF1CrwJraRxtMTEVLDiWJIxxnRlxsibi85ab2TD4QcVhdFiKq8pb5ESBQOPbAncIj eZf48pim+ypPqEVuAwxTeerFwElt1wGtjGqGP/bcyeNuCdcYnqfrvR08tR2ZKi+wC3lV b244B+pfl3pvhPLJ9kETWia9asVEAzLwr8DRX9IY8mXi+R3s+Wp0wto38MXdbHKAeyh5 og+rhWOEiNBwi0JYzGGlscMSDx2lUaqQZg4WNY8eo52R2sb+iLoY1jj/c93SpfBwOhIN 6glw== X-Gm-Message-State: AOAM531c1gcdKd5L584TLDg7978eYC1jHN4JOCYokjNloZ79PYnG5ElE GAIvuKT9L0N1mrTFjW/eFBUqew== X-Received: by 2002:a5d:5050:: with SMTP id h16mr17299474wrt.186.1614615418028; Mon, 01 Mar 2021 08:16:58 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:5a20:c00c:6ec3:cc84]) by smtp.gmail.com with ESMTPSA id w6sm3919789wrl.49.2021.03.01.08.16.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Mar 2021 08:16:57 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH 1/6] mhi: pci_generic: Parametrable element count for events Date: Mon, 1 Mar 2021 17:25:06 +0100 Message-Id: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all hardwares need to use the same number of event ring elements. This change makes this parametrable. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8187fcf..c58bf96 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = false, \ } -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ { \ - .num_elements = 64, \ + .num_elements = el_count, \ .irq_moderation_ms = 0, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ - .num_elements = 128, \ + .num_elements = el_count, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ - .num_elements = 2048, \ + .num_elements = el_count, \ .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { static struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ - MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ - MHI_EVENT_CONFIG_DATA(1), + MHI_EVENT_CONFIG_DATA(1, 128), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) }; static struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Mon Mar 1 16:25:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388641 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3484234jap; Mon, 1 Mar 2021 08:18:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJw6Cv4lUBm0gAcdDSQjCSEZHc0p2X3YqO4SI/NkAthqCozal3wgUZxJYHD6BfODXs1r8OZt X-Received: by 2002:a05:6402:1118:: with SMTP id u24mr17325105edv.386.1614615523220; Mon, 01 Mar 2021 08:18:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614615523; cv=none; d=google.com; s=arc-20160816; b=ePlEUc/7AhcPdq4QAjtKuYq5pXxQgZI9dKSBpm6igF7LKJ/wcmIleuUZY43sDMlKFS 3iZnqk90jhCpeB5q/JJOLl6q0p0e1WJhYA7eM6p1KyyqA/OptGfNKWoKCvvHY6J+45we 5y1r1jaI1m8N6FRd64033pdCUdTCkmGXh1isHUfWg0UAf2HHQucOIuvnm9zxeIrErbm+ BuJ1IBemXQh3aADIpQ5KjTMXMIZOraK27Cr5P0xM0cdmsqo8keRzZ/LjYrcFelpA0pF9 +Z6nRybSXMB4yyYUXkgnyL4Kw3C+tGX04lvxqChgwq8T2q3Tj2DCIce8HYlgJup+YZBm /FCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=KS1kq5BuDgV8Wc46EkUvtnfUv9ANjYiniYKfO7WViLw=; b=tF0EbYDMQg782oJPbo47+1Mv+lLFBffAFmBr/0Zl01ns3nHYYNbHdw1fKyzXfV15Rb +F5f51bKUhIibrLjGS/nFYsEOFyfi72jciiLxTSun9+HW0nlLBjfRA+PoJC0PoLZ2WW/ fq80N5k5/FcDUklV2CGetGMeQbh6ngA0q8cL5IBVIhSAuOWROHF1jVh6ZXDg+CkxUU5Q xRIuiv0LnbcsymE6r+Pni8iu1J59yaTGe7hWFgZLxMyNY6J52DTIq2Dr0bGea+utgJSK iWte+7/gI2bV7NWg4sX8VcSckAydCFWSww7o+L3pLFtWAaJhXNtmlblqhSEnD5yF/D/+ qUtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dkoq2PHU; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The modem is mainly based on MBIM protocol for both the data and control path. The drivers for these channels (mhi-net-mbim and mhi_uci) are not yet part of the kernel but will be integrated by different series. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c58bf96..00a0410 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ .num_elements = el_count, \ @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 8000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); From patchwork Mon Mar 1 16:25:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388642 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3485249jap; Mon, 1 Mar 2021 08:20:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJyoIFW8MOuLl9Wtkw5XCUDLkS79FbMeiV1MpSrbUSTH/Y+14Ppfxa3gaK2MHfCWnHkoEmbo X-Received: by 2002:a17:906:128e:: with SMTP id k14mr16371783ejb.427.1614615602394; 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Also add the FIREHOSE channels used by the flash-programmer firmware loaded in EDL mode. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 00a0410..87bab93 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -212,6 +212,14 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { + .name = "qcom-sdx24", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_qcom_v1_mhiv_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), @@ -254,6 +262,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ From patchwork Mon Mar 1 16:25:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388639 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3484045jap; Mon, 1 Mar 2021 08:18:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJydaLchmTbHb3ytggb4CuaSeHZRCstxOjtcS+u2lo0cGr0vJ7MR7neo4zKyfW16fcKh+Add X-Received: by 2002:a17:906:8308:: with SMTP id j8mr11835ejx.339.1614615508902; Mon, 01 Mar 2021 08:18:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614615508; cv=none; d=google.com; s=arc-20160816; b=LvQfqZaoVCqy1tNqHBWLgV0xnbJcZsWq0qTp+daIE3PUQISHlBNM8uPP3Q6jnvubmy Rn6zd3upqb+ESTXN+s49+a4uEiYfDHXsNqPcDPPvKzetnPaq0mYbvWmCHMJyFU/MXHZr b0OiKKBySb85qF8NF5rs+Yxlfk/xDBshHSVZ11RLcj4+tEkDgCwuAJoA1CT850nSxR2N /hWEaUwtdZ2tzMKDwL34mc2P+0zRIsPFopA1Kj0DRroinX8XFPk1yUUIWX9nHjz+lPST pED7T6s70nj/5Z8fPLmR3EmxMimDoyCEdQvCDbxPB+c2+PqoytCB5jCzEAdutK6kDa4U Z1jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=eo+X6BiOa6FPRqtHpKr5U0LHaHSn2ylI7MnexnfxeYU=; b=i+KmkDJheF7VzfCiWJcXZsUbZBmfGjWD8qKSD6/pYltWzsHo1MHqyglbTtBGnJbM2V BpAXwmmIRJWAo1dzdaSlg8fvNm5XaPbnEqwnCPtrX7bo3eSu4NmzZpSMoIFHkMqyS1DN Q7Cu9QRtU9PZUy3c3oMNv+CwwzsfUXDur6OgXaX4Hl3XTW3IXmODXgpUmJgZP81lcEP0 bRcx0SojpiBAMuNyrK5od+4lO/5YICCIasVGmbmD/YekRqp43jwOyXM5DyLzn2lAMTRQ yM9iInY4BuI+JrywUHmmdcMAx0HU+8wFo6MuI5CD0S+gHqwHnnM55gOwXZysmuV7WAy3 DwAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QXFMtjxp; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z21si12194404edx.208.2021.03.01.08.18.28; Mon, 01 Mar 2021 08:18:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QXFMtjxp; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237662AbhCAQS1 (ORCPT + 16 others); Mon, 1 Mar 2021 11:18:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237706AbhCAQRq (ORCPT ); Mon, 1 Mar 2021 11:17:46 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A21BC06178B for ; Mon, 1 Mar 2021 08:17:03 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id n4so16786778wrx.1 for ; Mon, 01 Mar 2021 08:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eo+X6BiOa6FPRqtHpKr5U0LHaHSn2ylI7MnexnfxeYU=; b=QXFMtjxpTC+3z4uslhvfLVtxhpZupCRhjTOM1hp4LOe0caEIlRh/q3Dc5f/en20tae oUrJRWpKvE8VKREm71eXa+A8Yx3Jv+lT3A5Trcu1MSdX3i2Sawyh4e2IVamOYmX8Braf 1RlY/YcHZeObbCvkpGrJlIv//r7jG8zfqYIZPoFl9QOBijUR2fDbBFgPcGdBMit80JwZ Bgm8gMTsI9r6uWOwLRNy+o6yEwqj/emZZ/nYURO+4nWg/BHdQMuZEPjlW8xUNBT/Rz3Z Bng/QMySk+w8e9krsE8ZxT6QbtTFcukgakHFzzSq8+yH/ikUQzMaawZih/CVXPLCLa8F GCQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eo+X6BiOa6FPRqtHpKr5U0LHaHSn2ylI7MnexnfxeYU=; b=twpbkCA92UqwwG1EozHjOmDs/bdILTwawInM1YO3vihVj1u0BwYGUpvddv2+uQgTVl emZf8PWr5aeBX2eWAAdeRKNTPy2Ti30VZX0KWvJDSuGCYlvyTT4dSdW08LN2GL/34KwE 9x+T3FLgr+8ITeBknBNtMfAHApJh2kAv4h/2F4W8jm4DGVx2sJOU49Ru/0qWAr8/EOOV 9GCDuDiawAauKRf8wVsr/AxhleNctC1SOKuwAqCaB6U3S4JAOJXVgFgw9t5k1pQjK9th M527If8NsYQ4nWkakCmKkjya6uG0tNzCkAe7pwAgZG6PSvNm+q+AYXUehBK5yL54YjXF Mh8g== X-Gm-Message-State: AOAM532CrJIIcK6DbFlHlffm4ZEcMRSbLuR9mRWK9sqOOc6Sr1mUSTqn M8c/bee9lW3y/DYvKZURiHgHeg== X-Received: by 2002:a05:6000:2cf:: with SMTP id o15mr17283408wry.184.1614615422153; Mon, 01 Mar 2021 08:17:02 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:5a20:c00c:6ec3:cc84]) by smtp.gmail.com with ESMTPSA id w6sm3919789wrl.49.2021.03.01.08.17.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Mar 2021 08:17:01 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH 4/6] mhi: pci_generic: No-Op for device_wake operations Date: Mon, 1 Mar 2021 17:25:09 +0100 Message-Id: <1614615911-18794-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> References: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The wake_db register presence is highly speculative and can fuze MHI devices. Indeed, currently the wake_db register address is defined at entry 127 of the 'Channel doorbell array', thus writing to this address is equivalent to ringing the doorbell for channel 127, causing trouble with some device that get an unexpected channel 127 doorbell interrupt. This change fixes that issue by setting wake get/put as no-op for pci_generic devices. The wake device sideband mechanism seems really specific to each device, and is AFAIK no defined by the MHI spec. It also removes zeroing initialization of wake_db register during MMIO initialization, the register being set via wake_get/put accessors few cycles later during M0 transition. Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/init.c | 2 -- drivers/bus/mhi/pci_generic.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 2159dbc..32eb90f 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -510,8 +510,6 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) /* Setup wake db */ mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->wake_set = false; /* Setup channel db address for each channel in tre_ring */ diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 87bab93..8423293 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -312,6 +312,21 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, } } +static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) +{ + /* no-op */ +} + +static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) +{ + /* no-op */ +} + +static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) +{ + /* no-op */ +} + static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) { struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); @@ -515,6 +530,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) From patchwork Mon Mar 1 16:25:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388640 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3484203jap; Mon, 1 Mar 2021 08:18:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJyTdlK650ZyCGZyEhVsFXMLVG7yvfiPwX3RhM+eq4VFEb88wsTa/hmr5WhfUv8gmaSG4cUb X-Received: by 2002:a17:906:7015:: with SMTP id n21mr7673844ejj.391.1614615521209; Mon, 01 Mar 2021 08:18:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614615521; cv=none; d=google.com; s=arc-20160816; b=foGCKeUOBzh5MBNqiTW/TQR9aNWPoPPQWDMPXZoOlIIuJYDCamItPh+XMy0AKp5zHM VpsoUytTREUml2z1ib2ZGJUmdAtPN6qQYcn/EhBFbawnF3KiJoGG6WampbSGy72KGS8w xEJ4f4L9WGE+W3stbsuXVQglVTve8Dfl69Gy5Ny3iy9NziEz+4l9PkU097D6S3svzbul c5NipI3Tjmy6LcbVUGrjaoPKHH4NnDk8NJZZjfbeY3abrzW8fEkLGtDMcGv2YHTQnHS/ nCa5IW9XYT7VG5t33AJvLJbyJWkeQcH2NsrGSPQpe8ihzzLmxkhBrJvTGyOMuBYXilmO EMiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=jsyqTAbWOYH12GXgEyrYcHvBDKRbWqhbbW9V0ah26q8=; b=c0VrtbFA6N+YvrQwCvsCXvBskkfIuriDt8x7OfeT7MCbtWcfHNmX2buoOUtfTimjQL LGdxkgv9nV0n+WmeeKXQclYeRc0shhnmgDMeLuknVHqFKbjjXP70ALOW4j8AXZErO+cq 5VpN1h/FEi2cvbyn0Z8OwHpPcPxaZtFdTuBV+G5lJbQnV4YZdoEm0ISAvSazPavMiGDJ YCTOqvZvrOns5SmoTNeFEqyRHbDJJ9148xCACXlpOpGajJ09gbfoVsx02UIoV/PKSI79 ua4ILwDffMeUluBzRnJ65pgsL18AN+FdlM8HXdxHh1TYXOFu+QCyiyS7vnQiYddj5CAm b8pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LYrj+8dV; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z21si12194404edx.208.2021.03.01.08.18.41; Mon, 01 Mar 2021 08:18:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LYrj+8dV; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237701AbhCAQS2 (ORCPT + 16 others); Mon, 1 Mar 2021 11:18:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237707AbhCAQRq (ORCPT ); Mon, 1 Mar 2021 11:17:46 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 452FBC06178C for ; Mon, 1 Mar 2021 08:17:04 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id h98so16741985wrh.11 for ; Mon, 01 Mar 2021 08:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jsyqTAbWOYH12GXgEyrYcHvBDKRbWqhbbW9V0ah26q8=; b=LYrj+8dViEblyipd9eQYcPBVxLZ0F2kn/VARIc0tBvRCYrgQ7sLbNNuAY8wq3exZtN sTdCc32UUX3xjY5UyhSM/YhvBo3It2i2XnudGnlRLy5qujddWTDrCYtv5L34gK7HAlRU fhDra+biZzv+0l78csdWYuUHMUn9JwrbPQeBeEz8pVKQnojWqhXBBVjn1IWTr2Kj2Dod QdIfmzb7zOVBXTpzcJcxIGIK89QPuXyLCIuboGTEeSTv8sYDOGNRSPzzgo7RWFXCvYCZ gmJuLUAfI32TLHepGnMfqSTmstE/rIEWYVjLpFYSVIVRfVlwa3i7j2mso9ptaRJ0RfsA fImw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jsyqTAbWOYH12GXgEyrYcHvBDKRbWqhbbW9V0ah26q8=; b=jsAK/NC1O31ZYDGd3E7UaC53y9Whmx1vvq5PSKSLq+1bD6dxAfVDd0pd8BDs+6wDTq J69jYLQIZi8hqrfOrm1EzYuuInjWz1uKY0y2LrC9At6OMfm8lwLuko1U/erNNVFse1K4 wUfX1TXCqCPPTnp0JoE4iiRiLGbdMYJtne6vrC06U/eGwXEcNnyYmuFoCFvgKv/McBH+ YnntW6GDq7UkYWrBbuLvaeA8LOXX0P1HxX7BMwPJQ1aQCmnKN0zDccJeJU2I/yRWUmqZ Xyriq+sqaF3X+rTFrZvLamrSqhJ6nvwTgf//2S4e4xTqtstB12eiqVLg68ddQTt+zed2 N1/Q== X-Gm-Message-State: AOAM5326sj2boUf+5uBMuOadAiwbSkfx9LWm1zSH7f0uYi2AOTrQg6ms 3rby/A6ThdfmIUkCyJrE0JORag== X-Received: by 2002:a5d:61c9:: with SMTP id q9mr8896966wrv.219.1614615423014; Mon, 01 Mar 2021 08:17:03 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:5a20:c00c:6ec3:cc84]) by smtp.gmail.com with ESMTPSA id w6sm3919789wrl.49.2021.03.01.08.17.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Mar 2021 08:17:02 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH 5/6] mhi: pci_generic: Use generic PCI power management Date: Mon, 1 Mar 2021 17:25:10 +0100 Message-Id: <1614615911-18794-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> References: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PCI core can take care of proper PCI suspend/resume operations, but this is discarded when the driver saves PCI state by its own. This currently prevents the PCI core to enable PME (for modem initiated D3 exit) which is requested for proper runtime pm support. This change deletes explicit PCI state-saving and state-set from suspend callback, letting the PCI doing the appropriate work. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8423293..2a66f80 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -544,9 +544,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, mhi_pdev); - /* Have stored pci confspace at hand for restore in sudden PCI error */ + /* Have stored pci confspace at hand for restore in sudden PCI error. + * cache the state locally and discard the PCI core one. + */ pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_load_saved_state(pdev, NULL); pci_enable_pcie_error_reporting(pdev); @@ -717,10 +720,8 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) /* Transition to M3 state */ mhi_pm_suspend(mhi_cntrl); - pci_save_state(pdev); pci_disable_device(pdev); pci_wake_from_d3(pdev, true); - pci_set_power_state(pdev, PCI_D3hot); return 0; } @@ -732,14 +733,13 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - pci_set_master(pdev); - err = pci_enable_device(pdev); if (err) goto err_recovery; + pci_set_master(pdev); + pci_wake_from_d3(pdev, false); + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { From patchwork Mon Mar 1 16:25:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 388645 Delivered-To: patch@linaro.org Received: by 2002:a02:290e:0:0:0:0:0 with SMTP id p14csp3485417jap; Mon, 1 Mar 2021 08:20:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJyqkJZ/11+y2p8F8osB0I/btUEpBKEjp8HSecffopZEQhzunOCcB2LFyHYCEOyZ+yL9Y6mK X-Received: by 2002:a17:906:3916:: with SMTP id f22mr16868073eje.328.1614615614467; Mon, 01 Mar 2021 08:20:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614615614; cv=none; d=google.com; s=arc-20160816; b=RRbu3A2g7ujc9Vq/MenqJnJdHrpY+ULza12LVf+tMpPwKJVQl8LHSlCo2pEP+im/e5 ofHhmloPR63+6h6ZT9TmaHTAL4Hd9vaD7TlpGwGcCEWu+FGiKct+kFbst4qvAWLyqWfU 5EJdl9LFOSOw8LqlEmGOpl4CU83hvdgnHhM28kaeANG8vz5LlgZcV2qOLHcbrWhxeWm0 /dh/oaJQ60zxaH0H61/aajiwX9gHH6fDrgWSVgMXRreZBKDBZwJj9EIVq3wZefLNAd6h jDLMy3piiZRr797OrwQOdPBtiT535cnPFsYZNE/KF0Pgzpl8UpN7eY5iv0hrasXROB+g NA6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=LaV6X0F5DQzXiJGVsgwJy4CH3I5tNDQd/ra57eKQDJU=; b=bFhiPRdvS7Ge0bBaNPIOP/J7WzRVdIb/w6rMwrDmDxr4ZIGOvtDHCDjOp56liWIxUr 2j+alnYh3ENiuLlvPX1DtRHN5QIycQhzWzXPn5nU2Kubm8BbroG4NFLQ/ueE1vUjIBVi hsoBblFIb/Az+fiP45uv0VHA+806kgyTku71SvXKEw4DSXtzNElwIvQzBPxE4sCKsT7z iGSo0uTr5xzx4yG4tkED1znhgFqcz0jEIxmG7OKOywRMiEfEY4LZHbWqZzcB4D70vcYC Srw/7AU6qdVNEiK06+7z1e9hqspI7i06uVjxdjcXAqk2MW4kiEHZrZtuOI5oRAgNN5sW apuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXdxDkGT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b24si3522385edr.415.2021.03.01.08.20.14; Mon, 01 Mar 2021 08:20:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXdxDkGT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237790AbhCAQTQ (ORCPT + 16 others); Mon, 1 Mar 2021 11:19:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237620AbhCAQSu (ORCPT ); Mon, 1 Mar 2021 11:18:50 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F4BC061793 for ; Mon, 1 Mar 2021 08:17:05 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id e10so16525122wro.12 for ; Mon, 01 Mar 2021 08:17:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LaV6X0F5DQzXiJGVsgwJy4CH3I5tNDQd/ra57eKQDJU=; b=OXdxDkGTv8Vvr5bfhn/6QtXYVKbfPIfi8236twIKlc6MkBQhd73Y/Bw2M6o14XONzY sjtvx8VQGHY4VtEh6UD3lLFzAiy/XIecQnSUUhf1w7BHvLxEiWGtDH3uf5K0RIBSwQmu wmniB2xuDc0ufS4ZSgDfq9IdoMbqzcc/Im4D8ojDTk2BxgtX7NwKi833/rnTQMqn7NAD QfND/jlxmd3E5T+4kmeRp0XfqmxL4ttecTvDJj/6NASnffj47lk6yq6IdmXSfB1xLT7s 37a1zz6HlfGsR2hXeo8yO2v0RVEEGN+g+5qc5F/WyQY9HLx/MgC/gF0zunnBftUEo/kk K1wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LaV6X0F5DQzXiJGVsgwJy4CH3I5tNDQd/ra57eKQDJU=; b=neiANzNBN+EZHZ9hNjqB9MEIGc9gpRvelw2hPKIXhjjvSQQHTn83JzWBoFwyTshyok 2JwJck9ikgwczk+NGsjfBg76oOCeVI1Oxa2b71tASs5I6vG/3hndIvhRgPWEeoH0F18N YxGIcoKh0d0x2UAxsG623z/6bTqyvyq6VnV6d0HmMwX5i7Vnp1ulocjl0qd5aaGgMWT6 xPO1qStzOCaSJ0whiz+iIfVEdngSuIkBFVpwgyFpiyPZiyfEg1Q2XyzG0hVtdpo1hCwF nv0LyOg2yUmd2WOgiarVh+kwm5wJ9lPFjUWUbteZGcTyqdw18aG/jVqp1Ph06L5ZpcEC ih5w== X-Gm-Message-State: AOAM531pJ0xmrNtNfAwKuA2cWq3zQP8U/DZrNfsz9+/19zseMZuru4Bm JVRsdhl0aqC6sPItII/8Y4D/mPOCwZTh6buI X-Received: by 2002:adf:a4d1:: with SMTP id h17mr17715091wrb.57.1614615424131; Mon, 01 Mar 2021 08:17:04 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:5a20:c00c:6ec3:cc84]) by smtp.gmail.com with ESMTPSA id w6sm3919789wrl.49.2021.03.01.08.17.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Mar 2021 08:17:03 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH 6/6] mhi: pci_generic: Add support for runtime PM Date: Mon, 1 Mar 2021 17:25:11 +0100 Message-Id: <1614615911-18794-6-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> References: <1614615911-18794-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When the device is idle it is possible to move it into the lowest MHI PM state (M3). In that mode, all MHI operations are suspended and the PCI device can be safely put into PCI D3 state. The device is then resumed from D3/M3 either because of host initiated MHI operation (e.g. buffer TX) or because the device (modem) has triggered wake-up via PME feature (e.g. on incoming data). Same procedures can be used for system wide or runtime suspend/resume. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 65 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 58 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 2a66f80..2bc834d 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -274,6 +275,7 @@ MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); enum mhi_pci_device_status { MHI_PCI_DEV_STARTED, + MHI_PCI_DEV_SUSPENDED, }; struct mhi_pci_device { @@ -306,6 +308,10 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, case MHI_CB_FATAL_ERROR: case MHI_CB_SYS_ERROR: dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); + pm_runtime_forbid(&pdev->dev); + break; + case MHI_CB_EE_MISSION_MODE: + pm_runtime_allow(&pdev->dev); break; default: break; @@ -427,13 +433,19 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ - return 0; + /* The runtime_get() MHI callback means: + * Do whatever is requested to leave M3. + */ + return pm_runtime_get(mhi_cntrl->cntrl_dev); } static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ + /* The runtime_put() MHI callback means: + * Device can be moved in M3 state. + */ + pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); + pm_runtime_put(mhi_cntrl->cntrl_dev); } static void mhi_pci_recovery_work(struct work_struct *work) @@ -494,6 +506,10 @@ static void health_check(struct timer_list *t) return; } + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return; + /* reschedule in two seconds */ mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } @@ -575,6 +591,14 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) /* start health check */ mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + /* Only allow runtime-suspend if PME capable (for wakeup) */ + if (pci_pme_capable(pdev, PCI_D3hot)) { + pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + } + return 0; err_unprepare: @@ -598,6 +622,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) mhi_unprepare_after_power_down(mhi_cntrl); } + /* balancing probe put_noidle */ + if (pci_pme_capable(pdev, PCI_D3hot)) + pm_runtime_get_noresume(&pdev->dev); + mhi_unregister_controller(mhi_cntrl); } @@ -708,31 +736,45 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; -static int __maybe_unused mhi_pci_suspend(struct device *dev) +static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + goto pci_suspend; /* Nothing to do at MHI level */ + /* Transition to M3 state */ - mhi_pm_suspend(mhi_cntrl); + err = mhi_pm_suspend(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to suspend device: %d;\n", err); + clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); + return -EBUSY; + } +pci_suspend: pci_disable_device(pdev); pci_wake_from_d3(pdev, true); return 0; } -static int __maybe_unused mhi_pci_resume(struct device *dev) +static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; + clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); + err = pci_enable_device(pdev); if (err) goto err_recovery; @@ -740,6 +782,13 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) pci_set_master(pdev); pci_wake_from_d3(pdev, false); + /* It can be a remote wakeup (no mhi runtime_get), update access time */ + pm_runtime_mark_last_busy(dev); + + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + return 0; /* Nothing to do at MHI level */ + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { @@ -760,7 +809,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) } static const struct dev_pm_ops mhi_pci_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) + SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static struct pci_driver mhi_pci_driver = {