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[209.132.180.67]) by mx.google.com with ESMTP id t11si6046612pfl.55.2018.04.13.20.19.39; Fri, 13 Apr 2018 20:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hi49yUqJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751880AbeDNDTf (ORCPT + 6 others); Fri, 13 Apr 2018 23:19:35 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:41976 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751839AbeDNDTd (ORCPT ); Fri, 13 Apr 2018 23:19:33 -0400 Received: by mail-pl0-f66.google.com with SMTP id bj1-v6so7089962plb.8 for ; Fri, 13 Apr 2018 20:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kb8g8oQU3eBv/wGzySFKr10IQCXKbHVD9kM8Z6XT4Xg=; b=hi49yUqJjc7AtTUNEhk57noe9/DW/tu+KPt7KndnNcpych9ll6LkJstFGhBW3+yUao lIlHU+/N82racuiYRxwUzBwEKq9ceewzaxxuh1eY6G9wY5oBjJ5K8ZWMmrGKYLjGKA7l 0X73Pfv8fibsWzAmvFgwfExTagNqWM2xDu7VE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kb8g8oQU3eBv/wGzySFKr10IQCXKbHVD9kM8Z6XT4Xg=; b=MlT4HofATjjD5jmUvZrXt+Do9jGWW4qz6WDZm1X57Vhc48Ku1lYhYu0BBQF84kmbjq k5nDtknQlUBQGdcB9nnAQRF4EkQO7ET823yBScwuJMFi7zyTaicidrvfF4JGS2a+07cz KxhpuDsfPAOFUiS2Hc8kfcuH7sXaGiaRBuZJJ9Y7YgzVxmYvJwFq5FSMSG3SxIfk//SU 4BFQIugVEGr9eR1cAWXrfzBdqE+2vRbDg4EI6t9DWgjXjVR5HONYIZB9fSrn5KddhsCP i9pum5ZGPu7qpYdXBY8ShEzlmcYoQ0pDXHJHbYKRGFqlRaxHBMLJEazkFQ8i1Gn/+7ya r9IQ== X-Gm-Message-State: ALQs6tBidt8JvmGrDqtILqZUWZMuRr4Z2iA2T16dKJ35d+/RZrDmCGvK VVXmfhCR+cY9Y2IXgk/5qdh9 X-Received: by 2002:a17:902:444:: with SMTP id 62-v6mr7449413ple.127.1523675972597; Fri, 13 Apr 2018 20:19:32 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c8:4566:f594:fb20:952d:2ff8]) by smtp.gmail.com with ESMTPSA id f8sm16134250pgs.84.2018.04.13.20.19.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Apr 2018 20:19:32 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, bjorn.andersson@linaro.org, will.deacon@arm.com Cc: amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, dragonboard@lists.96boards.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/1] dts: qcom: db820c: Add gpio-line-names property Date: Sat, 14 Apr 2018 08:48:11 +0530 Message-Id: <20180414031811.11351-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180414031811.11351-1-manivannan.sadhasivam@linaro.org> References: <20180414031811.11351-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC. There are 4 gpio-controllers present on this board, including the APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO). Lines names are derived from 96Boards CE Specification 1.0, Appendix "Expansion Connector Signal Description". Line names for PMI8994 MPP pins are not added due to the absence of the gpio-controller support. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 240 +++++++++++++++++++++++++++ 1 file changed, 240 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 1c8f1b86472d..1c1deef031c6 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -19,6 +19,34 @@ #include #include +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * P HSEC = Primary High Speed External Connector + * S HSEC = Secondary High Speed External Connector + * J14 = Camera Connector + * TP = Test Points + * + * Line names are taken from the schematic "DragonBoard 820c", + * drawing no: LM25-P2751-1 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + / { aliases { serial0 = &blsp2_uart1; @@ -90,6 +118,218 @@ status = "okay"; }; + pinctrl@1010000 { + gpio-line-names = + "[SPI0_DOUT]", /* GPIO_0, LSEC pin 14 */ + "[SPI0_DIN]", /* GPIO_1, LSEC pin 10 */ + "[SPI0_CS]", /* GPIO_2, LSEC pin 12 */ + "[SPI0_SCLK]", /* GPIO_3, LSEC pin 8 */ + "[UART1_TxD]", /* GPIO_4, LSEC pin 11 */ + "[UART1_RxD]", /* GPIO_5, LSEC pin 13 */ + "[I2C1_SDA]", /* GPIO_6, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_7, LSEC pin 19 */ + "GPIO-H", /* GPIO_8, LSEC pin 30 */ + "TP93", /* GPIO_9 */ + "GPIO-G", /* GPIO_10, LSEC pin 29 */ + "[MDP_VSYNC_S]", /* GPIO_11, P HSEC pin 55 */ + "NC", /* GPIO_12 */ + "[CSI0_MCLK]", /* GPIO_13, P HSEC pin 15 */ + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ + "[CSI1_MCLK]", /* GPIO_15, P HSEC pin 17 */ + "TP99", /* GPIO_16 */ + "[I2C2_SDA]", /* GPIO_17, P HSEC pin 34 */ + "[I2C2_SCL]", /* GPIO_18, P HSEC pin 32 */ + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ + "GPIO-K", /* GPIO_23, LSEC pin 33 */ + "GPIO-D", /* GPIO_24, LSEC pin 26 */ + "GPIO-I", /* GPIO_25, LSEC pin 31 */ + "GPIO-J", /* GPIO_26, LSEC pin 32 */ + "BLSP6_I2C_SDA", /* GPIO_27 */ + "BLSP6_I2C_SCL", /* GPIO_28 */ + "GPIO-B", /* GPIO_29, LSEC pin 24 */ + "GPIO30", /* GPIO_30, S HSEC pin 4 */ + "HDMI_CEC", /* GPIO_31 */ + "HDMI_DDC_CLOCK", /* GPIO_32 */ + "HDMI_DDC_DATA", /* GPIO_33 */ + "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ + "PCIE0_RST_N", /* GPIO_35 */ + "PCIE0_CLKREQ_N", /* GPIO_36 */ + "PCIE0_WAKE", /* GPIO_37 */ + "SD_CARD_DET_N", /* GPIO_38 */ + "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ + "W_DISABLE_N", /* GPIO_40 */ + "[BLSP9_UART_TX]", /* GPIO_41 */ + "[BLSP9_UART_RX]", /* GPIO_42 */ + "[BLSP2_UART_CTS_N]", /* GPIO_43 */ + "[BLSP2_UART_RFR_N]", /* GPIO_44 */ + "[BLSP3_UART_TX]", /* GPIO_45 */ + "[BLSP3_UART_RX]", /* GPIO_46 */ + "[I2C0_SDA]", /* GPIO_47 LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_48 LSEC pin 15 */ + "[UART0_TxD]", /* GPIO_49 LSEC pin 5 */ + "[UART0_RxD]", /* GPIO_50 LSEC pin 7 */ + "[UART0_CTS]", /* GPIO_51 LSEC pin 3 */ + "[UART0_RTS]", /* GPIO_52 LSEC pin 9 */ + "[CODEC_INT1_N]", /* GPIO_53 */ + "[CODEC_INT2_N]", /* GPIO_54 */ + "[BLSP7_I2C_SDA]", /* GPIO_55 */ + "[BLSP7_I2C_SCL]", /* GPIO_56 */ + "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ + "[PCM_CLK]", /* GPIO_58 LSEC pin 18 */ + "[PCM_FS]", /* GPIO_59 LSEC pin 16 */ + "[PCM_DO]", /* GPIO_60 LSEC pin 20 */ + "[PCM_DI]", /* GPIO_61 LSEC pin 22 */ + "GPIO-E", /* GPIO_62, LSEC pin 27 */ + "TP87", /* GPIO_63 */ + "[CODEC_RST_N]", /* GPIO_64 */ + "[PCM1_CLK]", /* GPIO_65 */ + "[PCM1_SYNC]", /* GPIO_66 */ + "[PCM1_DIN]", /* GPIO_67 */ + "[PCM1_DOUT]", /* GPIO_68 */ + "AUDIO_REF_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "NC", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "TP94", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "TP95", /* GPIO_79 */ + "GPIO-A", /* GPIO_80, LSEC pin 23 */ + "TP88", /* GPIO_81 */ + "TP89", /* GPIO_82 */ + "TP90", /* GPIO_83 */ + "TP91", /* GPIO_84 */ + "[SD_DAT0]", /* GPIO_85, HSEC pin 1 */ + "[SD_CMD]", /* GPIO_86, HSEC pin 11 */ + "[SD_DAT3]", /* GPIO_87, HSEC pin 7 */ + "[SD_SCLK]", /* GPIO_88, HSEC pin 9 */ + "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ + "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ + "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ + "NC", /* GPIO_92 */ + "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ + "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ + "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ + "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ + "NC", /* GPIO_97 */ + "CAM1_STANDBY_N", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "NC", /* GPIO_100 */ + "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ + "BOOT_CONFIG1", /* GPIO_102 */ + "USB_HUB_RESET", /* GPIO_103 */ + "CAM1_RST_N", /* GPIO_104 */ + "NC", /* GPIO_105 */ + "NC", /* GPIO_106 */ + "NC", /* GPIO_107 */ + "NC", /* GPIO_108 */ + "NC", /* GPIO_109 */ + "NC", /* GPIO_110 */ + "NC", /* GPIO_111 */ + "NC", /* GPIO_112 */ + "PMI8994_BUA", /* GPIO_113 */ + "PCIE2_RST_N", /* GPIO_114 */ + "PCIE2_CLKREQ_N", /* GPIO_115 */ + "PCIE2_WAKE", /* GPIO_116 */ + "SSC_IRQ_0", /* GPIO_117 */ + "SSC_IRQ_1", /* GPIO_118 */ + "SSC_IRQ_2", /* GPIO_119 */ + "NC", /* GPIO_120 */ + "GPIO121", /* GPIO_121, S HSEC pin 2 */ + "NC", /* GPIO_122 */ + "SSC_IRQ_6", /* GPIO_123 */ + "SSC_IRQ_7", /* GPIO_124 */ + "GPIO-C", /* GPIO_125, LSEC pin 25 */ + "BOOT_CONFIG5", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "BOOT_CONFIG7", /* GPIO_129 */ + "PCIE1_RST_N", /* GPIO_130 */ + "PCIE1_CLKREQ_N", /* GPIO_131 */ + "PCIE1_WAKE", /* GPIO_132 */ + "GPIO-L", /* GPIO_133, LSEC pin 34 */ + "NC", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "BOOT_CONFIG8", /* GPIO_136 */ + "NC", /* GPIO_137 */ + "NC", /* GPIO_138 */ + "GPS_SSBI2", /* GPIO_139 */ + "GPS_SSBI1", /* GPIO_140 */ + "NC", /* GPIO_141 */ + "NC", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "BOOT_CONFIG6", /* GPIO_144 */ + "NC", /* GPIO_145 */ + "NC", /* GPIO_146 */ + "NC", /* GPIO_147 */ + "NC", /* GPIO_148 */ + "NC"; /* GPIO_149 */ + }; + + qcom,spmi@400f000 { + pmic@0 { + gpios@c000 { + gpio-line-names = + "NC", + "KEY_VOLP_N", + "NC", + "BL1_PWM", + "GPIO-F", /* LSEC pin 28 */ + "BL1_EN", + "NC", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "DIVCLK1", + "DIVCLK2", + "DIVCLK3", + "DIVCLK4", + "BT_EN", + "PMIC_SLB", + "PMIC_BUA", + "USB_VBUS_DET"; + }; + + mpps@a000 { + gpio-line-names = + "VDDPX_BIAS", + "WIFI_LED", + "NC", + "BT_LED", + "PM_MPP05", + "PM_MPP06", + "PM_MPP07", + "NC"; + }; + }; + + pmic@2 { + gpios@c000 { + gpio-line-names = + "NC", + "SPKR_AMP_EN1", + "SPKR_AMP_EN2", + "TP61", + "NC", + "USB2_VBUS_DET", + "NC", + "NC", + "NC", + "NC"; + }; + }; + }; + phy@34000 { status = "okay"; };