From patchwork Thu Mar 4 06:08:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 392930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DDFCC43332 for ; Thu, 4 Mar 2021 06:10:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2725864F31 for ; Thu, 4 Mar 2021 06:10:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234585AbhCDGJa (ORCPT ); Thu, 4 Mar 2021 01:09:30 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19314 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234555AbhCDGI6 (ORCPT ); Thu, 4 Mar 2021 01:08:58 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 03 Mar 2021 22:08:17 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 4 Mar 2021 06:08:17 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 4 Mar 2021 06:08:16 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v1 1/5] MAINTAINERS: Add Tegra CPUIDLE driver section Date: Wed, 3 Mar 2021 22:08:08 -0800 Message-ID: <1614838092-30398-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614838097; bh=ooxAqdYwtjF3ejhyniZpEkKraYlFNnY4uuE7CwW4z9E=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=kX4mberFHmtOmOR+if52uacJHyc/kbrmOUuItKBOs5kJ90SPyybPDtX8bwJLJMnrB 05eZqIh9U2vi7jB+SEmgrhiFKHCE/BL6Sxg8xx9whmjcrriWxeRCEhUf9WHvVcOJ7j BPnS2goJStdgN/U1JShKKiMROu8IZI4n22nFQuzVdnqsvkHNWj0nEp9XKH4a94NA5Q WOqkvKVQUaPoFGsliz/Vwt6nCP/hvA0P4yaNCwF1TFVppRgAUHKRbyqu0Cn+CgiQO0 2wTQkMizLwsDMKc2XqV4jWufCPWABmRODmqBoEUrpV2/eKV38h5mYXBZzEhj2EMM3f 36/16dj4fllMA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Tegra CPUIDLE driver section with maintainers and mailing list entries. Signed-off-by: Sowjanya Komatineni --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cac8429..277fcfd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4679,6 +4679,18 @@ S: Supported F: drivers/cpuidle/cpuidle-psci.h F: drivers/cpuidle/cpuidle-psci-domain.c +CPUIDLE DRIVER - TEGRA194 +M: Thierry Reding +M: Jonathan Hunter +M: Krishna Sitaraman +M: Sanjay Chandrashekara +M: Sowjanya Komatineni +L: linux-pm@vger.kernel.org +L: linux-tegra@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml +F: drivers/cpuidle/cpuidle-tegra194.c + CRAMFS FILESYSTEM M: Nicolas Pitre S: Maintained From patchwork Thu Mar 4 06:08:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 393814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7588C43381 for ; Thu, 4 Mar 2021 06:10:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B345864F0B for ; Thu, 4 Mar 2021 06:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234580AbhCDGJ3 (ORCPT ); Thu, 4 Mar 2021 01:09:29 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:2835 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234505AbhCDGI6 (ORCPT ); Thu, 4 Mar 2021 01:08:58 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 03 Mar 2021 22:08:18 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 4 Mar 2021 06:08:17 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 4 Mar 2021 06:08:17 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v1 2/5] firmware: tegra: Add Tegra194 MCE ARI driver Date: Wed, 3 Mar 2021 22:08:09 -0800 Message-ID: <1614838092-30398-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614838098; bh=lI74aTkbe7LHdD3TDHPb188VdRsOXpjv+fKYqb3YOUQ=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=Bz3tqcXReN+BamoYpdXOxQGSHyJBV38ZJo+56JWAdVWBivXubU5KQ7//VNovoo1PT wD12yGyUI0w/It31cMP4kDZj7DdQVCL8apGI4f6kJKcAydIFn3nIdqAVJx2yiODXdg pIDC+Jfh5t1PBDIG34OCGtljvEJOR7OxZEoUnT/16tsRIKnKTLI0AmUo0B1D03SLOi /Tju/oPoW0W0XZKRNc75oLmZFR9RGXJWLU94brRXMHBeB/zHXOtB1H1osa7rqHdod3 qt41Z8vmSkIW04hEmk4yNXw0c0FtaEgr26mTxRxTOrK/QtpQHXgcymzMpHwEEpI3ad Zl+2kFKbsSBWA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra MCE Abstract Request Interface (ARI) driver manages all NVG requests to MCE firmware running in the background. This patch adds Tegra194 MCE interface driver for communicating with MCE firmware on CPU state configurations and state transition requests from the CPU idle driver. Signed-off-by: Sowjanya Komatineni --- drivers/firmware/tegra/Kconfig | 11 +++ drivers/firmware/tegra/Makefile | 4 + drivers/firmware/tegra/mce-tegra194.c | 155 ++++++++++++++++++++++++++++++++++ drivers/firmware/tegra/mce.c | 88 +++++++++++++++++++ include/soc/tegra/mce.h | 32 +++++++ include/soc/tegra/t194_nvg.h | 56 ++++++++++++ 6 files changed, 346 insertions(+) create mode 100644 drivers/firmware/tegra/mce-tegra194.c create mode 100644 drivers/firmware/tegra/mce.c create mode 100644 include/soc/tegra/mce.h create mode 100644 include/soc/tegra/t194_nvg.h diff --git a/drivers/firmware/tegra/Kconfig b/drivers/firmware/tegra/Kconfig index 1c8ba1f..a14ef1c 100644 --- a/drivers/firmware/tegra/Kconfig +++ b/drivers/firmware/tegra/Kconfig @@ -23,4 +23,15 @@ config TEGRA_BPMP This driver manages the IPC interface between host CPU and the firmware running on BPMP. +config TEGRA_MCE + bool "Tegra MCE driver" + depends on ARCH_TEGRA_194_SOC + help + MCE (Micro Codec Engine) firmware is in charge of CPUs power state + transitions. + + Tegra MCE driver is an interface driver to communicate with MCE + firmware for all the CPU power state change requests from CPU idle + driver. + endmenu diff --git a/drivers/firmware/tegra/Makefile b/drivers/firmware/tegra/Makefile index 49c87e0..2c0417e 100644 --- a/drivers/firmware/tegra/Makefile +++ b/drivers/firmware/tegra/Makefile @@ -6,3 +6,7 @@ tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o obj-$(CONFIG_TEGRA_IVC) += ivc.o + +tegra-mce-y = mce.o +tegra-mce-$(CONFIG_ARCH_TEGRA_194_SOC) += mce-tegra194.o +obj-$(CONFIG_TEGRA_MCE) += tegra-mce.o diff --git a/drivers/firmware/tegra/mce-tegra194.c b/drivers/firmware/tegra/mce-tegra194.c new file mode 100644 index 0000000..5cec761d --- /dev/null +++ b/drivers/firmware/tegra/mce-tegra194.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, NVIDIA CORPORATION. + */ + +#include +#include +#include +#include + +#include + +/* Issue a NVG request with data */ +static noinline notrace void nvg_send_req_data(u64 req, u64 data) +{ + asm volatile ("msr s3_0_c15_c1_2, %0\n" + "msr s3_0_c15_c1_3, %1\n" + :: "r" (req), "r" (data)); +} + +/* Issue a NVG request with no data */ +static noinline notrace void nvg_send_req(u64 req) +{ + asm volatile ("msr s3_0_c15_c1_2, %0\n" :: "r" (req)); +} + +/* Issue a NVG request to read the command response */ +static noinline notrace u64 nvg_get_response(void) +{ + u64 ret; + + asm volatile ("mrs %0, s3_0_c15_c1_3" : "=r" (ret)); + + return ret; +} + +static int tegra194_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system, + u8 force, u32 wake_mask, bool valid) +{ + nvg_cstate_info_channel_t cstate_info = { 0 }; + + /* disable preemption */ + preempt_disable(); + + /* update CLUSTER_CSTATE? */ + if (cluster) { + cstate_info.bits.cluster_state = cluster; + cstate_info.bits.update_cluster = 1; + } + + /* update CCPLEX_CSTATE? */ + if (ccplex) { + cstate_info.bits.cg_cstate = ccplex; + cstate_info.bits.update_cg = 1; + } + + /* update SYSTEM_CSTATE? */ + if (system) { + cstate_info.bits.system_cstate = system; + cstate_info.bits.update_system = 1; + } + + /* update wake mask value? */ + if (valid) + cstate_info.bits.update_wake_mask = 1; + + /* set the wake mask */ + cstate_info.bits.wake_mask = wake_mask; + + /* set the updated cstate info */ + nvg_send_req_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, cstate_info.flat); + + /* enable preemption */ + preempt_enable(); + + return 0; +} + +static int tegra194_mce_update_crossover_time(u32 type, u32 time) +{ + if (type != TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND && + type != TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND && + type != TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND) { + pr_err("%s: unknown crossover type (%d)\n", __func__, type); + return -EINVAL; + } + + /* disable pre-emption*/ + preempt_disable(); + + nvg_send_req_data(type, (u64)time); + + /* enable pre-emption */ + preempt_enable(); + + return 0; +} + +static int tegra194_mce_read_cstate_stats(u32 state, u64 *stats) +{ + if (!stats) + return -EINVAL; + + /* disable preemption */ + preempt_disable(); + + nvg_send_req_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, (u64)state); + nvg_send_req(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE); + *stats = nvg_get_response(); + + /* enable preemption */ + preempt_enable(); + + return 0; +} + +static int tegra194_mce_read_versions(u32 *major, u32 *minor) +{ + u64 version; + + if (!major || !minor) + return -EINVAL; + + /* disable preemption */ + preempt_disable(); + + nvg_send_req(TEGRA_NVG_CHANNEL_VERSION); + version = nvg_get_response(); + *minor = (u32)version; + *major = (u32)(version >> 32); + + /* enable preemption */ + preempt_enable(); + + return 0; +} + +static struct tegra_mce_ops t194_mce_ops = { + .update_cstate_info = tegra194_mce_update_cstate_info, + .update_crossover_time = tegra194_mce_update_crossover_time, + .read_cstate_stats = tegra194_mce_read_cstate_stats, + .read_versions = tegra194_mce_read_versions, +}; + +static int __init tegra194_mce_early_init(void) +{ + tegra_mce_set_ops(&t194_mce_ops); + + return 0; +} +early_initcall(tegra194_mce_early_init); + +MODULE_DESCRIPTION("NVIDIA Tegra194 MCE driver"); +MODULE_AUTHOR("NVIDIA Corporation"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/firmware/tegra/mce.c b/drivers/firmware/tegra/mce.c new file mode 100644 index 0000000..6d949ff --- /dev/null +++ b/drivers/firmware/tegra/mce.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, NVIDIA CORPORATION. + */ + +#include +#include + +static struct tegra_mce_ops *mce_ops; + +void tegra_mce_set_ops(struct tegra_mce_ops *tegra_plat_mce_ops) +{ + mce_ops = tegra_plat_mce_ops; +} + +/** + * Specify deepest cluster/ccplex/system states allowed. + * + * @cluster: deepest cluster-wide state + * @ccplex: deepest ccplex-wide state + * @system: deepest system-wide state + * @force: forced system state + * @wake_mask: wake mask to be updated + * @valid: is wake_mask applicable? + * + * Returns 0 if success. + */ +int tegra_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system, + u8 force, u32 wake_mask, bool valid) +{ + if (mce_ops && mce_ops->update_cstate_info) + return mce_ops->update_cstate_info(cluster, ccplex, system, force, + wake_mask, valid); + else + return -EOPNOTSUPP; +} +EXPORT_SYMBOL_GPL(tegra_mce_update_cstate_info); + +/** + * Update threshold for one specific c-state crossover + * + * @type: type of state crossover. + * @time: idle time threshold. + * + * Returns 0 if success. + */ +int tegra_mce_update_crossover_time(u32 type, u32 time) +{ + if (mce_ops && mce_ops->update_crossover_time) + return mce_ops->update_crossover_time(type, time); + else + return -EOPNOTSUPP; +} +EXPORT_SYMBOL_GPL(tegra_mce_update_crossover_time); + +/** + * Query the runtime stats of a specific cstate + * + * @state: c-state of the stats. + * @stats: output integer to hold the stats. + * + * Returns 0 if success. + */ +int tegra_mce_read_cstate_stats(u32 state, u64 *stats) +{ + if (mce_ops && mce_ops->read_cstate_stats) + return mce_ops->read_cstate_stats(state, stats); + else + return -EOPNOTSUPP; +} +EXPORT_SYMBOL_GPL(tegra_mce_read_cstate_stats); + +/** + * Read out MCE API major/minor versions + * + * @major: output for major number. + * @minor: output for minor number. + * + * Returns 0 if success. + */ +int tegra_mce_read_versions(u32 *major, u32 *minor) +{ + if (mce_ops && mce_ops->read_versions) + return mce_ops->read_versions(major, minor); + else + return -EOPNOTSUPP; +} +EXPORT_SYMBOL_GPL(tegra_mce_read_versions); diff --git a/include/soc/tegra/mce.h b/include/soc/tegra/mce.h new file mode 100644 index 0000000..d4be89f --- /dev/null +++ b/include/soc/tegra/mce.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 NVIDIA Corporation + */ + +#ifndef __SOC_TEGRA_MCE_H__ +#define __SOC_TEGRA_MCE_H__ + +/* + * For correct version validation, below two defines need to be + * updated whenever there is a new ARI implementation. + */ +#define CUR_ARI_VER_MAJOR 1 +#define CUR_ARI_VER_MINOR 2 + +int tegra_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system, + u8 force, u32 wake_mask, bool valid); +int tegra_mce_update_crossover_time(u32 type, u32 time); +int tegra_mce_read_cstate_stats(u32 state, u64 *stats); +int tegra_mce_read_versions(u32 *major, u32 *minor); + +struct tegra_mce_ops { + int (*update_cstate_info)(u32 cluster, u32 ccplex, u32 system, + u8 force, u32 wake_mask, bool valid); + int (*update_crossover_time)(u32 type, u32 time); + int (*read_cstate_stats)(u32 state, u64 *stats); + int (*read_versions)(u32 *major, u32 *minor); +}; + +void tegra_mce_set_ops(struct tegra_mce_ops *mce_ops); + +#endif /* __SOC_TEGRA_MCE_H__ */ diff --git a/include/soc/tegra/t194_nvg.h b/include/soc/tegra/t194_nvg.h new file mode 100644 index 0000000..3a5d558 --- /dev/null +++ b/include/soc/tegra/t194_nvg.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 NVIDIA Corporation + */ + +#ifndef __T194_NVG_H__ +#define __T194_NVG_H__ + +/* Header for the NVIDIA Generic interface (NVG) */ + +/* + * Major version increments may break backwards compatibility and binary + * compatibility. Minor version increments occur when there is only new + * functionality. + */ +enum { + TEGRA_NVG_VERSION_MAJOR = 6, + TEGRA_NVG_VERSION_MINOR = 6, +}; + +enum { + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, +}; + +enum { + TEGRA_NVG_CORE_C0 = 0, + TEGRA_NVG_CORE_C1 = 1, + TEGRA_NVG_CORE_C6 = 6, +}; + +/* NVG Data subformats */ +typedef union { + u64 flat; + struct nvg_cstate_info_channel_t { + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + uint32_t wake_mask : 32; + } bits; +} nvg_cstate_info_channel_t; + +#endif /* __T194_NVG_H__ */ From patchwork Thu Mar 4 06:08:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 392931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C5A3C4332E for ; Thu, 4 Mar 2021 06:10:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7EEC64EFE for ; Thu, 4 Mar 2021 06:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234505AbhCDGJb (ORCPT ); Thu, 4 Mar 2021 01:09:31 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:2840 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234559AbhCDGI7 (ORCPT ); Thu, 4 Mar 2021 01:08:59 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 03 Mar 2021 22:08:19 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 4 Mar 2021 06:08:18 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 4 Mar 2021 06:08:18 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v1 3/5] dt-bindings: arm: Add cpu-idle-states to Tegra194 CPU nodes Date: Wed, 3 Mar 2021 22:08:10 -0800 Message-ID: <1614838092-30398-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614838099; bh=AeHcRoq9hm4Y3F+W1Gxplw/dz7bL3IgrAIK7ZKNNaTs=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=naNRmYJ/G+O+i3b1zVhsYooD+1K7cWCKGfjZlcdq6TbBSO+JsQcBZUhi9f7btn7b+ 1zUDtqGiDI0Aim2OKGKzv5yxFmGe5IOcY8nlf0nnBkuGFqDXOLUjSdfw/iWOD7rTwG p8kRiYRRP+cZU3y01cRGtj24/v294lYycf89kGpKiCu2CmRH5aLKQE2ixxynTC1UMS S1+/a+41C3akernmDyc5eY1wzXql976hFxanmeF1hkLtrdyBVQH3mkq2ITMUEMqy8z mHUKl66hdWEB+EGFqADOD2GQycZy1JSb3xJxlKPJW2DcqwtmtSaJByiWAvC8FajoX8 yHItFQPl1rW/Q== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds cpu-idle-states and corresponding state nodes to Tegra194 CPU in dt-binding document Signed-off-by: Sowjanya Komatineni --- .../bindings/arm/nvidia,tegra194-ccplex.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml index c9675c4..e1a5005 100644 --- a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml +++ b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml @@ -30,6 +30,36 @@ properties: Specifies the bpmp node that needs to be queried to get operating point data for all CPUs. + cluster-deepest-power-state: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU cluster deepest power state ID. + +patternProperties: + "^[a-z0-9]+$": + type: object + description: | + CPU core idle state nodes. + Refer to Documentation/devicetree/bindings/arm/idle-states.yaml + + properties: + compatible: + enum: + - nvidia,tegra194-cpuidle-core + + cpu_crossover_thresholds: + type: object + description: CPU idle states crossover threshold time in uSec. + + patternProperties: + "^[a-z0-9]+$": + type: object + + properties: + crossover_c1_c6: + $ref: /schemas/types.yaml#/definitions/uint32 + crossover_cc1_cc6: + $ref: /schemas/types.yaml#/definitions/uint32 + additionalProperties: true examples: @@ -39,12 +69,14 @@ examples: nvidia,bpmp = <&bpmp>; #address-cells = <1>; #size-cells = <0>; + cluster-deepest-power-state = <0x6>; cpu0_0: cpu@0 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + cpu-idle-states = <&C6>; }; cpu0_1: cpu@1 { @@ -52,6 +84,7 @@ examples: device_type = "cpu"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&C6>; }; cpu1_0: cpu@100 { @@ -59,6 +92,7 @@ examples: device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&C6>; }; cpu1_1: cpu@101 { @@ -66,6 +100,25 @@ examples: device_type = "cpu"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&C6>; + }; + + cpu_core_power_states { + C6: c6 { + compatible = "nvidia,tegra194-cpuidle-core"; + idle-state-name = "CPU powergated, state retained"; + wakeup-latency-us = <2000>; + min-residency-us = <30000>; + arm,psci-suspend-param = <0x6>; + status = "okay"; + }; + }; + + cpu_crossover_thresholds { + thresholds { + crossover_c1_c6 = <30000>; + crossover_cc1_cc6 = <80000>; }; + }; }; ... From patchwork Thu Mar 4 06:08:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 393812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F6FC43332 for ; Thu, 4 Mar 2021 06:10:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53A5264F09 for ; Thu, 4 Mar 2021 06:10:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234573AbhCDGKC (ORCPT ); Thu, 4 Mar 2021 01:10:02 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:2990 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234570AbhCDGJh (ORCPT ); Thu, 4 Mar 2021 01:09:37 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 03 Mar 2021 22:08:20 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 4 Mar 2021 06:08:18 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 4 Mar 2021 06:08:19 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v1 4/5] cpuidle: Add Tegra194 cpuidle driver Date: Wed, 3 Mar 2021 22:08:11 -0800 Message-ID: <1614838092-30398-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614838100; bh=0pJEP6jipLYvv6sFAICyxbzrST6NiET4EpYzd0/C6LI=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=BBZ5qWoUshnDmW9wQt64U6agB1kKABpctK/uoHFjtBAetyOgIFGdK2yZFazxEODw9 XtFvVNGIu73PxF/8DzhQDKGBRdz3/ux5QjF4e2IHyue/5xt0/6wFoDSaB14zfrXLnj R45x2lObcErWgMGdZfTrdVy1znKDdVpA0cICYElxpOLFhFKOxO75INyaiUAdWSNlx+ ZjG5xuPSZ19pYdGAJJHWjSkrJhYdzaobyoGIdUPX4PWelCDPRd2UzTrsd8Xs2lOeUo Tgp3gQGyoU+COWXS4tENmQJgLuS5wKBhrVtHWcQKGJlmVXSzZ+X43mr2Bvpa+CpR03 InslMDnEATnAg== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds cpuidle driver for Tegra194. Tegra194 Carmel CPU supports two core idle state C1 (clock gated) and C6 (power gated with state restoration) and one cluster idle state CC6 (power gated). MCE firmware makes decision on core/cluster power state transition based on its background tasks and states information provided by CPU idle driver. CPU idle driver provides deepest cluster power state, core power state transition request, estimated time of next wake-up and states crossover thresholds to MCE firmware through Tegra mce driver. Signed-off-by: Sowjanya Komatineni --- drivers/cpuidle/Kconfig.arm | 10 ++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra194.c | 319 +++++++++++++++++++++++++++++++++++++ 3 files changed, 330 insertions(+) create mode 100644 drivers/cpuidle/cpuidle-tegra194.c diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 0844fad..e9adad1 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -105,6 +105,16 @@ config ARM_TEGRA_CPUIDLE help Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs. +config ARM_TEGRA194_CPUIDLE + tristate "CPU Idle Driver for NVIDIA Tegra194 SoC" + depends on ARCH_TEGRA_194_SOC + select ARM_CPU_SUSPEND + select DT_IDLE_STATES + select TEGRA_MCE + default y + help + Select this to enable cpuidle for NVIDIA Tegra194 SoC. + config ARM_QCOM_SPM_CPUIDLE bool "CPU Idle Driver for Qualcomm Subsystem Power Manager (SPM)" depends on (ARCH_QCOM || COMPILE_TEST) && !ARM64 diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 26bbc5e..4d89578 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o obj-$(CONFIG_ARM_PSCI_CPUIDLE) += cpuidle-psci.o obj-$(CONFIG_ARM_PSCI_CPUIDLE_DOMAIN) += cpuidle-psci-domain.o obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o +obj-$(CONFIG_ARM_TEGRA194_CPUIDLE) += cpuidle-tegra194.o obj-$(CONFIG_ARM_QCOM_SPM_CPUIDLE) += cpuidle-qcom-spm.o ############################################################################### diff --git a/drivers/cpuidle/cpuidle-tegra194.c b/drivers/cpuidle/cpuidle-tegra194.c new file mode 100644 index 0000000..4ae67ce --- /dev/null +++ b/drivers/cpuidle/cpuidle-tegra194.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU idle driver for Tegra194 CPUs + * + * Copyright (c) 2020-2021, NVIDIA Corporation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "cpuidle-psci.h" +#include "dt_idle_states.h" + +#define T194_NVG_CROSSOVER_C6 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND +#define T194_NVG_CROSSOVER_CC6 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND + +#define PSCI_PSTATE_ID_MASK 0xf +#define PSCI_PSTATE_WKTIM_MASK 0x0ffffff0 +#define PSCI_PSTATE_WKTIM_SHIFT 4 + +/* + * BG_TIME is margin added to target_residency so that actual HW has better + * chance entering deep idle state instead of getting back to shallower one. + * Units in us. + */ +#define BG_TIME 2000 + +static DEFINE_PER_CPU_READ_MOSTLY(u32 *, psci_power_state); + +static struct cpuidle_driver t194_cpu_idle_driver; +static enum cpuhp_state hp_state; +static u32 deepest_cc_state; +static u32 tsc_per_usec; + +static bool check_mce_version(void) +{ + u32 mce_version_major, mce_version_minor; + int err; + + err = tegra_mce_read_versions(&mce_version_major, &mce_version_minor); + if (!err && mce_version_major >= TEGRA_NVG_VERSION_MAJOR) + return true; + else + return false; +} + +static int +t194_cpu_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) +{ + u32 *state = __this_cpu_read(psci_power_state); + u32 power_state = state[index]; + u32 wake_time; + int ret; + + /* + * MCE firmware does the state transition based on requested idle state, + * state crossover thresholds and target residency time along with its + * background work. + * Pass the state target_residency time along with state ID to MCE + * firmware through PSCI power-state value. + * + * LSB 8 bits of wake time is lost and only 24 MSB bits of wake time can fit + * into additional bits of state value. + */ + wake_time = (drv->states[index].target_residency + BG_TIME) * tsc_per_usec; + power_state |= ((wake_time >> PSCI_PSTATE_WKTIM_SHIFT) & PSCI_PSTATE_WKTIM_MASK); + + if ((power_state & PSCI_PSTATE_ID_MASK) == TEGRA_NVG_CORE_C6) + ret = CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(psci_cpu_suspend_enter, index, + power_state); + else + ret = CPU_PM_CPU_IDLE_ENTER_PARAM(psci_cpu_suspend_enter, index, power_state); + + return ret; +} + +static struct cpuidle_driver t194_cpu_idle_driver = { + .name = "tegra194_cpuidle_driver", + .owner = THIS_MODULE, + .states[0] = { + .enter = t194_cpu_enter_state, + .exit_latency = 1, + .target_residency = 1, + .power_usage = UINT_MAX, + .flags = 0, + .name = "c1", + .desc = "CPU clock gated", + } +}; + +static const struct of_device_id t194_cpuidle_of_match[] = { + { .compatible = "nvidia,tegra194-cpuidle-core", .data = t194_cpu_enter_state }, + { }, +}; + +struct xover_table { + char *name; + int index; +}; + +static void send_crossover(void *data) +{ + struct device_node *of_states = (struct device_node *)data; + struct device_node *child; + u32 value; + int i; + + struct xover_table table1[] = { + {"crossover_c1_c6", T194_NVG_CROSSOVER_C6}, + {"crossover_cc1_cc6", T194_NVG_CROSSOVER_CC6}, + }; + + /* pass the state crossover thresholds to MCE firmware */ + for_each_child_of_node(of_states, child) + for (i = 0; i < ARRAY_SIZE(table1); i++) { + if (of_property_read_u32(child, table1[i].name, &value) == 0) + tegra_mce_update_crossover_time(table1[i].index, + value * tsc_per_usec); + } +} + +static int crossover_init(struct device_node *cpunode) +{ + struct device_node *cpu_xover; + + cpu_xover = of_get_child_by_name(cpunode, "cpu_crossover_thresholds"); + if (!cpu_xover) + pr_warn("cpuidle: %s: missing crossover thresholds in dt\n", __func__); + else + on_each_cpu_mask(cpu_online_mask, send_crossover, cpu_xover, 1); + + return 0; +} + +static void program_cc_state(void *data) +{ + u32 *cc_state = (u32 *)data; + + tegra_mce_update_cstate_info(*cc_state, 0, 0, 0, 0, 0); +} + +static int +tegra_suspend_notify_callback(struct notifier_block *nb, unsigned long action, void *pcpu) +{ + switch (action) { + case PM_POST_SUSPEND: + /* + * Re-program deepest allowed cluster and cluster group power state + * after system resumes from SC7 + */ + on_each_cpu_mask(cpu_online_mask, program_cc_state, &deepest_cc_state, 1); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block suspend_notifier = { + .notifier_call = tegra_suspend_notify_callback, +}; + +static int tegra_cpu_online(unsigned int cpu) +{ + /* + * Program deepest allowed cluster and cluster group power state + * after a core in that cluster is onlined. + */ + smp_call_function_single(cpu, program_cc_state, &deepest_cc_state, 1); + + return 0; +} + +static int tegra_cpuidle_psci_dt_init(struct device *dev, struct cpuidle_driver *drv) +{ + unsigned int state_count = drv->state_count; + struct device_node *cpu_node, *state_node; + int i, cpu, state_idx = 1, ret = 0; + u32 *psci_states; + + psci_states = devm_kcalloc(dev, state_count, sizeof(*psci_states), GFP_KERNEL); + if (!psci_states) + return -ENOMEM; + + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask)); + for (i = 1; ; i++) { + state_node = of_get_cpu_state_node(cpu_node, i - 1); + if (!state_node) + break; + + if (!of_device_is_available(state_node)) { + of_node_put(state_node); + continue; + } + + ret = psci_dt_parse_state_node(state_node, &psci_states[state_idx++]); + of_node_put(state_node); + if (ret) + goto put_cpunode; + } + + of_node_put(cpu_node); + + for_each_online_cpu(cpu) + per_cpu(psci_power_state, cpu) = psci_states; + + return 0; + +put_cpunode: + of_node_put(cpu_node); + return ret; +} + +static int __init tegra194_cpuidle_probe(struct platform_device *pdev) +{ + struct cpumask *cpumask; + int cpu, ret; + + if (!check_mce_version()) { + pr_err("cpuidle: incompatible MCE version, cannot register driver\n"); + return -ENODEV; + } + + tsc_per_usec = arch_timer_get_cntfrq() / 1000000; + + cpumask = devm_kzalloc(&pdev->dev, cpumask_size(), GFP_KERNEL); + for_each_online_cpu(cpu) + cpumask_set_cpu(cpu, cpumask); + t194_cpu_idle_driver.cpumask = cpumask; + + /* + * CCPLEX MCE firmware does core/cluster state transitions based on idle + * thresholds along with requested state and target residency time. + * So, state idle time crossover thresholds should be provided to MCE + * firmware. + */ + crossover_init(pdev->dev.of_node); + + ret = of_property_read_u32(pdev->dev.of_node, + "cluster-deepest-power-state", &deepest_cc_state); + on_each_cpu_mask(cpu_online_mask, program_cc_state, &deepest_cc_state, 1); + + ret = dt_init_idle_driver(&t194_cpu_idle_driver, t194_cpuidle_of_match, 1); + if (ret <= 0) { + pr_err("cpuidle: failed to init idle driver states\n"); + ret = -ENODEV; + goto probe_exit; + } + + /* initialize cpuidle states psci power-state from DT */ + ret = tegra_cpuidle_psci_dt_init(&pdev->dev, &t194_cpu_idle_driver); + if (ret) + goto probe_exit; + + ret = cpuidle_register(&t194_cpu_idle_driver, NULL); + if (ret) { + pr_err("cpuidle: failed to register cpuidle driver\n"); + goto probe_exit; + } + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "tegra_cpu:online", tegra_cpu_online, NULL); + if (ret < 0) { + pr_err("cpuidle: failed to setup cpu hotplug state callbacks\n"); + goto cpuhp_error; + } + + hp_state = ret; + + register_pm_notifier(&suspend_notifier); + + return 0; + +cpuhp_error: + cpuidle_unregister(&t194_cpu_idle_driver); +probe_exit: + return ret; +} + +static int tegra194_cpuidle_remove(struct platform_device *pdev) +{ + unregister_pm_notifier(&suspend_notifier); + cpuhp_remove_state(hp_state); + cpuidle_unregister(&t194_cpu_idle_driver); + kfree(t194_cpu_idle_driver.cpumask); + + return 0; +} + +static const struct of_device_id tegra194_cpuidle_of_match[] = { + { .compatible = "nvidia,tegra194-ccplex" }, + { /* sentinel */ } +}; + +static struct platform_driver tegra194_cpuidle_driver __refdata = { + .driver = { + .owner = THIS_MODULE, + .name = "cpuidle-tegra194", + .of_match_table = of_match_ptr(tegra194_cpuidle_of_match), + }, + .probe = tegra194_cpuidle_probe, + .remove = tegra194_cpuidle_remove, +}; + +module_platform_driver(tegra194_cpuidle_driver); From patchwork Thu Mar 4 06:08:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 392929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4851CC433E6 for ; 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Thu, 4 Mar 2021 06:08:20 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v1 5/5] arm64: dts: tegra194: Add CPU idle states Date: Wed, 3 Mar 2021 22:08:12 -0800 Message-ID: <1614838092-30398-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> References: <1614838092-30398-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614838101; bh=RzsRJmF/fyXlMNdfcnWNDfADO93LDhVHrFuKPCvUYIY=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=AnvZFBIIXacAaimPcUM/bxF8QJBfikH/qg3ymiHv6yiRdkcDIqzbGM+rWJ/9T9mD0 8O921BI+nIfkbf+qhLilZeW9/97Iwp/rHu8zQQzTmBdREUSzcVlySlrKjdSHau0h++ Rxt7STuDiIJK1J+U9xdsU9UBVtg6liBr78m6MhY3OfLZu/WCPBBbjveKqeZIz6agSH mK/g4U3E2MnXeda/U4mMnBBUSP+/XyWSwfCfAbGuZPKdrRDrxM6Sk2hZWbLEWn/ypT n9njpPu8U97bHrhuH3vSbKYTBbVftESmMWI6dvFuYbc41e7Hj1D3O8Sq1MP8MF8OBZ pJtcycV91fIdw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds CPU core and cluster idle states to Tegra194 device tree Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9449156..f9c2731 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2155,12 +2155,14 @@ nvidia,bpmp = <&bpmp>; #address-cells = <1>; #size-cells = <0>; + cluster-deepest-power-state = <0x6>; cpu0_0: cpu@0 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2175,6 +2177,7 @@ device_type = "cpu"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2189,6 +2192,7 @@ device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2203,6 +2207,7 @@ device_type = "cpu"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2217,6 +2222,7 @@ device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2231,6 +2237,7 @@ device_type = "cpu"; reg = <0x201>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2245,6 +2252,7 @@ device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2259,6 +2267,7 @@ device_type = "cpu"; reg = <0x301>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2343,12 +2352,31 @@ cache-line-size = <64>; cache-sets = <4096>; }; + + cpu_core_power_states { + C6: c6 { + compatible = "nvidia,tegra194-cpuidle-core"; + idle-state-name = "CPU powergated, state retained"; + wakeup-latency-us = <2000>; + min-residency-us = <30000>; + arm,psci-suspend-param = <0x6>; + status = "okay"; + }; + }; + + cpu_crossover_thresholds { + thresholds { + crossover_c1_c6 = <30000>; + crossover_cc1_cc6 = <80000>; + }; + }; }; psci { compatible = "arm,psci-1.0"; status = "okay"; method = "smc"; + cpu_suspend = <0xC4000001>; }; sound {