From patchwork Fri Mar 5 12:47:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393504 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp390628jai; Fri, 5 Mar 2021 04:40:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJyE7bk1l3S4KNTufS+Js4OTYXExrY/v+PgQlyj7PMDUwD+OzuTjx9LwlSVSoe2ej+H9xwL7 X-Received: by 2002:a17:906:9714:: with SMTP id k20mr2020738ejx.519.1614948020720; Fri, 05 Mar 2021 04:40:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614948020; cv=none; d=google.com; s=arc-20160816; b=UqViZtCy55QFxLB7phwtVVNML2YJh5c3Hqm4jjDJuPvvGJ4/Gb1Vsz//YHoRzkkGFB lZ+5PBGG/US6IU5E49vRKrArP3Yo9xGM+LE8ZtT9X5ZcHl7egxAB2S26zUI1GYVpB6B2 QUmxDyRgoc6cMpnVgtYpHwtZgUqqecBCyFxJBkqn27rmgnnRs+Y/jrPXRb+kZW4BeheA 3CJoufyX5zw/BoZngA3CAyvcknK7qVqIerQ8wxrzFsyoFyGRas4s+7VPfqfn4wcqRUie 5GGaNWZAjmQotX4AqBG5Ht2JboiaUv9aT7G1/PeN92MayUsdbeAS62747tQ9KcfaVsOV OXRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=7qoy8ws0GMoO76ZFzFvVASvAp1cibtRrbaHfOrGKlvA=; b=IOzhnYSn0A4afXYnVC4E3gn4gmTBWM2xXvlMpGpr1ffdrIP7h5Q45p0Cb8ArZmSHkU u5v2omtHOOGNUXBNJHbH8P/zSEZ5vFJs8BV5kXeXPsb3sGjeAbuCPQlF01xd8loVVtSY s5OJe/dbSIhoL1TyEReWPRlao301iO538iTOPA3p/jJsh/0AdqW/f0rZQAhhvzXTN9cf 7+GACgqee8z0+91saZpE7X3k9traWTeiPkjUgwLZpD+UJo3IJbUpxIVdBGS2OTOkXStJ ac+hE3Yx9JUYelrFTw7mZwcYIdX3FEfMVLNQTTSrhl3RhM6Hm5vgaod1Wt2YPtKkzD63 DF4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NR94e4OS; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This change makes this parametrable. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: no change drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8187fcf..c58bf96 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = false, \ } -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ { \ - .num_elements = 64, \ + .num_elements = el_count, \ .irq_moderation_ms = 0, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ - .num_elements = 128, \ + .num_elements = el_count, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ - .num_elements = 2048, \ + .num_elements = el_count, \ .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { static struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ - MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ - MHI_EVENT_CONFIG_DATA(1), + MHI_EVENT_CONFIG_DATA(1, 128), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) }; static struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Fri Mar 5 12:47:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393505 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp390700jai; Fri, 5 Mar 2021 04:40:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJyZC2jesU6LR+/245O0GpcxtPl2t9UGA69mNZuPv6V2AIyPsaFSGgU3TBhF0wN1VWZS9N0r X-Received: by 2002:a17:906:71d3:: with SMTP id i19mr2078435ejk.347.1614948025028; Fri, 05 Mar 2021 04:40:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614948025; cv=none; d=google.com; s=arc-20160816; b=Y+FkQDsujYF72DtZviywE8JOxb3CXkRPmJG0JrnxlNc0P/hdU4OJ+sGGnQtVKSTSMa tZJgAo5//ppvufJ/SyRfPTeW04nJn219arv/1sDH2E1DsaWRr+N+xCXLMOXNE+mPBGNh l4FyX9aHsx+a+QsNn+ykDNeOh9MXsqbWG+IBi935wOnDnxW0qVKTvpF51Qwwud4Eh9vo p5xWuvHJbkMVUHt+ZIlYEUV0oBI6JmIa0Rd/YhCsu99GEa6DTRNJNBJjbyJo9a4qQhhU A5QT+I5xXwHoqX/i9c2x/gRDhnfwtzQJAhBpFYqd2Yy4zNH0H4FJTgs0vUYqZdrQlqhR 4cKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=hXwJbBHbKOG31eO3yG/NTbzTUBBq/q1jaZdTaJGXqlE=; b=jIps7z0TSyUOQBZCihQn/5Up9yub9FUIdph6kTy6jgSZe1Wge4p0lfUyoWBtRxsPj2 HXCfBKn7cGG/Tvx2u7byarIUJHJ07wvMfmTSNIK7hdMKeHaLOeKyla/vxBIl/of3Zkb6 +DZbLqT40JTDLyU8BZlMAVi3hQ0JjYhR7+SOBRfN3UgmScMM+hzj60hG/S8DJLhkLqlV 5NSlKkH4Gww/zmMAV/gYskYjWrtm/Xvm2a77rv5lsmYERbD3NCiIhOGOR0LcM6u/FsFK R4BGVIKQR0juQtqfsuPaIM+gTqVsNRJMqDV3tzumP/KQs2Sgxg1Pydu3HqAzQWltWC6I Jbeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qa1zMd9R; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The modem is mainly based on MBIM protocol for both the data and control path. The drivers for these channels (mhi-net-mbim and mhi_uci) are not yet part of the kernel but will be integrated by different series. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: update timeout_ms according real modem boot time drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c58bf96..45d0cf2 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ .num_elements = el_count, \ @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 20000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); From patchwork Fri Mar 5 12:47:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393506 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp390713jai; Fri, 5 Mar 2021 04:40:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJx8CYB72YUimi/57P6SDRFfqftNzKR1atR3X8av3eMHfuPxROW4ubJVDPFh3qpL14xSLK7t X-Received: by 2002:aa7:cd8d:: with SMTP id x13mr8810706edv.286.1614948025877; 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Also add the FIREHOSE channels used by the flash-programmer firmware loaded in EDL mode. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: no change drivers/bus/mhi/pci_generic.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 45d0cf2..c274e65 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -212,6 +212,14 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { + .name = "qcom-sdx24", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_qcom_v1_mhiv_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), @@ -254,6 +262,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ From patchwork Fri Mar 5 12:47:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393507 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp390737jai; Fri, 5 Mar 2021 04:40:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJy+72N8/S/O632PPFslJA75PH/oPfhPtcKR1FcLwIyd5D6xUfhxlrlpn/W5o/iFccD/Jd0D X-Received: by 2002:a17:906:f44:: with SMTP id h4mr2016515ejj.204.1614948027612; Fri, 05 Mar 2021 04:40:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614948027; cv=none; d=google.com; s=arc-20160816; b=p99fH/FaNOxCcmHlpiHBOsiblJ30BhSS0Bt2ydNNkbPBw41+sJoWaI/iQE7NGG4YXj S054C+ZGM9GXfs0yFIvEL1btz4YewnQ/fPxFdmh/rHkJL39bZSmQS+73PYr7MJpRFLSF jhBNmotOhoFy5LNn+03yJWPQcfrFjuATF63h4FseNbgheyP52KUU/eKGHiumI3v0J1cd fw2dyyVURIU3yq4CO3H3l5Cvgzc0UZzhFVY4KplTOfX15SAlOcbYVgeuT4BlJR1yWiJb RnnbCO9eqmLYt0EnVu1LYM4Hw1Qxb+k9oRM6WIIJ4W5YXsNecuqeBrxc6aOBIQNdhDY3 LI9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=VLQJiK7FJqZgMOFQh0WIw0zvyjcVmsT0CUIB/62ZpXA=; b=rkttk7ET7XxtCqYwD2+mT1i6eoz+k6h5JBzHAmY7b1CTUeNMmrrcYUYlfFiZzMxAnk n1f+vBJjF/rmcryvtBicuOY3hCSmjoYWXO0O0h0bIRbTZd41hTwc+dATijQUo6Z7X/nw mVRWPLzfIm63Wk4kQGnPljeDlYICVlOnNowDpaTtbftyY/WfEi49pwrPPCJPj9SL0TYP eg2gMEn/sUv57q8cW4W2UBKwtbowx1EpzOsLt0kGRvVY1hXLxo6L7BG/cEVAhMr9Cr1Z fpk3Qm9cu2OztdkRZGNDAhIm8M9esqHZWLf2kVftcqH4jpUsvbPdcbwcXYdqpKFa97qP p+3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bnvPo/8K"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c8si1080821edj.174.2021.03.05.04.40.27; Fri, 05 Mar 2021 04:40:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bnvPo/8K"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233190AbhCEMjw (ORCPT + 16 others); Fri, 5 Mar 2021 07:39:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbhCEMjg (ORCPT ); Fri, 5 Mar 2021 07:39:36 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D36FFC061574 for ; Fri, 5 Mar 2021 04:39:35 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id u187so1307550wmg.4 for ; Fri, 05 Mar 2021 04:39:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VLQJiK7FJqZgMOFQh0WIw0zvyjcVmsT0CUIB/62ZpXA=; b=bnvPo/8KQ7cd9IGJlQI0ldBNgHBIgiZ3jZjyinBqlqnyxUuYR3eH1zQ+AgN5cFUbkM GGoSeRqSYnM8fC9pYngNf72ckriBzKgpSuc6nkAb/wvG6KOq5qQQq10lnvxMVmldR0yi +WCsCkSP90ERWJZNNq292pVi1NmlBAYc0Uqmjvujx5h4saDhQF1j40iMP+Ha9kKmo9Fx HX8zewV0tafenQCcolXxJ3UY2DAI8z/ie87Xcji75ROV1lKBUbJte77XE/4QoGUhecAK 2YOX42Dgx8AfS+C8Px0rG07+4L1fJD2h6g5X1tc69PvGPqONkbp2yMG28+3nj0uTEumB XF+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VLQJiK7FJqZgMOFQh0WIw0zvyjcVmsT0CUIB/62ZpXA=; b=spLwS7kGujH0WkpdCCsJdTwE0eZzo8WaKdczIk1kMfTUbj5nKB3tCHZuP4vxAJX/Zt FHXblzTGxHo8ipU6tOJyWx9unSfjGO4iu/Kb+OO1+y/IVh678NWnT9L61BISfmqlctig Ro5fml0KV29O4J2qYcpf+SgkheHKTAU0V6vv4m5hLGIHi9oIUseDY/bUlKogOES8U84c hAJe3mSzukvyG5OiTTqNUTXdln/SBq7EbdnhZ1irx5klcIkTrX9YdYyFWJJHAFJAuy81 wjSCABlbXWkeHmb5MZGYSa/ud7w36s2kV4NSyp2Lv/q6gru+Mr4RKd9wDLUi/YwogZ2n Cpcw== X-Gm-Message-State: AOAM530LBliqOEJhguAFhmvJMZw3PnBxY4R+O3QiZ7qx62iGokv9WK1f 9AzUoFCN0MEGTvF58T9CdWVgjg== X-Received: by 2002:a05:600c:4150:: with SMTP id h16mr7138191wmm.120.1614947974483; Fri, 05 Mar 2021 04:39:34 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id f5sm4173256wrx.39.2021.03.05.04.39.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 04:39:34 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v2 4/6] mhi: pci_generic: No-Op for device_wake operations Date: Fri, 5 Mar 2021 13:47:56 +0100 Message-Id: <1614948478-2284-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614948478-2284-1-git-send-email-loic.poulain@linaro.org> References: <1614948478-2284-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The wake_db register presence is highly speculative and can fuze MHI devices. Indeed, currently the wake_db register address is defined at entry 127 of the 'Channel doorbell array', thus writing to this address is equivalent to ringing the doorbell for channel 127, causing trouble with some devics (e.g. SDX24 based modems) that get an unexpected channel 127 doorbell interrupt. This change fixes that issue by setting wake get/put as no-op for pci_generic devices. The wake device sideband mechanism seems really specific to each device, and is AFAIK not defined by the MHI spec. It also removes zeroing initialization of wake_db register during MMIO initialization, the register being set via wake_get/put accessors few cycles later during M0 transition. Signed-off-by: Loic Poulain --- v2: reword commit message drivers/bus/mhi/core/init.c | 2 -- drivers/bus/mhi/pci_generic.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 2159dbc..32eb90f 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -510,8 +510,6 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) /* Setup wake db */ mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->wake_set = false; /* Setup channel db address for each channel in tre_ring */ diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c274e65..4685a83 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -312,6 +312,21 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, } } +static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) +{ + /* no-op */ +} + +static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) +{ + /* no-op */ +} + +static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) +{ + /* no-op */ +} + static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) { struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); @@ -515,6 +530,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) From patchwork Fri Mar 5 12:47:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393511 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp391933jai; Fri, 5 Mar 2021 04:41:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYJg29WIlEI+7cf3wZ2pO0P3I7JJKBHSV/qRaZWmnU8whucZX+umYCY5j0LdBfhzOcuYHS X-Received: by 2002:a17:906:5918:: with SMTP id h24mr2108607ejq.501.1614948030687; Fri, 05 Mar 2021 04:40:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614948030; cv=none; d=google.com; s=arc-20160816; b=T2nSQKrp0jHrCyovvXUaEthsA3OwGwgqMqpM12RBZyTEx/P6o7L3KXt/iECjZCjrnW Ia2aQrKbGvuKZxcSSTmdJVhBcfSU0Zh2m5gteZqnraB3yBAilmuq5CBbHSVfuIr8I5OK RWS/poaqURA8DqQ8c0GilwM9UAlufOpaKyHZqnliFYYqaxOJdXoaJwT2n/zkJw7tQl3O YBkgUb7Y8CP9+VZcjMZrvJnJcXOgod0GCprLsBfBqOigBRipuFhjEsLfKJxvx0FGoIUL wHepbvNQYgSXCI1yYOcwWkrZ5idtAMBEK1Kp9yjBuBpAzRzK/4cg0/WrnjuhLJEY+9IB scBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=a3GgDD69zl4/2/h19pwS+AI+qQbgB4hX4JHShxDn3Xk=; b=oOgzT/ihruvKmDFlXsWMM2UvZZxPmeTKjMeYRDka9L0imPCqPZCkZ0h9RA3NrrKflA bVs9pYpscVDmcVELzqkaSOWH2NJ6SkLVSYSPHTMpTATfQ7FGfkG709qYZyT+QgnXMm28 KLqlmOusH2d7EsYFq9R0nLgaqvQx0bk5lwllGbfRhAZlwX6tw7Z+v0CdgziCHiZYKhDg xQ6EjZqkgoIZfZun/zwbooYCoRF2EAMsXbHwYbR9d1W5HTmceRu9ga90IUwe+2la5hnJ wT76/rqkWR5yipTr/EVQbRN+9uhoTaUFMfvB07LyTmgPQ16wd1/2/TprqxgU2Rb2b1jt euCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dyu2kPYx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c8si1080821edj.174.2021.03.05.04.40.30; Fri, 05 Mar 2021 04:40:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dyu2kPYx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233238AbhCEMjw (ORCPT + 16 others); Fri, 5 Mar 2021 07:39:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232891AbhCEMjh (ORCPT ); Fri, 5 Mar 2021 07:39:37 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2796C061756 for ; Fri, 5 Mar 2021 04:39:36 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id w11so1904296wrr.10 for ; Fri, 05 Mar 2021 04:39:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a3GgDD69zl4/2/h19pwS+AI+qQbgB4hX4JHShxDn3Xk=; b=dyu2kPYxikI2ZQ6c9dVGbLUqMTGrV3RQ/z7I2gMtxxb1cUDnD0TS/CnoXHRrFT1mo4 hO5y2eqx+UcfLsmRn7HCEFsQSr4FqaZkiDsfukrMfZj8IjyFAU4pHFqMsiMsGuUhLLie 5UINke1A9hNM1DpNd0XlxG+ccxcSvW/+/gO6rBQh0tE9OfprSRgpreiYUsIolURXKv98 v9Ai4Ff0nps+71AFjhki1M664SYNXwDfu/Oe5+ckAZ9fuN+O24QiD1Py5XGPfEMAqiWF 30S9egjHzJRtp3E9mLzfHxjp79gSG6QVFMdXjKv3jMAuJfjK9U0ToWdfuVzEq7f5dkOl UONA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a3GgDD69zl4/2/h19pwS+AI+qQbgB4hX4JHShxDn3Xk=; b=Q67Yi6Ex4TfDcKkX/atmrKIEWCConi1rtOMBAD1I2W9iIkLwLgZTqNixbIn4XmSDhN 0oEms3L1pV8p0y+x+W+LbxGTbX9Ez0cqfPbikP0agEV69ghoEGI+6HNW+DeGn8mrbn8g g4dbHT284kkvIvcF1XQzxXncoySxewvoh+JwSzJeft82ppWsyfUicx7M3xxrJV0mTyVU M98oCukAZBWMj/tsF4W9akVYinJLahfJjccAErV+d09uSKo1K2PRJ50unuF7gql+EGvS +tJUxWYnhv9MQbRRfGz7O01gmEkTvv8mtwsq5cNXd/9PptlTATKXZ9aAe1td8mXgIos0 o26w== X-Gm-Message-State: AOAM532s5EQ8YeuMPuRKBq0ztvTsbA9WnD+fMSJXtI+L5Q5YTJswhxXa L/i39RVFt9DxYfKE18zAL7/QHZupZJTJOl+v X-Received: by 2002:adf:f7cc:: with SMTP id a12mr9226925wrq.54.1614947975429; Fri, 05 Mar 2021 04:39:35 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id f5sm4173256wrx.39.2021.03.05.04.39.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 04:39:34 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v2 5/6] mhi: pci_generic: Use generic PCI power management Date: Fri, 5 Mar 2021 13:47:57 +0100 Message-Id: <1614948478-2284-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614948478-2284-1-git-send-email-loic.poulain@linaro.org> References: <1614948478-2284-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PCI core can take care of proper PCI suspend/resume operations, but this is discarded when the driver saves PCI state by its own. This currently prevents the PCI core to enable PME (for modem initiated D3 exit) which is requested for proper runtime pm support. This change deletes explicit PCI state-saving and state-set from suspend callback, letting the PCI doing the appropriate work. Signed-off-by: Loic Poulain --- v2: no change drivers/bus/mhi/pci_generic.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 4685a83..4ab0aa8 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -544,9 +544,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, mhi_pdev); - /* Have stored pci confspace at hand for restore in sudden PCI error */ + /* Have stored pci confspace at hand for restore in sudden PCI error. + * cache the state locally and discard the PCI core one. + */ pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_load_saved_state(pdev, NULL); pci_enable_pcie_error_reporting(pdev); @@ -717,10 +720,8 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) /* Transition to M3 state */ mhi_pm_suspend(mhi_cntrl); - pci_save_state(pdev); pci_disable_device(pdev); pci_wake_from_d3(pdev, true); - pci_set_power_state(pdev, PCI_D3hot); return 0; } @@ -732,14 +733,13 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - pci_set_master(pdev); - err = pci_enable_device(pdev); if (err) goto err_recovery; + pci_set_master(pdev); + pci_wake_from_d3(pdev, false); + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { From patchwork Fri Mar 5 12:47:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393508 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp390783jai; Fri, 5 Mar 2021 04:40:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJxZMTYwqHx9geF8/K70Wm/NrloG2yGz0/TQgDr/9KWrAG3JaY+yparbKEMn6fRxUultCMi/ X-Received: by 2002:a17:906:bd2:: with SMTP id y18mr2067538ejg.482.1614948030230; Fri, 05 Mar 2021 04:40:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614948030; cv=none; d=google.com; s=arc-20160816; b=vTAXpkTd39B2jT3jkN7dCbLIJUWvu/vGoekC+BRum91IbCdSYUvqzOEkLZ1s1YkgB1 dR7cqndYzUVn/bzWsQ043nRaXsdE9ii/KQbMVifwzlJWfha4eNEyIz4c8ZyFRll5UfcI 2srTFJAroUX83G/JwFJTi8y4j542HwcOOiQgqi0OjjAHFi6KSb30eQJB05h+MP24DbTg f+0QMECcBe9RAWKAGTeoKCfV4VRh9LO2Fe0kriw0twXdNRBqcDc1YVPjG0PYqbglkSLO CGry81amKNySMJiaQfNG0tQ1V3l5SKfBGujARrT2X6k6MUMx1ksdhiinST1lQfEHA614 h5tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=vwZP6CmHJ7pwo/dc1QlCiNITnkzK3g1H3RNDeoUYb4g=; b=oTD+vhD1zRupNSwfEueKSzuWyGO/3X65c3JDAsDS+Beguk9rgWt1eN2N4xvSpBA+TT SnfVyHyo+mB+9KL6daki8zE5NjaNwdasKTTr8lXoCjlVeVcWqWbpA1s7AQrYWYJhc3ON fqlFbv1/k2Kveq4sv7v39wbGr3yGexBsNiODaEelG9AiWwNT7iBrzW3PA4YdGNx9n/z3 2TZu0ik5T+dO41Z7l0DKNRnUHPCEjdNOUkda1htOWDYG61KVBYnhQlrurbj7OWA0Sgfn Pj+mT7ttVlghmWrYZM/xTJgpA1a4Gfch6nA8ozuKs8fFsVWbYfqnH2fspc3/1QDZiVPd iHAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VmMD0w9y; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In that mode, all MHI operations are suspended and the PCI device can be safely put into PCI D3 state. The device is then resumed from D3/M3 either because of host initiated MHI operation (e.g. buffer TX) or because the device (modem) has triggered wake-up via PME feature (e.g. on incoming data). Same procedures can be used for system wide or runtime suspend/resume. Signed-off-by: Loic Poulain --- v2: replace force_runtime_suspend/resume via local function to ensure device is always resumed during system resume whatever its runtime pm state. drivers/bus/mhi/pci_generic.c | 95 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 4ab0aa8..e36f5a9 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -274,6 +275,7 @@ MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); enum mhi_pci_device_status { MHI_PCI_DEV_STARTED, + MHI_PCI_DEV_SUSPENDED, }; struct mhi_pci_device { @@ -306,6 +308,11 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, case MHI_CB_FATAL_ERROR: case MHI_CB_SYS_ERROR: dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); + pm_runtime_forbid(&pdev->dev); + break; + case MHI_CB_EE_MISSION_MODE: + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_allow(&pdev->dev); break; default: break; @@ -427,13 +434,19 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ - return 0; + /* The runtime_get() MHI callback means: + * Do whatever is requested to leave M3. + */ + return pm_runtime_get(mhi_cntrl->cntrl_dev); } static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ + /* The runtime_put() MHI callback means: + * Device can be moved in M3 state. + */ + pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); + pm_runtime_put(mhi_cntrl->cntrl_dev); } static void mhi_pci_recovery_work(struct work_struct *work) @@ -447,6 +460,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); del_timer(&mhi_pdev->health_check_timer); + pm_runtime_forbid(&pdev->dev); /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -454,7 +468,6 @@ static void mhi_pci_recovery_work(struct work_struct *work) mhi_unprepare_after_power_down(mhi_cntrl); } - /* Check if we can recover without full reset */ pci_set_power_state(pdev, PCI_D0); pci_load_saved_state(pdev, mhi_pdev->pci_state); pci_restore_state(pdev); @@ -488,6 +501,10 @@ static void health_check(struct timer_list *t) struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return; + if (!mhi_pci_is_alive(mhi_cntrl)) { dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); queue_work(system_long_wq, &mhi_pdev->recovery_work); @@ -575,6 +592,14 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) /* start health check */ mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + /* Only allow runtime-suspend if PME capable (for wakeup) */ + if (pci_pme_capable(pdev, PCI_D3hot)) { + pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + } + return 0; err_unprepare: @@ -598,6 +623,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) mhi_unprepare_after_power_down(mhi_cntrl); } + /* balancing probe put_noidle */ + if (pci_pme_capable(pdev, PCI_D3hot)) + pm_runtime_get_noresume(&pdev->dev); + mhi_unregister_controller(mhi_cntrl); } @@ -708,31 +737,48 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; -static int __maybe_unused mhi_pci_suspend(struct device *dev) +static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return 0; del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + goto pci_suspend; /* Nothing to do at MHI level */ + /* Transition to M3 state */ - mhi_pm_suspend(mhi_cntrl); + err = mhi_pm_suspend(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to suspend device: %d;\n", err); + clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); + return -EBUSY; + } +pci_suspend: pci_disable_device(pdev); pci_wake_from_d3(pdev, true); return 0; } -static int __maybe_unused mhi_pci_resume(struct device *dev) +static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; + if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return 0; + err = pci_enable_device(pdev); if (err) goto err_recovery; @@ -740,6 +786,13 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) pci_set_master(pdev); pci_wake_from_d3(pdev, false); + /* It can be a remote wakeup (no mhi runtime_get), update access time */ + pm_runtime_mark_last_busy(dev); + + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + return 0; /* Nothing to do at MHI level */ + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { @@ -753,13 +806,37 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) return 0; err_recovery: - /* The device may have loose power or crashed, try recovering it */ + /* Do not fail to not mess up our PCI device state, the device likely + * lost power (d3cold) and we simply need to reset it from the recovery + * procedure, trigger the recovery asynchronously to prevent system + * suspend exit delaying. + */ queue_work(system_long_wq, &mhi_pdev->recovery_work); - return err; + return 0; +} + +static int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + pm_runtime_disable(dev); + return mhi_pci_runtime_suspend(dev); +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + int ret; + + /* Depending the platform, device may have lost power (d3cold), we need + * to resume it now to check its state and recover when necessary. + */ + ret = mhi_pci_runtime_resume(dev); + pm_runtime_enable(dev); + + return ret; } static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) };