From patchwork Mon Mar 8 06:35:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 395769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B23C433E6 for ; Mon, 8 Mar 2021 06:37:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F368465200 for ; Mon, 8 Mar 2021 06:37:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234909AbhCHGgv (ORCPT ); Mon, 8 Mar 2021 01:36:51 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57774 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232629AbhCHGgU (ORCPT ); Mon, 8 Mar 2021 01:36:20 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1286a6vf056792; Mon, 8 Mar 2021 00:36:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615185366; bh=WEmR5Z/eVfZg1yoS3V+mkU0/CGlAmAnWGl/eIMdtlyU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TWdRvvncEDQEuTt4nQV4vhTr1LWnzpU4FaD7A0aa8y2MgGUWRWPf0KFp7JKGsVzBJ sFlkJ3K8gqnWnmE7kg29GrNYdOTCHkhy9HYmgptfhNrGeilJnse2NVEggCRrWzLySZ oilkPhfMqUlJkbBoa0X+fcQzERYMhPhx7UJC+/v4= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1286a6GP017507 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Mar 2021 00:36:06 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 8 Mar 2021 00:36:06 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 8 Mar 2021 00:36:06 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1286ZuTT117458; Mon, 8 Mar 2021 00:36:02 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Tom Joseph , Lorenzo Pieralisi , Nadeem Athani CC: , , , , , Lokesh Vutla Subject: [PATCH v4 1/4] dt-bindings: PCI: ti, j721e: Add binding to represent refclk to the connector Date: Mon, 8 Mar 2021 12:05:47 +0530 Message-ID: <20210308063550.6227-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308063550.6227-1-kishon@ti.com> References: <20210308063550.6227-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add binding to represent refclk to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 0880a613ece6..963f90816645 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -46,12 +46,17 @@ properties: maxItems: 1 clocks: - maxItems: 1 - description: clock-specifier to represent input to the PCIe + minItems: 1 + maxItems: 2 + description: |+ + clock-specifier to represent input to the PCIe for 1 item. + 2nd item if present represents reference clock to the connector. clock-names: + minItems: 1 items: - const: fck + - const: pcie_refclk vendor-id: const: 0x104c From patchwork Mon Mar 8 06:35:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 395368 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1464373jai; Sun, 7 Mar 2021 22:37:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxztNeiUFYMPxJb+TvXvCb3OJXBK0bsBYTNNk/WazSUghtKqpPwwFTPypxRR/unOwQGrk7q X-Received: by 2002:a05:6402:1d33:: with SMTP id dh19mr20288727edb.362.1615185451113; Sun, 07 Mar 2021 22:37:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615185451; cv=none; d=google.com; s=arc-20160816; b=UayI/g3ntaPciaScA0b+QAN1y97JVdMTVatGBuKIzbCdXYYBEwNLIx5JAZFe3Rjp3s kVN6kSh4GUVozj/YiKteSUavpMKXaSULPkBR/E+bZF9DGtw0rkjOZr5VoF7LoNunK/F0 AeCUL+CFvDjIX3WfH+hqFqHD5hKb/xrpDltM/usEbgITeSBeLcghdWaMfDOlY/PhJOJU UNSnDD9qzGOZeSF4uTdqlSx/+pcTf82z/mLPiYThAzSJURE2Ml72DJI/DalWhqU0DYE3 HzxhYiMaq0cUA8F0BpBdS6+HZ43tVyBzQqCYzCpVGmR5fozuY6lUfKWmrqFM5Z0BuQpA 2LCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FejSDqeomqCQKLWeCp5I8g8qIQKEwylz/nun8gY7riQ=; b=u8aM3LLwZ24ptVduJvi2oHzmCArTjWVJ+blUG7ZY+/RG475ZtIV1244XRLVdlUuUeV JaL8c+Q7KeGR1vQBWskEoH7k/OOFKNq23QyO8F7ZT+niuvkxROsqLUVV8QvoG7CIYOoG 3Upt/mhv4rNqRelR5pr7H9Qnxe6b4E9jGlCDqlEQ6J++gFVY/nnPRMnVss58xIwViYRQ TrYSlDMXsW00/XQ9cYwge9DjNXq5QSkqhDBL3jXNPnidGC596wTgQOm41vhazFA9CEKf pPiZ17+Q652b+PZ6dTe6UstgG+Pn3cJ0ICf5eLD7iCb/UYsiI5p5/5rbZmkQoCGxQWDG YxcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HsN52u3D; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hc39si6722170ejc.125.2021.03.07.22.37.30; Sun, 07 Mar 2021 22:37:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HsN52u3D; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234913AbhCHGgv (ORCPT + 3 others); Mon, 8 Mar 2021 01:36:51 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57782 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234045AbhCHGgZ (ORCPT ); Mon, 8 Mar 2021 01:36:25 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1286aBsR056820; Mon, 8 Mar 2021 00:36:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615185371; bh=FejSDqeomqCQKLWeCp5I8g8qIQKEwylz/nun8gY7riQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HsN52u3Ddep1o+vJjNvcufQwUG9qFXMsHpCDA3dQskCnCDUCUHePl/N4uFr1dxNy4 +CHh/ZCF0ECgWV+yjpI7AqeUcaQ9v/0xucP0uq1eIrR8OdlzQDgiqCLv26to/5Oiap G23fKjQ2ST44UK4F7bMx558Mu6KIdCPLx+8MwEno= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1286aBjl048522 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Mar 2021 00:36:11 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 8 Mar 2021 00:36:11 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 8 Mar 2021 00:36:10 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1286ZuTU117458; Mon, 8 Mar 2021 00:36:06 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Tom Joseph , Lorenzo Pieralisi , Nadeem Athani CC: , , , , , Lokesh Vutla Subject: [PATCH v4 2/4] dt-bindings: PCI: ti, j721e: Add host mode dt-bindings for TI's AM64 SoC Date: Mon, 8 Mar 2021 12:05:48 +0530 Message-ID: <20210308063550.6227-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308063550.6227-1-kishon@ti.com> References: <20210308063550.6227-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 963f90816645..cc900202df29 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -16,12 +16,14 @@ allOf: properties: compatible: oneOf: - - description: PCIe controller in J7200 + - const: ti,j721e-pcie-host + - description: PCIe controller in AM64 items: - - const: ti,j7200-pcie-host + - const: ti,am64-pcie-host - const: ti,j721e-pcie-host - - description: PCIe controller in J721E + - description: PCIe controller in J7200 items: + - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host reg: @@ -67,6 +69,8 @@ properties: - const: 0xb00d - items: - const: 0xb00f + - items: + - const: 0xb010 msi-map: true @@ -83,7 +87,6 @@ required: - vendor-id - device-id - msi-map - - dma-coherent - dma-ranges - ranges - reset-gpios From patchwork Mon Mar 8 06:35:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 395367 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1464362jai; Sun, 7 Mar 2021 22:37:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJwM9dDsRAUBi8pZ5sa5R7yuuAGnAkFVte3z8kb6/XZZ6NH8ag1Oeu0O2volIS8Egf/t0M1S X-Received: by 2002:a17:906:8447:: with SMTP id e7mr13868003ejy.523.1615185450348; Sun, 07 Mar 2021 22:37:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615185450; cv=none; d=google.com; s=arc-20160816; b=uUdoKKGe6lBLkbIcWD1DTKkoFg826NoDQxUFSU37NWKnoGX8QKk2fJSo3b6rcunUXM 3N9swi8GPcv+v2nFLom9QvxLiGfPOFo2n4nqRDsKg057MUnApjWblOQahTkWyz9aehcS qB9+deG5ZYkLxTUUIJ/dz/siOhWQnicYW1ErTUU8Lg014Qb4jQF5NRJiHR503wtxAWo1 1qdazAVFeHBWVR4sG11Y1DhL4BNGgJfDXiQ7/OAb0l2G2YCZrU8kKxVwAu8zQRzYbT5B IYA1OAZoOXJIe8jsPg5Epppx69Mh1TFBmxxoGzsgK4LlstOHaHQAbMbgArsOYrM7M287 ZnLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uODH0rlQQxDYF6jAbEjsFXPgdBaCE0YdlE+2Nqq1WMA=; b=NuZCgjuJROI3xn2jQV/1FioKHK65fpVVjc/SFlcf3NVkYbTXIOtB0OK6Ji+Dd+qqkF rfNOQCaPXZHIdPVzepd/FfdpuCfPQOVigSNKyMbecx4yffdGUca5UpsHxvBcIZZWqxPc PqdQPvwpIRHgbTVt0lr2bNp3BSdXTjqXvbbMkecvYH6k/n6wRAb0wQ+44+xywZA8vTXc ZP2qtWVeTiiZTeHdcg8sZYxroUmv+GGcQW/P5CKfmuDbmU7aYFafS60dv1BAU+kCXd25 YHBPp/Nx3O+jJdUemIQ7tfWz9Riqmp1SbJf289r6MTuvKgA+4v0yAbpZWQuepJxifarM xtgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iyB5h1St; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hc39si6722170ejc.125.2021.03.07.22.37.30; Sun, 07 Mar 2021 22:37:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iyB5h1St; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234918AbhCHGgv (ORCPT + 3 others); Mon, 8 Mar 2021 01:36:51 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55876 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229523AbhCHGg3 (ORCPT ); Mon, 8 Mar 2021 01:36:29 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1286aFTn110170; Mon, 8 Mar 2021 00:36:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615185375; bh=uODH0rlQQxDYF6jAbEjsFXPgdBaCE0YdlE+2Nqq1WMA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iyB5h1StywmF+t/eccCnRaFTjuYEpQOiJ/q2x7B90bT9qUVkNMHcDF+VEdQ9UcwB9 tUzhjeUj6FbnyIr44AYahen72rZR+mAg5qsZvMTb4aOKZOVwZD2g9H8gR4DX8+02XB r6uUBa8PoP5F699mi9hNWsInsxgqwRcvotVDLc6E= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1286aFGS017730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Mar 2021 00:36:15 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 8 Mar 2021 00:36:15 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 8 Mar 2021 00:36:15 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1286ZuTV117458; Mon, 8 Mar 2021 00:36:11 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Tom Joseph , Lorenzo Pieralisi , Nadeem Athani CC: , , , , , Lokesh Vutla Subject: [PATCH v4 3/4] dt-bindings: PCI: ti, j721e: Add endpoint mode dt-bindings for TI's AM64 SoC Date: Mon, 8 Mar 2021 12:05:49 +0530 Message-ID: <20210308063550.6227-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308063550.6227-1-kishon@ti.com> References: <20210308063550.6227-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index d06f0c4464c6..aed437dac363 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -16,12 +16,14 @@ allOf: properties: compatible: oneOf: - - description: PCIe EP controller in J7200 + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in AM64 items: - - const: ti,j7200-pcie-ep + - const: ti,am64-pcie-ep - const: ti,j721e-pcie-ep - - description: PCIe EP controller in J721E + - description: PCIe EP controller in J7200 items: + - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep reg: @@ -66,7 +68,6 @@ required: - power-domains - clocks - clock-names - - dma-coherent - max-functions - phys - phy-names From patchwork Mon Mar 8 06:35:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 395369 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1464401jai; Sun, 7 Mar 2021 22:37:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJxrVMj5v6FEuWcTBxi2levPFdXCniQp4g4hbrzI5TlkJm0PT8zBr2pBS6KlZo3Z9aOm0Xje X-Received: by 2002:a05:6402:68e:: with SMTP id f14mr4871913edy.169.1615185453661; Sun, 07 Mar 2021 22:37:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615185453; cv=none; d=google.com; s=arc-20160816; b=Wu36Im/y5C4fWQtv7PAxPHlLutr3LbX1TWDXyAjf+UGjs4H2yKLqD8qlm52f84O/p4 eMnWs1GiDImmeAMq6J5HDDSMyIFPKaXLJ2xYBb2Msym0NJOGE10H/wQRlKJ+43a9f5oS jozxvooFwNLIWedBXgZGGJFC5eZanwrdHgpe8Fo0G9RqJiUUTfrdBhS1mSst4aKP5rwL 4wevlwkRhyxuEres0PrOVesPpHrSGhivqDHht/d15J1SzCe0K0qyEGUIG64+mVHEsWRp 33uF5VwdnuLysxpx0fUyxDUzk/UkrQpDu9wqJJxKcHeq+wu8Pup7ZdYrDVxQokpBKQK2 9GdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RuH1XyFPlD2/xUnAbgo3c6Sl0V2SC3r4WGxGh2uZNc8=; b=Kuc9xPClhXvJqc+zY37K+OxTiBEAic96f/gGVDOY9FPMDRpu6QcF4B+DZ4mD6bvwKH jh/x5bbfTvn2YGKKbJPvE5nCtVD3pf09gw8VOHKJjYiaH/lCBA44y5gbT5wnZWfo5OxS 1/0eYyQOjUdmPprSx7g+wjGnZHiZ9qEv0uYIyTUvE5ymoM9VFJgOtCtXQremJtHxYAGY iZU+3rv/i6O4eSZs1yJcq2ebkjbU8kvx/yRSjuleoOmizQDwVWL+i3SalVlljJCW7dmV NKohA9PK8MFkyBEwwSPrDaq2tuBOCqTqt86a6YgBEi7g5w1m1rejPGfvtY502UYaWYLw Gn+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Yosq7WER; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pci-j721e.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index dac1ac8a7615..7f9dd34b98a9 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -6,6 +6,7 @@ * Author: Kishon Vijay Abraham I */ +#include #include #include #include @@ -50,6 +51,7 @@ enum link_status { struct j721e_pcie { struct device *dev; + struct clk *refclk; u32 mode; u32 num_lanes; struct cdns_pcie *cdns_pcie; @@ -310,6 +312,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) struct cdns_pcie_ep *ep; struct gpio_desc *gpiod; void __iomem *base; + struct clk *clk; u32 num_lanes; u32 mode; int ret; @@ -408,6 +411,20 @@ static int j721e_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + clk = devm_clk_get_optional(dev, "pcie_refclk"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "failed to get pcie_refclk\n"); + goto err_pcie_setup; + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(dev, "failed to enable pcie_refclk\n"); + goto err_get_sync; + } + pcie->refclk = clk; + /* * "Power Sequencing and Reset Signal Timings" table in * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 @@ -422,8 +439,10 @@ static int j721e_pcie_probe(struct platform_device *pdev) } ret = cdns_pcie_host_setup(rc); - if (ret < 0) + if (ret < 0) { + clk_disable_unprepare(pcie->refclk); goto err_pcie_setup; + } break; case PCI_MODE_EP: @@ -476,6 +495,7 @@ static int j721e_pcie_remove(struct platform_device *pdev) struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; struct device *dev = &pdev->dev; + clk_disable_unprepare(pcie->refclk); cdns_pcie_disable_phy(cdns_pcie); pm_runtime_put(dev); pm_runtime_disable(dev);