From patchwork Wed Apr 25 06:17:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 134224 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp462978lji; Tue, 24 Apr 2018 23:17:59 -0700 (PDT) X-Google-Smtp-Source: AIpwx49umgbthwqyWGlBRmaWDUfvisKyEjmhzvrDhrGdwmkoMKONzjY9WXzsDmPhAfO7xmUuKeCx X-Received: by 10.80.196.71 with SMTP id w7mr36587435edf.87.1524637079374; Tue, 24 Apr 2018 23:17:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524637079; cv=none; d=google.com; s=arc-20160816; b=gNc2JoGqNEj5183nKDEqUFYnmNusr1m9IGMRyzbqFBwEkTB9p1V8x2WrpfnlWSl2GY B5zFeQMxf5tW5SGSTLRYI9SvP42UtZeC81GY7UIrP5KSIrV5MOnYzsInasOSvA6p7pEK G56XM2vWgFB8SHj7OyzLI5DlYAsn6gkXsJXdK7zlXf6/RZMrXu9ZK8S/16FQ5EXnGoJ1 5v4+9JyABj5SEq4IS9JRwgJDdalbqn1CoN6V/QjrLEPoUI/uVk28C0LsHfsXomMzsT7Y 3nwkQb6Ch+IjbOcasj9W7dLRGoH8/9tD7SEXC9k6ASWaPfhCsqz9wrfpPKR7N0ylN9W8 aOvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :arc-authentication-results; bh=p8hdeSss7nx+Tkk1OPdrVoSH3whLNz3xstrVD7+ZPBI=; b=E1jo9au5iVzfO0rFLBzej6mvs5QmxsB27F6DH+LNMnf8pDRWK96QmgkhNMn9TDWju7 A3iFb2rSyvMxa/BLI4wZmxK7JMOi7mGGUykA4ZjH9JxaEJnFjdVVLJUXApaE6zhmY2Pa kYzTs+9EaI4O7byRfoD26oc55z3x9wKD5G7aVJVWNDYqyj0TPboH+By6dvhrRHU0ZO/I RXb9G98ODL9M2i76DI+VHgbcxKZCzdFRNJZhrtwZqqfoCs99xxPthOXJLcQM9EFRWN3d DVuX8+Le0R7ffIPrXQLsHFR2YNOLyb5Qz+hO8fUOd/fMhd6SFtMv8JnKuMenuVghDX72 JGlQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id y4si4602483edi.367.2018.04.24.23.17.59; Tue, 24 Apr 2018 23:17:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id DD012C21F82; Wed, 25 Apr 2018 06:17:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=RCVD_IN_DNSWL_MED, UPPERCASE_50_75 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5AC7BC21EA8; Wed, 25 Apr 2018 06:17:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5EDDBC21EA8; Wed, 25 Apr 2018 06:17:54 +0000 (UTC) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by lists.denx.de (Postfix) with ESMTPS id 29455C21E85 for ; Wed, 25 Apr 2018 06:17:53 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 757ADAC76; Wed, 25 Apr 2018 06:17:52 +0000 (UTC) From: Alexander Graf To: u-boot@lists.denx.de Date: Wed, 25 Apr 2018 08:17:51 +0200 Message-Id: <20180425061751.18790-1-agraf@suse.de> X-Mailer: git-send-email 2.12.3 Cc: Michal Simek Subject: [U-Boot] [PATCH v3] zynqmp: Add generic target X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" I would like to create a generic U-Boot build that adapts itself completely based on the DT passed in. That way we can potentially support running random board configurations with a single U-Boot binary built as part of the distribution. Currently a few things are still missing to make it a full reality. The most obvious one I think is the EEPROM location. This would need to also move into something described by DT. Apart from that, we're almost there. This patch adds a defconfig that simply contains all drivers we could make use of. We can then enable individual boards along the way and slowly adapt everything to be fully DT described while we identify each missing bit. Signed-off-by: Alexander Graf --- v1 -> v2: - Remove debug uart v2 -> v3 - show model information instead of custom IDENT_STRING --- configs/xilinx_zynqmp_generic_defconfig | 94 +++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp_generic.h | 23 ++++++++ 2 files changed, 117 insertions(+) create mode 100644 configs/xilinx_zynqmp_generic_defconfig create mode 100644 include/configs/xilinx_zynqmp_generic.h diff --git a/configs/xilinx_zynqmp_generic_defconfig b/configs/xilinx_zynqmp_generic_defconfig new file mode 100644 index 0000000000..a37622bd94 --- /dev/null +++ b/configs/xilinx_zynqmp_generic_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_generic" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc" +CONFIG_ZYNQMP_USB=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/xilinx_zynqmp_generic.h b/include/configs/xilinx_zynqmp_generic.h new file mode 100644 index 0000000000..56bd5bd6f1 --- /dev/null +++ b/include/configs/xilinx_zynqmp_generic.h @@ -0,0 +1,23 @@ +/* + * Configuration for the Xilinx ZynqMP generic platform + * + * (C) Copyright 2018 Alexander Graf + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_GENERIC_H +#define __CONFIG_ZYNQMP_GENERIC_H + +/* All of these should be enumerated using DT instead ... */ + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI1 + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#include + +#endif /* __CONFIG_ZYNQMP_GENERIC_H */