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[81.169.180.215]) by mx.google.com with ESMTP id o1si3120965edl.94.2018.04.25.13.56.44; Wed, 25 Apr 2018 13:56:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DVZh3RsZ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 7C64FC21FD6; Wed, 25 Apr 2018 20:56:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 45943C21F21; Wed, 25 Apr 2018 20:56:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 657DCC21F21; Wed, 25 Apr 2018 20:56:38 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id C4EEAC21F16 for ; Wed, 25 Apr 2018 20:56:37 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3PKuZbJ012248; Wed, 25 Apr 2018 15:56:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524689795; bh=0CRHymPjXRZfGStRqKAurDjbzIkfifcKaLaRu95CRtQ=; h=From:To:CC:Subject:Date; b=DVZh3RsZ3303wU0XyD0a7gemsJt9eif311MrK435KxVACEVMpq5q0EbvUmfhhwtBd hPZayPyE9UNd9JCi3XQcCrnI4QRQ75s0+QPOwHe/JCqzyhcbE/1ORmJrBfbfIaSM8Q YV6nAHQWF0t66C3oygsdM4oPpA3unW6u1eUMULg4= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3PKuYl1025126; Wed, 25 Apr 2018 15:56:34 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 25 Apr 2018 15:56:34 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 25 Apr 2018 15:56:34 -0500 Received: from droidlinux (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3PKuYYs012604; Wed, 25 Apr 2018 15:56:34 -0500 Received: from praneeth by droidlinux with local (Exim 4.82) (envelope-from ) id 1fBRSs-0001Pr-Gg; Wed, 25 Apr 2018 15:56:34 -0500 From: Praneeth Bajjuri To: Praneeth Bajjuri , Date: Wed, 25 Apr 2018 15:56:34 -0500 Message-ID: <1524689794-5413-1-git-send-email-praneeth@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini Subject: [U-Boot] [PATCH 1/3] arm: dra76: fastboot: extend cpu type for getvar command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" 'commit dda0bd674481 ("arm: dra762: Add support for device package identification")' introduces ABZ and ACD package identification. This patch is to extend usage of "fastboot getvar cpu" for DRA76x ABZ and ACD devices. Helps in fixing the boot warning. Warning: fastboot.cpu: unknown CPU rev: 123863298 on CPU : DRA762-GP ES1.0 ABZ package Model: TI AM5748 IDK Board: AM574x IDK REV 1.0A Signed-off-by: Praneeth Bajjuri Reviewed-by: Tom Rini --- arch/arm/mach-omap2/utils.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 1d39625..391055e 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -30,6 +30,8 @@ static void omap_set_fastboot_cpu(void) switch (cpu_rev) { case DRA762_ES1_0: + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: cpu = "DRA762"; break; case DRA752_ES1_0: