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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm18014596pgp.92.2018.05.02.10.47.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 10:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 10:47:49 -0700 Message-Id: <20180502174753.16133-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502174753.16133-1-richard.henderson@linaro.org> References: <20180502174753.16133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 1/5] tcg: Document INDEX_mul[us]h_* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/README | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.14.3 diff --git a/tcg/README b/tcg/README index bb2ea5121b..a5237a9edb 100644 --- a/tcg/README +++ b/tcg/README @@ -431,6 +431,14 @@ double-word product T0. The later is returned in two single-word outputs. Similar to mulu2, except the two inputs T1 and T2 are signed. +* mulsh_i32/i64 t0, t1, t2 +* muluh_i32/i64 t0, t1, t2 + +Provide the high part of a signed or unsigned multiply, respectively. +If mulu2/muls2 are not provided by the backend, the tcg-op generator +can obtain the same results can be obtained by emitting a pair of +opcodes, mul+muluh/mulsh. + ********* Memory Barrier support * mb <$arg> From patchwork Wed May 2 17:48:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 134860 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp964058lji; Wed, 2 May 2018 10:51:59 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpXkHCLDtLiBnlLmNa/j0P9Sv318Vbte5WE77INn94oQFeNkbqW5omNkOixRbuM0ciweB1K X-Received: by 2002:a25:af8b:: with SMTP id g11-v6mr13504628ybh.47.1525283519449; Wed, 02 May 2018 10:51:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525283519; cv=none; d=google.com; s=arc-20160816; b=sp2Ye69+Xckj5HTLbgAPnQxWUVvR7U8J8bOAl1RUE4bfD5d460kOWvMJkqFID12tZd iX8XNsdSZvHP0oJB2YMfG7cEuV5eHKURBck9O9DdCfoeUxsqqK5vdWZlSm+14Uieh3t4 VC+mN6d+rramA6qNGyMoZlKBlW8DdMq0bBhUfv1chQj13OziAQxoqDtHyGGL77u6uV4+ J0ZSwL17Sxq2XDSbdxalnIC+xIp8Dc42kkTKNLXS683e5DUMmAQyGHE6KlPaQemr1ial hnNsFpQaEGID67AK9PTFnfr4BsYNIb5PcO7oTwgO78MvhPE/TQPI2fPSoDni2vBhKsZJ 5ezQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=JwG5fnPfvfkPAI/+Dgh6fhLl16VBeooZ50HvBg3Ow5s=; b=Otq3cAOLUpG0yhPvA2IZfw/e/TOGuT3hSGQXoDDyVFFqW/OYO4WS0VJeJI+sjIqjOD zeGdNSWn4xq8oi3iNhzlj8HhWbrUgMJ+veVhOlqTgrkC6WqgR1eQhslJI1P+Pih0sfgk FqlyoGLad9uSIF98466OCliCGFJwHkl4EzQV+rfaXbQs5Vr8yAVvpNtIE2xJPsihHxDH Pzco3AQnFrryWDWMl/iqwbMGocoGV4UqWXazm/CJFd2AmxO34VwrDteMefTgFEJt3e4h UCzO7zyK24PDXxVvUnx6bNFrazQDaWZLjpilngaUPJlxBJD7yNteXm2Pp54XGE4gm5HJ a4PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fU4ZJk40; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id w7sm22275533pfn.83.2018.05.02.10.48.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 10:48:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 10:48:39 -0700 Message-Id: <20180502174842.16253-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 2/5] tcg/arm: Fix memory barrier encoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Henry Wertz , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Henry Wertz I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Henry Wertz Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index dc83f3e5be..56a32a470f 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -159,8 +159,8 @@ typedef enum { INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, - INSN_DMB_ISH = 0x5bf07ff5, - INSN_DMB_MCR = 0xba0f07ee, + INSN_DMB_ISH = 0xf57ff05b, + INSN_DMB_MCR = 0xee070fba, /* Architected nop introduced in v6k. */ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this From patchwork Wed May 2 17:48:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 134859 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp963956lji; Wed, 2 May 2018 10:51:51 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqRZJpdrjvCA7MEdvIbZRajWSx+Q1LsIEqp9pgKI5c9mFyux3QaXBTljlRMS2Y9v4CY4778 X-Received: by 2002:a25:af8c:: with SMTP id g12-v6mr13235318ybh.133.1525283511164; Wed, 02 May 2018 10:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525283511; cv=none; d=google.com; s=arc-20160816; b=e1PrgDSJSu/4GiRaUM6TD/xpWAi38uTzdL/xLqrquXNFIViWsEz6QO6QAEWCEwAE07 Ujkor2iVJHEcnZy72KlXz/87GarpSBlj6HlHZ7uWJTszNWZCUPkVXuQMxPYNDm0cGb7p FWFxDDblRo6Y5dTFGHjqtf8t0OLLWiE7UeS5zMjtmVr4QGzvW6R/GQYU4sr2+4AyICZc yJHC/OtCHF2ZNtYtXsVeL8jmVREJoyhWkeSMgvBgJZcZ8Hxf2qESzzIy2NDHOmnvTpvx 7o/PbQS5GRmBWvi66RmnmgjoMju5iYZnd2iHB/zp+opjSDsQYd5/BepKzp4L2/gCz7o2 lTiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=S5RU9eEG+8jocHjnBf6OhBHd5z3vDnB9kAxbQcUu2jM=; b=JtcdvgJz5MfyGaOMNHW8Sxr55BE1S1xMB1kIJrWKLD19XzcAhtduax2dPQVCa/8CRS eKYZKhp4nnvoViw5fkphF3o5WyqZQmnEVgjtQCHUwwi4ikg5rRi56qms4N9jM6YB4I7j TGxcHUxqshVMEYNnwx7QVy9t9LeuYz/jg59oLhJfMFv9p4YLgvLbAcf4iosBpt6/6bvz 53EHj3hE7h2N2PGyJJHrGGH0eBlJvovytD+LayuYHet+joJtshkwlLa6ChsNtpo3oXSI GRt2NLmxaXz1fWD/4W7x5U/Ew3vRgZMtWbhYck/IWYZUqSDAljjzN6U/EVq9g9U6dkbg do6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ijhq0fZn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id w7sm22275533pfn.83.2018.05.02.10.48.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 10:48:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 10:48:40 -0700 Message-Id: <20180502174842.16253-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502174842.16253-1-richard.henderson@linaro.org> References: <20180502174842.16253-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 3/5] tcg: Allow wider vectors for cmp and mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In db432672, we allow wide inputs for operations such as add. However, in 212be173 and 3774030a we didn't do the same for compare and multiply. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 70ec889bc1..2ca219734d 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -355,8 +355,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGType type = rt->base_type; int can; - tcg_debug_assert(at->base_type == type); - tcg_debug_assert(bt->base_type == type); + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); if (can > 0) { vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); @@ -377,8 +377,8 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) TCGType type = rt->base_type; int can; - tcg_debug_assert(at->base_type == type); - tcg_debug_assert(bt->base_type == type); + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); can = tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece); if (can > 0) { vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi); From patchwork Wed May 2 17:48:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 134855 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp961504lji; Wed, 2 May 2018 10:49:18 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrx9xs6HkK6MUBn8B9uUAY8DJu4clsZCyaBNiS8V6+nzOypKRTDtPKueB2msU1sbhcFjCX0 X-Received: by 10.176.2.74 with SMTP id 68mr15922530uas.17.1525283358756; Wed, 02 May 2018 10:49:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525283358; cv=none; d=google.com; s=arc-20160816; b=I2VYNDGwpUzyMYABiCxCBUbvu+7zIfuX6euI4CpkEnnG5Lpq38txR7jCz45Te7Y0Px QwSxFY2oWNJVP+VpzOBu5ECrxQtavZHisZF5E5g1bd/hseS45PxOfx5X+CMPI7yq1VIR z70cnkxiYqgZ+p0BW+UPTP/emrKhMY+wiYZMlEeJiUHwovdyrYxdxAuM0B5TTUjTjNIM 9o+XeTSNPf/Ka6KiCxZPQlpkVvVphoQToQjHpZqOZ3zHwC3RPVuEvEBEfDxF0XAcrUdr oY4pAuV5LNeENqMIGn4h+v1imPM2pbftN2NHE+3nrnHpu4NyxdSDdml/4oDSPr86N0JC LNSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=k8JG79sXyY1tqHVrXt7stKLpRTL0iNll2wLFIrgwvMA=; b=NCLOQwgzTV2pgVN+XlUX3HcESsxspc890x86X/ZlJCyS05M93Y5OErtdsq30ueulEw 78VRupAjnIy+Fb0/cHZaBuw1Erzk62TGVwDDJGk6QNt8L8jNlFJG0tHFZF0fjLBZ5Zij 2tuugYt9VhDM/6VJssWE6rxner7E8LNKinavt97SGLZpqTm5plrYvW9mKGjniNuRdon/ WLfsKGE1zVlLQfyXQhHV/wIB4ilJCTcK5vkoWi67kDxr98aQDPqPtSNWO3Jh0YZF99Wj 8fzpIlv5D2sHlHN0Di5co5ci5CirxPY30hWe4hGubX7bueEuR4TY/IrZ+d/Z4Bz3VEip Ar9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X+jNbhHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id w7sm22275533pfn.83.2018.05.02.10.48.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 10:48:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 10:48:41 -0700 Message-Id: <20180502174842.16253-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502174842.16253-1-richard.henderson@linaro.org> References: <20180502174842.16253-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 4/5] tcg: Improve TCGv_ptr support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 91 +++++++++++++++++++++++++++++++++++++------------ tcg/tcg.h | 86 ++++++++++++++++++++++++++++++---------------- target/hppa/translate.c | 16 ++------- tcg/tcg.c | 31 ++--------------- 4 files changed, 130 insertions(+), 94 deletions(-) -- 2.14.3 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 75bb55aeac..5d2c91a1b6 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1137,25 +1137,74 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #endif #if UINTPTR_MAX == UINT32_MAX -# define tcg_gen_ld_ptr(R, A, O) \ - tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) -# define tcg_gen_discard_ptr(A) \ - tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) -# define tcg_gen_add_ptr(R, A, B) \ - tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) -# define tcg_gen_addi_ptr(R, A, B) \ - tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) -# define tcg_gen_ext_i32_ptr(R, A) \ - tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) +# define PTR i32 +# define NAT TCGv_i32 #else -# define tcg_gen_ld_ptr(R, A, O) \ - tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) -# define tcg_gen_discard_ptr(A) \ - tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) -# define tcg_gen_add_ptr(R, A, B) \ - tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) -# define tcg_gen_addi_ptr(R, A, B) \ - tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) -# define tcg_gen_ext_i32_ptr(R, A) \ - tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) -#endif /* UINTPTR_MAX == UINT32_MAX */ +# define PTR i64 +# define NAT TCGv_i64 +#endif + +static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) +{ + glue(tcg_gen_ld_,PTR)((NAT)r, a, o); +} + +static inline void tcg_gen_discard_ptr(TCGv_ptr a) +{ + glue(tcg_gen_discard_,PTR)((NAT)a); +} + +static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) +{ + glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); +} + +static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) +{ + glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); +} + +static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, + intptr_t b, TCGLabel *label) +{ + glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); +} + +static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_mov_i32((NAT)r, a); +#else + tcg_gen_ext_i32_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_extrl_i64_i32((NAT)r, a); +#else + tcg_gen_mov_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_extu_i32_i64(r, (NAT)a); +#else + tcg_gen_mov_i64(r, (NAT)a); +#endif +} + +static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_mov_i32(r, (NAT)a); +#else + tcg_gen_extrl_i64_i32(r, (NAT)a); +#endif +} + +#undef PTR +#undef NAT diff --git a/tcg/tcg.h b/tcg/tcg.h index 30896ca304..eb0d4f6ca7 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -890,15 +890,30 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); - -TCGv_i32 tcg_temp_new_internal_i32(int temp_local); -TCGv_i64 tcg_temp_new_internal_i64(int temp_local); +TCGTemp *tcg_temp_new_internal(TCGType, bool); +void tcg_temp_free_internal(TCGTemp *); TCGv_vec tcg_temp_new_vec(TCGType type); TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); -void tcg_temp_free_i32(TCGv_i32 arg); -void tcg_temp_free_i64(TCGv_i64 arg); -void tcg_temp_free_vec(TCGv_vec arg); +static inline void tcg_temp_free_i32(TCGv_i32 arg) +{ + tcg_temp_free_internal(tcgv_i32_temp(arg)); +} + +static inline void tcg_temp_free_i64(TCGv_i64 arg) +{ + tcg_temp_free_internal(tcgv_i64_temp(arg)); +} + +static inline void tcg_temp_free_ptr(TCGv_ptr arg) +{ + tcg_temp_free_internal(tcgv_ptr_temp(arg)); +} + +static inline void tcg_temp_free_vec(TCGv_vec arg) +{ + tcg_temp_free_internal(tcgv_vec_temp(arg)); +} static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, const char *name) @@ -909,12 +924,14 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, static inline TCGv_i32 tcg_temp_new_i32(void) { - return tcg_temp_new_internal_i32(0); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); + return temp_tcgv_i32(t); } static inline TCGv_i32 tcg_temp_local_new_i32(void) { - return tcg_temp_new_internal_i32(1); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); + return temp_tcgv_i32(t); } static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, @@ -926,12 +943,33 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, static inline TCGv_i64 tcg_temp_new_i64(void) { - return tcg_temp_new_internal_i64(0); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); + return temp_tcgv_i64(t); } static inline TCGv_i64 tcg_temp_local_new_i64(void) { - return tcg_temp_new_internal_i64(1); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); + return temp_tcgv_i64(t); +} + +static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, + const char *name) +{ + TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); + return temp_tcgv_ptr(t); +} + +static inline TCGv_ptr tcg_temp_new_ptr(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); + return temp_tcgv_ptr(t); +} + +static inline TCGv_ptr tcg_temp_local_new_ptr(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); + return temp_tcgv_ptr(t); } #if defined(CONFIG_DEBUG_TCG) @@ -1009,26 +1047,6 @@ do {\ abort();\ } while (0) -#if UINTPTR_MAX == UINT32_MAX -static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; } -static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; } - -#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) -#define tcg_global_mem_new_ptr(R, O, N) \ - TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) -#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) -#define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T)) -#else -static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; } -static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; } - -#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) -#define tcg_global_mem_new_ptr(R, O, N) \ - TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) -#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) -#define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) -#endif - bool tcg_op_supported(TCGOpcode op); void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); @@ -1052,6 +1070,14 @@ TCGv_vec tcg_const_ones_vec(TCGType); TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); +#if UINTPTR_MAX == UINT32_MAX +# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) +# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) +#else +# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) +# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) +#endif + TCGLabel *gen_new_label(void); /** diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c532889b1f..cdc397308b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -151,13 +151,7 @@ #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 -#if UINTPTR_MAX == UINT32_MAX -# define tcg_gen_trunc_reg_ptr(p, r) \ - tcg_gen_trunc_i64_i32(TCGV_PTR_TO_NAT(p), r) -#else -# define tcg_gen_trunc_reg_ptr(p, r) \ - tcg_gen_mov_i64(TCGV_PTR_TO_NAT(p), r) -#endif +#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr #else #define TCGv_reg TCGv_i32 #define tcg_temp_new tcg_temp_new_i32 @@ -251,13 +245,7 @@ #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 -#if UINTPTR_MAX == UINT32_MAX -# define tcg_gen_trunc_reg_ptr(p, r) \ - tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p), r) -#else -# define tcg_gen_trunc_reg_ptr(p, r) \ - tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p), r) -#endif +#define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr #endif /* TARGET_REGISTER_BITS */ typedef struct DisasCond { diff --git a/tcg/tcg.c b/tcg/tcg.c index bb24526c93..b5e706bc49 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -980,7 +980,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, return ts; } -static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) +TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) { TCGContext *s = tcg_ctx; TCGTemp *ts; @@ -1025,18 +1025,6 @@ static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) return ts; } -TCGv_i32 tcg_temp_new_internal_i32(int temp_local) -{ - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local); - return temp_tcgv_i32(t); -} - -TCGv_i64 tcg_temp_new_internal_i64(int temp_local) -{ - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local); - return temp_tcgv_i64(t); -} - TCGv_vec tcg_temp_new_vec(TCGType type) { TCGTemp *t; @@ -1072,7 +1060,7 @@ TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) return temp_tcgv_vec(t); } -static void tcg_temp_free_internal(TCGTemp *ts) +void tcg_temp_free_internal(TCGTemp *ts) { TCGContext *s = tcg_ctx; int k, idx; @@ -1093,21 +1081,6 @@ static void tcg_temp_free_internal(TCGTemp *ts) set_bit(idx, s->free_temps[k].l); } -void tcg_temp_free_i32(TCGv_i32 arg) -{ - tcg_temp_free_internal(tcgv_i32_temp(arg)); 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id w7sm22275533pfn.83.2018.05.02.10.48.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 May 2018 10:48:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 10:48:42 -0700 Message-Id: <20180502174842.16253-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180502174842.16253-1-richard.henderson@linaro.org> References: <20180502174842.16253-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 5/5] tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , peter.maydell@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Laurent Vivier ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st slow path. BC instruction uses a relative address encoded on 14 bits. The slow path functions are added at the end of the generated instructions buffer, in the reverse order of the callers. So more we have slow path functions more the distance between the caller (BC) and the function increases. This patch changes the behavior to generate the functions in the same order of the callers. Cc: qemu-stable@nongnu.org Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps") Signed-off-by: Laurent Vivier Message-Id: <20180429235840.16659-1-lvivier@redhat.com> Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 +- tcg/tcg-ldst.inc.c | 8 ++++---- tcg/tcg.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/tcg/tcg.h b/tcg/tcg.h index eb0d4f6ca7..75fbad128b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -699,7 +699,7 @@ struct TCGContext { /* These structures are private to tcg-target.inc.c. */ #ifdef TCG_TARGET_NEED_LDST_LABELS - struct TCGLabelQemuLdst *ldst_labels; + QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdst) ldst_labels; #endif #ifdef TCG_TARGET_NEED_POOL_LABELS struct TCGLabelPoolData *pool_labels; diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c index 0e14cf4357..47f41b921b 100644 --- a/tcg/tcg-ldst.inc.c +++ b/tcg/tcg-ldst.inc.c @@ -30,7 +30,7 @@ typedef struct TCGLabelQemuLdst { TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ - struct TCGLabelQemuLdst *next; + QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; } TCGLabelQemuLdst; @@ -46,7 +46,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s) TCGLabelQemuLdst *lb; /* qemu_ld/st slow paths */ - for (lb = s->ldst_labels; lb != NULL; lb = lb->next) { + QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { if (lb->is_ld) { tcg_out_qemu_ld_slow_path(s, lb); } else { @@ -72,7 +72,7 @@ static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) { TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); - l->next = s->ldst_labels; - s->ldst_labels = l; + QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); + return l; } diff --git a/tcg/tcg.c b/tcg/tcg.c index b5e706bc49..551caf1c53 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3297,7 +3297,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) s->code_ptr = tb->tc.ptr; #ifdef TCG_TARGET_NEED_LDST_LABELS - s->ldst_labels = NULL; + QSIMPLEQ_INIT(&s->ldst_labels); #endif #ifdef TCG_TARGET_NEED_POOL_LABELS s->pool_labels = NULL;