From patchwork Wed Mar 17 12:25:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 403261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E3EC43333 for ; Wed, 17 Mar 2021 12:26:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BBBC664F6E for ; Wed, 17 Mar 2021 12:26:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229863AbhCQM0D (ORCPT ); Wed, 17 Mar 2021 08:26:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229806AbhCQMZi (ORCPT ); Wed, 17 Mar 2021 08:25:38 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1444C061762 for ; Wed, 17 Mar 2021 05:25:38 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id y5so986172pfn.1 for ; Wed, 17 Mar 2021 05:25:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cGzmTTjWe1AbEuSBzNDXhCdxGNlI9I7Ym5rhNfsOEPE=; b=hyvzVHeaKT5CdkW0D6cUUD6bRVX++YCV20wSSg1coULPHz5AfgOLvfL7HQdaFojqF4 5v5t26HbIHzmBHYJByEC5vRHB0+BuY3YWAuFHJzy78JeIiK+Omr99zGUnnIo0UEk3NJH +7NCVU+du5H0Nc9HPbgBqKXKKf4SQnGGeac+PX2ihWZMdU+GY1g6IlxX9ftl+p47cmeC GB7jHqacMALLLOWAy593vGyu8uMc6wI6cFc+6AXzfAiYhA9FJHJ5ZtCHCeFPTQ1/sWUc DIOWri0EIJbsenDSWoRFMeIGOG9c1TVi3ShhoCPpbZ1KwWu9AaVWZWZXvbLI6BVpbciN H1jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cGzmTTjWe1AbEuSBzNDXhCdxGNlI9I7Ym5rhNfsOEPE=; b=FA6MIT/kyf7j81kF7IT5AFfmBnVPC/PZbFpzsDH30yUuW9xR8IkQYdJbxNhuBVQ/PZ p8PcKIV59I2bylxAg8uE1bE+SgBGL81A99EniA+Ey6krZ85rcvybD0A22JXFzWrRJJko Vc9IJaJ8FdeKTqi5ZB/QGcYT9RzvofnI/PG8bfVPyp7jJGP/W+2Hb1VyEcPgwnn0sQ5D KQ954MCy5qirZC3HywZi7y8H3JZrOwq1GqEnz78CyCo5J5uhUIXkM0ddsHzkhjP8/UVL k5tlr/JKdL1ERyrtoKovAOSYAOF7JBlOWq7pf7j0w3xYizGD3TfKVWkc91jyES8pj2vc NEoQ== X-Gm-Message-State: AOAM532ByYn6Od7KtaEpTPoD+fLmq195NrQHBnySmVPfzhqoHjOrXXj5 A9JASUPH0lRtyVQ1hN0UtW+C X-Google-Smtp-Source: ABdhPJy/SeiYsJVh0qMKBjSvnT0Qdi9a9LDO5ABIuNeOAUoWTJYARGoqrPl1gtZ2yOidGarSm3aqOQ== X-Received: by 2002:aa7:92c7:0:b029:1ee:75b2:2dab with SMTP id k7-20020aa792c70000b02901ee75b22dabmr4123453pfa.61.1615983938243; Wed, 17 Mar 2021 05:25:38 -0700 (PDT) Received: from localhost.localdomain ([103.66.79.72]) by smtp.gmail.com with ESMTPSA id y23sm19285730pfo.50.2021.03.17.05.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 05:25:37 -0700 (PDT) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam Subject: [PATCH v5 2/3] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Date: Wed, 17 Mar 2021 17:55:12 +0530 Message-Id: <20210317122513.42369-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317122513.42369-1-manivannan.sadhasivam@linaro.org> References: <20210317122513.42369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). So let's add a property for declaring such secure regions so that the drivers can skip touching them. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index d0e422f4b3e0..678b39952502 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -143,6 +143,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. + secure-regions: + $ref: /schemas/types.yaml#/definitions/uint64-matrix + description: + Regions in the NAND chip which are protected using a secure element + like Trustzone. This property contains the start address and size of + the secure regions present. + required: - reg From patchwork Wed Mar 17 12:25:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 403144 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp424088jai; Wed, 17 Mar 2021 05:26:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzM+g2P6YjVM4Hu0jhI+68edWnLg6rWMnQZ/Oh2Au2Y1oUD3bXt3eUDEnxXPI/mklG9rxwP X-Received: by 2002:a17:906:5849:: with SMTP id h9mr35708772ejs.551.1615983997300; Wed, 17 Mar 2021 05:26:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615983997; cv=none; d=google.com; s=arc-20160816; b=fMN31PwhKPIkJ2/uBSazOWNAJmaNEXCS0FDi8GWLV5nGDaKYuBmuIY5Lu830TjiKDZ t/ExjJNUzms9HZx3HZx4Kf6HwK17JAH9aQ/ghxfFRT3kVcS579OXOhLCiCdoSXdlCUSY oMsZozpsEcYuYke7Drx+PcDdzcL1PJZ6wKohlvt49GvRtfsYZx3iIu33Wf1DMiMpwu4D gGzoDpYVjk94JcSdmBhFwCmHc9N65QQxptyfRUrJt/tSsfYEF5eWcuLUn3/dvG+voAhz 7tnhzsQ/HDXbXAxrSslQxidCbvzo15HwLbh2ME+oLMQ9Pl3+CwtxUu9cVOP2IyjDbrqb rTmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Z9Fk1ZVyrYehdc+R8QhCU6Tgcb/96NRNVoZXBJNxJZ8=; b=NP+RKleBDULeJ45N+zR0q0SSCMPMLMlMmDxubazAMSzRDEF2fBCDHiclZBFt+6lzri xT6rUrj+8jWu0yN8QS09P5ha3mU7s+Ds2mB3hmia9dUfCRx5hg4qlk/jHzGdL637Mc35 5idgRGHzTlAEIotR984WeT2HW/auAsYtjV7LRxG2ewkSSpJr3IxyoZV8hz+LQTgcd2Cw jUib24qThX83RFfMCUMEk77VQ83B0Gnh1yIpbRh/oSH5BDibaGwsElWgy2ewjH2M1yKq B5uWN9SGh2Ht8smxxFv7K+shSa4nXjhma8npF/lM2QHS41kQrDg9FoYtsedQIncXW7Je TO1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pcy3PYxf; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). The regions are declared using a NAND chip DT property, "secure-regions". So let's make use of this property in the nand core and skip access to the secure regions present in a system. Signed-off-by: Manivannan Sadhasivam --- drivers/mtd/nand/raw/nand_base.c | 105 +++++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 4 ++ 2 files changed, 109 insertions(+) -- 2.25.1 diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c33fa1b1847f..c85cbd491f05 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -278,11 +278,41 @@ static int nand_block_bad(struct nand_chip *chip, loff_t ofs) return 0; } +/** + * nand_check_sec_region() - Check if the region is secured + * @chip: NAND chip object + * @offset: Offset of the region to check + * + * Checks if the region is secured by comparing the offset with the list of + * secure regions obtained from DT. Returns -EIO if the region is secured + * else 0. + */ +static int nand_check_sec_region(struct nand_chip *chip, loff_t offset) +{ + int i, j; + + /* Skip touching the secure regions if present */ + for (i = 0, j = 0; i < chip->nr_sec_regions; i++, j += 2) { + if (offset >= chip->sec_regions[j] && + (offset <= chip->sec_regions[j] + chip->sec_regions[j + 1])) + return -EIO; + } + + return 0; +} + static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) { + int ret; + if (chip->options & NAND_NO_BBM_QUIRK) return 0; + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, ofs); + if (ret) + return ret; + if (chip->legacy.block_bad) return chip->legacy.block_bad(chip, ofs); @@ -397,6 +427,11 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to, return -EINVAL; } + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, to); + if (ret) + return ret; + chipnr = (int)(to >> chip->chip_shift); /* @@ -565,6 +600,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; + + /* Check if the region is secured */ + if (nand_check_sec_region(chip, ofs)) + return -EIO; + /* Return info from the table */ return nand_isreserved_bbt(chip, ofs); } @@ -2737,6 +2777,11 @@ static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf, uint8_t *ecc_code = chip->ecc.code_buf; unsigned int max_bitflips = 0; + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, ((loff_t)page << chip->page_shift)); + if (ret) + return ret; + chip->ecc.read_page_raw(chip, buf, 1, page); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) @@ -3127,6 +3172,11 @@ static int nand_do_read_ops(struct nand_chip *chip, loff_t from, int retry_mode = 0; bool ecc_fail = false; + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, from); + if (ret) + return ret; + chipnr = (int)(from >> chip->chip_shift); nand_select_target(chip, chipnr); @@ -3458,6 +3508,11 @@ static int nand_do_read_oob(struct nand_chip *chip, loff_t from, pr_debug("%s: from = 0x%08Lx, len = %i\n", __func__, (unsigned long long)from, readlen); + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, from); + if (ret) + return ret; + stats = mtd->ecc_stats; len = mtd_oobavail(mtd, ops); @@ -3709,6 +3764,11 @@ static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf, uint8_t *ecc_calc = chip->ecc.calc_buf; const uint8_t *p = buf; + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, ((loff_t)page << chip->page_shift)); + if (ret) + return ret; + /* Software ECC calculation */ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) chip->ecc.calculate(chip, p, &ecc_calc[i]); @@ -3979,6 +4039,11 @@ static int nand_do_write_ops(struct nand_chip *chip, loff_t to, return -EINVAL; } + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, to); + if (ret) + return ret; + column = to & (mtd->writesize - 1); chipnr = (int)(to >> chip->chip_shift); @@ -4180,6 +4245,11 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, if (check_offs_len(chip, instr->addr, instr->len)) return -EINVAL; + /* Check if the region is secured */ + ret = nand_check_sec_region(chip, instr->addr); + if (ret) + return ret; + /* Grab the lock and see if the device is available */ ret = nand_get_device(chip); if (ret) @@ -4995,10 +5065,32 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np) return of_property_read_bool(np, "nand-on-flash-bbt"); } +static int of_get_nand_secure_regions(struct nand_chip *chip) +{ + struct device_node *dn = nand_get_flash_node(chip); + struct property *prop; + int length, nr_elem; + + prop = of_find_property(dn, "secure-regions", &length); + if (prop) { + nr_elem = length / sizeof(u64); + chip->nr_sec_regions = nr_elem / 2; + + chip->sec_regions = kcalloc(nr_elem, sizeof(u32), GFP_KERNEL); + if (!chip->sec_regions) + return -ENOMEM; + + of_property_read_u64_array(dn, "secure-regions", chip->sec_regions, nr_elem); + } + + return 0; +} + static int rawnand_dt_init(struct nand_chip *chip) { struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); struct device_node *dn = nand_get_flash_node(chip); + int ret; if (!dn) return 0; @@ -5015,6 +5107,16 @@ static int rawnand_dt_init(struct nand_chip *chip) of_get_nand_ecc_user_config(nand); of_get_nand_ecc_legacy_user_config(chip); + /* + * Look for secure regions in the NAND chip. These regions are supposed + * to be protected by a secure element like Trustzone. So the read/write + * accesses to these regions will be blocked in the runtime by this + * driver. + */ + ret = of_get_nand_secure_regions(chip); + if (!ret) + return ret; + /* * If neither the user nor the NAND controller have requested a specific * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. @@ -6068,6 +6170,9 @@ void nand_cleanup(struct nand_chip *chip) /* Free manufacturer priv data. */ nand_manufacturer_cleanup(chip); + /* Free secure regions data */ + kfree(chip->sec_regions); + /* Free controller specific allocations after chip identification */ nand_detach(chip); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 6b3240e44310..5ae77ecf41f3 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1086,6 +1086,8 @@ struct nand_manufacturer { * NAND Controller drivers should not modify this value, but they're * allowed to read it. * @read_retries: The number of read retry modes supported + * @sec_regions: Array representing the secure regions + * @nr_sec_regions: Number of secure regions * @controller: The hardware controller structure which is shared among multiple * independent devices * @ecc: The ECC controller structure @@ -1135,6 +1137,8 @@ struct nand_chip { unsigned int suspended : 1; int cur_cs; int read_retries; + u64 *sec_regions; + u8 nr_sec_regions; /* Externals */ struct nand_controller *controller;