From patchwork Fri Mar 19 00:52:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 404986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EDF9C433E6 for ; Fri, 19 Mar 2021 00:53:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36C4B64F24 for ; Fri, 19 Mar 2021 00:53:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233426AbhCSAxF (ORCPT ); Thu, 18 Mar 2021 20:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231892AbhCSAwr (ORCPT ); Thu, 18 Mar 2021 20:52:47 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9316FC06175F; Thu, 18 Mar 2021 17:52:46 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id w18so8914383edc.0; Thu, 18 Mar 2021 17:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Igmc9cLwjjnQbW2NQgn8XSOIxrY5hQGnjVY13RlbqSs=; b=ZuwZPySLxKfbajls8fvAx6ZxvxXLGCqrU6d0wSZyj0vi8HicNuJqERrJvFiYYkudnH orbOFHe4B4R3hIpm/S4rTBazuQg20OuI9Ac+U9noozWEk3S563a4UyQF7/fRqqMC7fUt qvNLifBraOyIMw3wWZqsX/teK5T7dmBDngOs1FpMaRqxywHgfWIjPvDus8Lnj1nCjhFi rx8Y00V/lQEQRj1VWlvWOnuRbCZpXMHAVshuDPQ+7uyzN/7ec7q3tZBQevAwlw7UveYL m6s6bmNq/I1QPF/ZssPG90JA2xAhhfQhxGhtXh2y/ZPG/PRQlkuFVrLdLGga1P2I0KGS QbRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Igmc9cLwjjnQbW2NQgn8XSOIxrY5hQGnjVY13RlbqSs=; b=aRWOSlEsm8my1EcYfkPPfbfnZZWWx1AScdR4jCzE+J/fO8+O4nJIsX9U0ZkZDy8r+r IfWnwXDuJe20E/9F4u1Ahe7r1eYsMLTPLZxx6vZPLqjgGyf0Mj8Oc4RZG/53d/UE9Mc3 5PtdJQtKw3iRtqjGhqYcLGzlANF4d02fAreXYE/xl2Y4gGg3xMH5K1ULrY4G1iJOoryG zaYi1Rb880q+fZA7hpkX8OO5v14IQ7yA/8gSriqe8dRBNEPFIe1ZDr5VYCwPfJwwAa44 BrKzYDEZ6Zj7H8mrN05JQc6n3GkQW/62XODTiihyeWVm3a5kYzknKywKAMg4NiPknDSq bzvQ== X-Gm-Message-State: AOAM531AIA/cC51vRb9kK+7O+PZPLZeN5BJB4rJjsw/ie7ncwtl4FDrH LSGpf02krxRkoaglkB2vRjU= X-Google-Smtp-Source: ABdhPJyOx/xJvbaDPN/uPN7cj/jTTvZX29GGie3BKYmg774cntnpq8LkLb/WyerU4NEAeWFKCnfW1w== X-Received: by 2002:a05:6402:2744:: with SMTP id z4mr6831334edd.347.1616115165262; Thu, 18 Mar 2021 17:52:45 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:45 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 1/9] drivers: thermal: tsens: Add VER_0 tsens version Date: Fri, 19 Mar 2021 01:52:19 +0100 Message-Id: <20210319005228.1250-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org VER_0 is used to describe device based on tsens version before v0.1. These device are devices based on msm8960 for example apq8064 or ipq806x. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 141 ++++++++++++++++++++++++++++------- drivers/thermal/qcom/tsens.h | 4 +- 2 files changed, 116 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index d8ce3a687b80..277d9b17e949 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", hw_id, __func__, temp); } + + if (tsens_version(priv) < VER_0_1) { + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + break; + } } return IRQ_HANDLED; @@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + if (tsens_version(priv) < VER_0_1) { + /* Pre v0.1 IP had a single register for each type of interrupt + * and thresholds + */ + hw_id = 0; + } + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); @@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp) u32 valid; int ret; - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; - while (!valid) { - /* Valid bit is 0 for 6 AHB clock cycles. - * At 19.2MHz, 1 AHB clock is ~60ns. - * We should enter this loop very, very rarely. - */ - ndelay(400); + /* VER_0 doesn't have VALID bit */ + if (tsens_version(priv) >= VER_0_1) { ret = regmap_field_read(priv->rf[valid_idx], &valid); if (ret) return ret; + while (!valid) { + /* Valid bit is 0 for 6 AHB clock cycles. + * At 19.2MHz, 1 AHB clock is ~60ns. + * We should enter this loop very, very rarely. + */ + ndelay(400); + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; + } } /* Valid bit is set, OK to read the temperature */ @@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; int hw_id = s->hw_id; - int last_temp = 0, ret; + int last_temp = 0, ret, trdy; + unsigned long timeout; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); - if (ret) - return ret; + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); + do { + if (tsens_version(priv) == VER_0) { + ret = regmap_field_read(priv->rf[TRDY], &trdy); + if (ret) + return ret; + if (!trdy) + continue; + } - *temp = code_to_degc(last_temp, s) * 1000; + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); + if (ret) + return ret; - return 0; + *temp = code_to_degc(last_temp, s) * 1000; + + return 0; + } while (time_before(jiffies, timeout)); + + return -ETIMEDOUT; } #ifdef CONFIG_DEBUG_FS @@ -738,19 +772,31 @@ int __init init_common(struct tsens_priv *priv) priv->tm_offset = 0x1000; } - res = platform_get_resource(op, IORESOURCE_MEM, 0); - tm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(tm_base)) { - ret = PTR_ERR(tm_base); - goto err_put_device; + if (tsens_version(priv) >= VER_0_1) { + res = platform_get_resource(op, IORESOURCE_MEM, 0); + tm_base = devm_ioremap_resource(dev, res); + if (IS_ERR(tm_base)) { + ret = PTR_ERR(tm_base); + goto err_put_device; + } + + priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); + } else { /* VER_0 share the same gcc regs using a syscon */ + struct device *parent = priv->dev->parent; + + if (parent) + priv->tm_map = syscon_node_to_regmap(parent->of_node); } - priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); - if (IS_ERR(priv->tm_map)) { + if (IS_ERR_OR_NULL(priv->tm_map)) { ret = PTR_ERR(priv->tm_map); goto err_put_device; } + /* VER_0 have only tm_map */ + if (!priv->srot_map) + priv->srot_map = priv->tm_map; + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, @@ -769,6 +815,10 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[TSENS_EN]); goto err_put_device; } + /* in VER_0 TSENS need to be explicitly enabled */ + if (tsens_version(priv) == VER_0) + regmap_field_write(priv->rf[TSENS_EN], 1); + ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; @@ -791,6 +841,20 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + priv->rf[TSENS_SW_RST] = devm_regmap_field_alloc( + dev, priv->srot_map, priv->fields[TSENS_SW_RST]); + if (IS_ERR(priv->rf[TSENS_SW_RST])) { + ret = PTR_ERR(priv->rf[TSENS_SW_RST]); + goto err_put_device; + } + + priv->rf[TRDY] = + devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]); + if (IS_ERR(priv->rf[TRDY])) { + ret = PTR_ERR(priv->rf[TRDY]); + goto err_put_device; + } + /* This loop might need changes if enum regfield_ids is reordered */ for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -806,7 +870,7 @@ int __init init_common(struct tsens_priv *priv) } } - if (priv->feat->crit_int) { + if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) { /* Loop might need changes if enum regfield_ids is reordered */ for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -844,7 +908,11 @@ int __init init_common(struct tsens_priv *priv) } spin_lock_init(&priv->ul_lock); - tsens_enable_irq(priv); + + /* VER_0 interrupt doesn't need to be enabled */ + if (tsens_version(priv) >= VER_0_1) + tsens_enable_irq(priv); + tsens_debug_init(op); err_put_device: @@ -943,10 +1011,14 @@ static int tsens_register_irq(struct tsens_priv *priv, char *irqname, if (irq == -ENXIO) ret = 0; } else { - ret = devm_request_threaded_irq(&pdev->dev, irq, - NULL, thread_fn, - IRQF_ONESHOT, - dev_name(&pdev->dev), priv); + /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */ + ret = devm_request_threaded_irq( + &pdev->dev, irq, + tsens_version(priv) == VER_0 ? thread_fn : NULL, + tsens_version(priv) == VER_0 ? NULL : thread_fn, + tsens_version(priv) == VER_0 ? IRQF_TRIGGER_RISING : + IRQF_ONESHOT, + dev_name(&pdev->dev), priv); if (ret) dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); @@ -975,6 +1047,19 @@ static int tsens_register(struct tsens_priv *priv) priv->ops->enable(priv, i); } + /* VER_0 require to set MIN and MAX THRESH + * These 2 regs are set using the: + * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C + * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C + */ + if (tsens_version(priv) < VER_0_1) { + regmap_field_write(priv->rf[CRIT_THRESH_0], + tsens_mC_to_hw(priv->sensor, 120000)); + + regmap_field_write(priv->rf[CRIT_THRESH_1], + tsens_mC_to_hw(priv->sensor, 0)); + } + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); if (ret < 0) return ret; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f40b625f897e..8e6c1fd3ccf5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,6 +13,7 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define TIMEOUT_US 100 #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 @@ -25,7 +26,8 @@ struct tsens_priv; /* IP version numbers in ascending order */ enum tsens_ver { - VER_0_1 = 0, + VER_0 = 0, + VER_0_1, VER_1_X, VER_2_X, }; From patchwork Fri Mar 19 00:52:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 404982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE356C2BB4D for ; Fri, 19 Mar 2021 00:53:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95A0964E83 for ; Fri, 19 Mar 2021 00:53:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233445AbhCSAxH (ORCPT ); Thu, 18 Mar 2021 20:53:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233295AbhCSAwt (ORCPT ); Thu, 18 Mar 2021 20:52:49 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5463C06174A; Thu, 18 Mar 2021 17:52:48 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id l18so655931edc.9; Thu, 18 Mar 2021 17:52:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XBoIInb/cFrB8GkTWJ/fkeyLJF+HUm2hVs09Cz8kxE4=; b=EK1UhSHsFArWHjfAp+AgqOkgyYE6OtzYhj1VfMAUZMx0YOPHID6+bOlNP2n/diXOpY Cs0WWBEqixjUHRH1iRueN+hApJHl0cMipwVAQBKj2RLeXrOA+b4H1vEMmmNVX3SeykFT 4E+FWJAweMLKc7v3oploca+/domRhO+Cn0mC9x2GTW5zywDqz6Wrtgae1WguB69R7h54 Uz9sW7J4Do+4hsTtopwfFTGGXnfwJg4tOljMLMOj66iJl3uwC0M6iudq5pN4dD98f2mg OAPz6iYb2DCwrMAXmPzaXdkObHrudWcsVGui2AdP/XsxHOrjCh16dOTH2Ap/91yCtcbC jzuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XBoIInb/cFrB8GkTWJ/fkeyLJF+HUm2hVs09Cz8kxE4=; b=F/Unyi0ysTJ+MEtCo9qNDy3IlUroDo6UH3YAFRheCd8x/lf+DKVBeYRhvt4Wb/KUff 7VpLPXdvMopvbF3KST3cs4rV77baJI6oUdxAqgV8EeBFNd6AHS03bAJSNt2il/7Li+ht cOxOE+U0rfnN2e9YGKq5zWKKYv39Q40xhdymYtQo7z/XsF3mHKB6kJqQOBxU8PxrD4BN 6xP/XQCuLX3GuWLnVkCFeyuSa6u3uKlk8uSDR61ySHzPgIvaW0ym6rbpA5nj6wG6UBhQ zIBAN/x6XtsIAPz7PceOEsumMGWP82bxKueblHdhkBTKpTVU7Jq97mhjIDZufY9ZBno5 D9Hg== X-Gm-Message-State: AOAM531kaHyoyDHluck+I7VnKTF9uzi8kQMB6SQS1Aq8Pz9B4CqpadnN AttTsV/aFTmGJUNzBn2u1Dw= X-Google-Smtp-Source: ABdhPJyurCARFEI8RocKMYxvZUJ3Fa6nJ6OBbclfT95CcGlrpmd8R3yFvlXeZDAZegGn2lQKhHuWyA== X-Received: by 2002:aa7:c14a:: with SMTP id r10mr6593968edp.132.1616115167397; Thu, 18 Mar 2021 17:52:47 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:47 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 2/9] drivers: thermal: tsens: Don't hardcode sensor slope Date: Fri, 19 Mar 2021 01:52:20 +0100 Message-Id: <20210319005228.1250-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Function compute_intercept_slope hardcode the sensor slope to SLOPE_DEFAULT. Change this and use the default value only if a slope is not defined. This is needed for tsens VER_0 that has a hardcoded slope table. Signed-off-by: Ansuel Smith Reviewed-by: Thara Gopinath --- drivers/thermal/qcom/tsens.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 277d9b17e949..44bce16217db 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, "%s: sensor%d - data_point1:%#x data_point2:%#x\n", __func__, i, p1[i], p2[i]); - priv->sensor[i].slope = SLOPE_DEFAULT; + if (!priv->sensor[i].slope) + priv->sensor[i].slope = SLOPE_DEFAULT; if (mode == TWO_PT_CALIB) { /* * slope (m) = adc_code2 - adc_code1 (y2 - y1)/ From patchwork Fri Mar 19 00:52:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 404985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0FB4C4321A for ; Fri, 19 Mar 2021 00:53:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A43D564F10 for ; Fri, 19 Mar 2021 00:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233460AbhCSAxI (ORCPT ); Thu, 18 Mar 2021 20:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233303AbhCSAwv (ORCPT ); Thu, 18 Mar 2021 20:52:51 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05195C06174A; Thu, 18 Mar 2021 17:52:51 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id u5so6897267ejn.8; Thu, 18 Mar 2021 17:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fu81fKlLAFW3uWu/bLxRNDUvKBG2yYeAnb3WyHS2HYs=; b=h/RqlYrd2MDFtUVengSYKmy4XEV3bZOua+KKCq9PuqAT/u5smi5tpIM+qcvg3g5GPy 9YHNilrlm7tNk36Ej+aljRHjPDRBHtiDMCvLnc2oXlu8TqdsP7jwQ004poyKiEqK8Cjs rO0f8tx/egrZhGXQBaIyx93jMZZKnHwGmyx913J7/ETqWv9aROcmbGUb91FAIV75u4zQ ct8ulvPsgAMCxe3ganLMpGt6Kg3QFLgye5repMOSWty3wkf5SNaZFI3WqpiHhAlJNZwx h2nYzHLyFVmaR6WaKrNHs1Lh18hhN++pW9JFGVRe3q2h/p8uofljaPGpvImz0oicjycL vMew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fu81fKlLAFW3uWu/bLxRNDUvKBG2yYeAnb3WyHS2HYs=; b=WNYhC84AHto3GxkzxgHNskf8xUHJ1y+MGJZWOVkrduul77PqN0iRZTQJsrrXcq1GFI XTge9O2323vg4i571gDrlmxzZgIY0FZ7CNAUKxN36F7Qzw0YiDR3Ri05W+HpmBKP5eDP KsaYfjJ8QBolkt7IJDft1e2JvmBSvyKZ+SHICxj33be4/OLwZNPzHSgid4Af/UuXlbWG SpLNVingjnyPmRu3IyQ0Gw2+YVwNpNtq8RpcdvZs3SROOfI5VEyJ1Tg4I8PUpOjdZEJf Zlnwh1gGHEm6BgA8Jz9TFJA6iDa9oUmtoGweZO9y1i+LK9Ipb6QjRoyeVK5uJanDR6Rc alVw== X-Gm-Message-State: AOAM532Pq8owigFfM+BhpCW9arvJsbhzQKYFS7mQmQmdiLo2wh5244jD T5q8/IKHuvNq+mo95wbpkeM= X-Google-Smtp-Source: ABdhPJx4lvQgiaOzL58DmNV/2jc7Xh1oCI/2kvWxdJkgrZO8hfbzfUpTpGQZ9PahwhJAazqsxq+9qA== X-Received: by 2002:a17:906:1352:: with SMTP id x18mr1395881ejb.545.1616115169733; Thu, 18 Mar 2021 17:52:49 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:49 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 3/9] drivers: thermal: tsens: Convert msm8960 to reg_field Date: Fri, 19 Mar 2021 01:52:21 +0100 Message-Id: <20210319005228.1250-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert msm9860 driver to reg_field to use the init_common function. Signed-off-by: Ansuel Smith Acked-by: Thara Gopinath --- drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2a28a5af209e..3f4fc1ffe679 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -51,11 +51,22 @@ #define MIN_LIMIT_TH 0x0 #define MAX_LIMIT_TH 0xff -#define S0_STATUS_ADDR 0x3628 #define INT_STATUS_ADDR 0x363c #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 +#define S0_STATUS_OFF 0x3628 +#define S1_STATUS_OFF 0x362c +#define S2_STATUS_OFF 0x3630 +#define S3_STATUS_OFF 0x3634 +#define S4_STATUS_OFF 0x3638 +#define S5_STATUS_OFF 0x3664 /* Sensors 5-10 found on apq8064/msm8960 */ +#define S6_STATUS_OFF 0x3668 +#define S7_STATUS_OFF 0x366c +#define S8_STATUS_OFF 0x3670 +#define S9_STATUS_OFF 0x3674 +#define S10_STATUS_OFF 0x3678 + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -269,6 +280,71 @@ static int get_temp_8960(const struct tsens_sensor *s, int *temp) return -ETIMEDOUT; } +static struct tsens_features tsens_8960_feat = { + .ver_major = VER_0, + .crit_int = 0, + .adc = 1, + .srot_split = 0, + .max_sensors = 11, +}; + +static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = { + /* ----- SROT ------ */ + /* No VERSION information */ + + /* CNTL */ + [TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0), + [TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1), + /* 8960 has 5 sensors, 8660 has 11, we only handle 5 */ + [SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7), + + /* ----- TM ------ */ + /* INTERRUPT ENABLE */ + /* NO INTERRUPT ENABLE */ + + /* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */ + [LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7), + [UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15), + /* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield + * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp + * MIN_THRESH_0 -> CRIT_THRESH_1 + * MAX_THRESH_0 -> CRIT_THRESH_0 + */ + [CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23), + [CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31), + + /* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */ + /* 1 == clear, 0 == normal operation */ + [LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9), + [UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10), + + /* NO CRITICAL INTERRUPT SUPPORT on 8960 */ + + /* Sn_STATUS */ + [LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7), + [LAST_TEMP_1] = REG_FIELD(S1_STATUS_OFF, 0, 7), + [LAST_TEMP_2] = REG_FIELD(S2_STATUS_OFF, 0, 7), + [LAST_TEMP_3] = REG_FIELD(S3_STATUS_OFF, 0, 7), + [LAST_TEMP_4] = REG_FIELD(S4_STATUS_OFF, 0, 7), + [LAST_TEMP_5] = REG_FIELD(S5_STATUS_OFF, 0, 7), + [LAST_TEMP_6] = REG_FIELD(S6_STATUS_OFF, 0, 7), + [LAST_TEMP_7] = REG_FIELD(S7_STATUS_OFF, 0, 7), + [LAST_TEMP_8] = REG_FIELD(S8_STATUS_OFF, 0, 7), + [LAST_TEMP_9] = REG_FIELD(S9_STATUS_OFF, 0, 7), + [LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0, 7), + + /* No VALID field on 8960 */ + /* TSENS_INT_STATUS bits: 1 == threshold violated */ + [MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0), + [LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1), + [UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2), + /* No CRITICAL field on 8960 */ + [MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3), + + /* TRDY: 1=ready, 0=in progress */ + [TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7), +}; + static const struct tsens_ops ops_8960 = { .init = init_8960, .calibrate = calibrate_8960, @@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 = { struct tsens_plat_data data_8960 = { .num_sensors = 11, .ops = &ops_8960, + .feat = &tsens_8960_feat, + .fields = tsens_8960_regfields, }; From patchwork Fri Mar 19 00:52:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 404983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30D1DC2BA82 for ; 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[95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:53 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 5/9] drivers: thermal: tsens: Fix bug in sensor enable for msm8960 Date: Fri, 19 Mar 2021 01:52:23 +0100 Message-Id: <20210319005228.1250-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device based on tsens VER_0 contains a hardware bug that results in some problem with sensor enablement. Sensor id 6-11 can't be enabled selectively and all of them must be enabled in one step. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 86585f439985..bdc64d4188bf 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -27,9 +27,9 @@ #define EN BIT(0) #define SW_RST BIT(1) #define SENSOR0_EN BIT(3) +#define MEASURE_PERIOD BIT(18) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) -#define MEASURE_PERIOD 1 #define SENSOR0_SHIFT 3 /* INT_STATUS_ADDR bitmasks */ @@ -126,17 +126,35 @@ static int resume_8960(struct tsens_priv *priv) static int enable_8960(struct tsens_priv *priv, int id) { int ret; - u32 reg, mask; + u32 reg, mask = BIT(id); ret = regmap_read(priv->tm_map, CNTL_ADDR, ®); if (ret) return ret; - mask = BIT(id + SENSOR0_SHIFT); + /* HARDWARE BUG: + * On platform with more than 6 sensors, all the remaining + * sensors needs to be enabled all togheder or underfined + * results are expected. (Sensor 6-7 disabled, Sensor 3 + * disabled...) In the original driver, all the sensors + * are enabled in one step hence this bug is not triggered. + */ + if (id > 5) { + mask = GENMASK(10, 6); + + /* Sensors already enabled. Skip. */ + if ((reg & mask) == mask) + return 0; + } + + mask <<= SENSOR0_SHIFT; + ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); if (ret) return ret; + reg |= MEASURE_PERIOD; + if (priv->num_sensors > 1) reg |= mask | SLP_CLK_ENA | EN; else From patchwork Fri Mar 19 00:52:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 404984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D29D9C2BA2B for ; Fri, 19 Mar 2021 00:53:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AD5C64E83 for ; Fri, 19 Mar 2021 00:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233506AbhCSAxL (ORCPT ); Thu, 18 Mar 2021 20:53:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233424AbhCSAxC (ORCPT ); Thu, 18 Mar 2021 20:53:02 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43E1EC06174A; Thu, 18 Mar 2021 17:53:02 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id l4so6898691ejc.10; Thu, 18 Mar 2021 17:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z09SdxQbYon303jwEPJnCBbmtQ7jFYsjkeWRJycNuHE=; b=NlAMVGa5F163FQ36h2ItKN9+BSqtVSK23vAXaoXgpLxiiu7alu/09Mfsw79b5QqX8d zLWrzZTW+s3yfA1SNe6lynuahIvzoTmIculqRjWBEpJlTBnCvMd9ZrXiZvKELac4vLWA L7ILrTHtJuZUNz80GvWPM8EuojVdIguEWs4WsMIFyA9GQLjbrtcu8G6s42ipvf1gTg07 XJIbMUmjV3GuqJ6NklLvq7iCntoajAdMn2k7WyJmvUCq4FI98i3gd/TFFkyHt4p2ufP9 qjM1yxVlF32/SjdpOBWnpF4pbXuLKHiTvwc96MjkOiopORmgLOe3KvUq1sQp2gGyCIBb J8uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z09SdxQbYon303jwEPJnCBbmtQ7jFYsjkeWRJycNuHE=; b=YsAggfHOfJr0mZ+l5dExS5Ji6GnKiPG/kirFqVzEGAO+DYABC0J6fyNx9dggonoODJ z1f49f1J46wmFixeDGKhxYrj+97Fi1/i23b+yxPmyfzLi1HePFiJgUA+uD9TvurJydN5 TiQLTRl1Tv4fsPW0RNedGFvT18p2PHzpwqk6frrclcxNxMugGBlS/oVPWWXcRSVlNKou rfYMsrAH1Qg/2qAJp9TfrY0sEi86nOiuZrktFbvhl9Yl3d9xqqytHhR1595+wNoQKxPD cCCA+6g7r6WhAT7RaxY1KbcflgrtL0a/hlHtsWputqXDguZQ4rMnUQxbBwSZwd8ai0RR ZsDA== X-Gm-Message-State: AOAM532pPoISMBbwqEhA15iFKtQSLoUbuvx4n+aBFfPg6x+c6xr/G/7z rOpJaMPC1ltWP3sTTdcYw2mig6kiy7s= X-Google-Smtp-Source: ABdhPJx5HKgwcm1Aa2tfroj/Wz3C9RuOYXA6qyjIQQeJuhQ0gvsxX7qbOcVwu57IbtyEK2tLUGDPag== X-Received: by 2002:a17:906:7f01:: with SMTP id d1mr1527847ejr.136.1616115180942; Thu, 18 Mar 2021 17:53:00 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:53:00 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 8/9] drivers: thermal: tsens: Add support for ipq8064-tsens Date: Fri, 19 Mar 2021 01:52:26 +0100 Message-Id: <20210319005228.1250-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for tsens present in ipq806x SoCs based on generic msm8960 tsens driver. Signed-off-by: Ansuel Smith Reviewed-by: Thara Gopinath --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 44bce16217db..1fd634f8f5d2 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -964,6 +964,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume); static const struct of_device_id tsens_table[] = { { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8960, + }, { .compatible = "qcom,msm8916-tsens", .data = &data_8916, }, {