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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id n16sm4501698ilq.71.2021.03.20.08.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:57:11 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/5] net: ipa: use configuration data for QSB settings Date: Sat, 20 Mar 2021 10:57:03 -0500 Message-Id: <20210320155707.2009962-2-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210320155707.2009962-1-elder@linaro.org> References: <20210320155707.2009962-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use the QSB configuration data in ipa_hardware_config_qsb(), rather than determining in code what values to use based on IPA version. Pass configuration data to ipa_hardware_config() so it can be passed to ipa_hardware_config_qsb(). Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 73 +++++++++++++++----------------------- 1 file changed, 28 insertions(+), 45 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index d354e3e65ec50..1ce593b46b04c 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -249,53 +249,35 @@ static void ipa_hardware_config_comp(struct ipa *ipa) iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); } -/* Configure DDR and PCIe max read/write QSB values */ -static void ipa_hardware_config_qsb(struct ipa *ipa) +/* Configure DDR and (possibly) PCIe max read/write QSB values */ +static void +ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) { - enum ipa_version version = ipa->version; - u32 max0; - u32 max1; + const struct ipa_qsb_data *data0; + const struct ipa_qsb_data *data1; u32 val; - /* QMB_0 represents DDR; QMB_1 represents PCIe */ - val = u32_encode_bits(8, GEN_QMB_0_MAX_WRITES_FMASK); - switch (version) { - case IPA_VERSION_4_2: - max1 = 0; /* PCIe not present */ - break; - case IPA_VERSION_4_5: - max1 = 8; - break; - default: - max1 = 4; - break; - } - val |= u32_encode_bits(max1, GEN_QMB_1_MAX_WRITES_FMASK); + /* assert(data->qsb_count > 0); */ + /* assert(data->qsb_count < 3); */ + + /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */ + data0 = &data->qsb_data[IPA_QSB_MASTER_DDR]; + if (data->qsb_count > 1) + data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE]; + + /* Max outstanding write accesses for QSB masters */ + val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK); + if (data->qsb_count > 1) + val |= u32_encode_bits(data1->max_writes, + GEN_QMB_1_MAX_WRITES_FMASK); iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET); - max1 = 12; - switch (version) { - case IPA_VERSION_3_5_1: - max0 = 8; - break; - case IPA_VERSION_4_0: - case IPA_VERSION_4_1: - max0 = 12; - break; - case IPA_VERSION_4_2: - max0 = 12; - max1 = 0; /* PCIe not present */ - break; - case IPA_VERSION_4_5: - max0 = 0; /* No limit (hardware maximum) */ - break; - } - val = u32_encode_bits(max0, GEN_QMB_0_MAX_READS_FMASK); - val |= u32_encode_bits(max1, GEN_QMB_1_MAX_READS_FMASK); - if (version != IPA_VERSION_3_5_1) { - /* GEN_QMB_0_MAX_READS_BEATS is 0 */ - /* GEN_QMB_1_MAX_READS_BEATS is 0 */ - } + /* Max outstanding read accesses for QSB masters */ + val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK); + /* GEN_QMB_0_MAX_READS_BEATS is 0 (IPA v4.0 and above) */ + if (data->qsb_count > 1) + val |= u32_encode_bits(data1->max_reads, + GEN_QMB_1_MAX_READS_FMASK); iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); } @@ -385,8 +367,9 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa) /** * ipa_hardware_config() - Primitive hardware initialization * @ipa: IPA pointer + * @data: IPA configuration data */ -static void ipa_hardware_config(struct ipa *ipa) +static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) { enum ipa_version version = ipa->version; u32 granularity; @@ -414,7 +397,7 @@ static void ipa_hardware_config(struct ipa *ipa) ipa_hardware_config_comp(ipa); /* Configure system bus limits */ - ipa_hardware_config_qsb(ipa); + ipa_hardware_config_qsb(ipa, data); if (version < IPA_VERSION_4_5) { /* Configure aggregation timer granularity */ @@ -610,7 +593,7 @@ static int ipa_config(struct ipa *ipa, const struct ipa_data *data) */ ipa_clock_get(ipa); - ipa_hardware_config(ipa); + ipa_hardware_config(ipa, data); ret = ipa_endpoint_config(ipa); if (ret) From patchwork Sat Mar 20 15:57:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 405449 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2267459jai; Sat, 20 Mar 2021 08:59:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjrDHMmOF8cEDbpTgT42IwEEGOiR56G7azQb/ytcCzZ5lxKK+wyEdbAuwwA8QotJrzOcBm X-Received: by 2002:aa7:da14:: with SMTP id r20mr15970233eds.181.1616255955331; Sat, 20 Mar 2021 08:59:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616255955; cv=none; d=google.com; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id n16sm4501698ilq.71.2021.03.20.08.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:57:12 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/5] net: ipa: implement MAX_READS_BEATS QSB data Date: Sat, 20 Mar 2021 10:57:04 -0500 Message-Id: <20210320155707.2009962-3-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210320155707.2009962-1-elder@linaro.org> References: <20210320155707.2009962-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Starting with IPA v4.0, a limit is placed on the number of bytes outstanding in a transaction, to reduce latency. The limit is imposed only if this value is non-zero. We don't use a non-zero value for SC7180, but newer versions of IPA do. Prepare for that by allowing a programmed value to be specified in the platform configuration data. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_data-sc7180.c | 1 + drivers/net/ipa/ipa_data.h | 2 ++ drivers/net/ipa/ipa_main.c | 10 ++++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c index 216f790b22b66..8fa10d0d9a4e7 100644 --- a/drivers/net/ipa/ipa_data-sc7180.c +++ b/drivers/net/ipa/ipa_data-sc7180.c @@ -14,6 +14,7 @@ static const struct ipa_qsb_data ipa_qsb_data[] = { [IPA_QSB_MASTER_DDR] = { .max_writes = 8, .max_reads = 12, + /* no outstanding read byte (beat) limit */ }, }; diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index d50cd5ae7714f..4162c4722c00c 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -59,10 +59,12 @@ enum ipa_qsb_master_id { * struct ipa_qsb_data - Qualcomm System Bus configuration data * @max_writes: Maximum outstanding write requests for this master * @max_reads: Maximum outstanding read requests for this master + * @max_reads_beats: Max outstanding read bytes in 8-byte "beats" (if non-zero) */ struct ipa_qsb_data { u8 max_writes; u8 max_reads; + u8 max_reads_beats; /* Not present for IPA v3.5.1 */ }; /** diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 1ce593b46b04c..64b92dfdd3f5c 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -274,10 +274,16 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) /* Max outstanding read accesses for QSB masters */ val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK); - /* GEN_QMB_0_MAX_READS_BEATS is 0 (IPA v4.0 and above) */ - if (data->qsb_count > 1) + if (ipa->version >= IPA_VERSION_4_0) + val |= u32_encode_bits(data0->max_reads_beats, + GEN_QMB_0_MAX_READS_BEATS_FMASK); + if (data->qsb_count > 1) { val |= u32_encode_bits(data1->max_reads, GEN_QMB_1_MAX_READS_FMASK); + if (ipa->version >= IPA_VERSION_4_0) + val |= u32_encode_bits(data1->max_reads_beats, + GEN_QMB_1_MAX_READS_BEATS_FMASK); + } iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); } From patchwork Sat Mar 20 15:57:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 405451 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2267482jai; Sat, 20 Mar 2021 08:59:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4imMIJlIRw+J+hBP+L8kzg3qi0QtUWzutkKBgTy3F04oG+gDV0UYhocjpngU7QDn2+rsr X-Received: by 2002:a05:6402:c8:: with SMTP id i8mr16304462edu.57.1616255956880; Sat, 20 Mar 2021 08:59:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616255956; cv=none; d=google.com; s=arc-20160816; b=YTZ0P8Z4OaBYbWFlHAz7fZrQYsr7Uel4e4qS+QFWTPDZ3eJOfp0YuFdk35nvm7AcdX Sk68vs+Aq0P35OSRSNcDxweVcV/Nbar8hsrwMv+HXq1sBBmj+g4kYjV3l5hspcUM+187 Ta8Fj2X7C2+fc7CmAzK6hMj4pebgLjJazbAGJYs380eidGnfTskzo1ivKuUSEm5mAjjp jXfPFHWv2c9LYc/Jq8HbXXDwQ2HgR9kIfC13KE+/MPwI2E9hNlt6zja8kad4/b2I/czE sQRqmnmOUva+CHuDagXGRfBeG0bjXXMRF4aTThyB3rJqSk1zy6/2bK+v3fSfVdUO6ixc LMjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kBso4vxCR9mE3vQ4KCSh4OicS8VHOel88RWScgRFJBk=; b=ToAZGpX9/oakPry6Vx7XoZTX4axNEi73Sn1TAqVmN/usdgWoEQTEvE+LldhWuBXqST SDMrvDwFGKj7ci8ZxWOY/ssYTm/NBNGNSKL9PprEYFMRTDzZ+xJE9JNd7HAPl2YYD98u EKY7KEahRJJQPDE/RNJ6eDPlJm5g3ywy30Cx9VeIPS4iESRWeJP8JuA0IW7QxiCXK68j QCGlewHtAIX3Gf1trCTSJkz0N5kF83m4bFpaKNOomy02j+LAw8+SYfJr+KSlVx92JFmx VZXwu/q3uksy/AoGDXSmwyGuXlsg+KtDaMVmGl/8HQSZyKdR/u8RuYv0JMeTA3bSDNqs 9YbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p3IHz9Qs; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id n16sm4501698ilq.71.2021.03.20.08.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:57:12 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/5] net: ipa: split sequencer type in two Date: Sat, 20 Mar 2021 10:57:05 -0500 Message-Id: <20210320155707.2009962-4-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210320155707.2009962-1-elder@linaro.org> References: <20210320155707.2009962-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org An IPA endpoint has a sequencer that must be configured based on how the endpoint is to be used. Currently the IPA code programs the sequencer type by splitting a value into four 4-bit nibbles. Doing that doesn't really add much value, and regardless, a better way of splitting the sequencer type is into two halves--the lower byte describing how normal packet processing is handled, and the next byte describing information about processing replicas. So split the sequencer type into two sub-parts: the sequencer type and the replication sequencer type. Define the values supported for the "main" sequencer type, and define the values supported for the replication part separately. In addition, the sequencer type names are quite verbose, encoding what the type includes, but also what it *excludes*. Rename the sequencer types in a way that mainly describes the number of passes that a packet takes through the IPA processing pipeline, and how many of those passes end by supplying the processed packet to the microprocessor. The result expands the supported types beyond what is required for now, but simplifies the way these are defined. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_data-sc7180.c | 8 ++++-- drivers/net/ipa/ipa_data-sdm845.c | 7 +++-- drivers/net/ipa/ipa_data.h | 6 ++-- drivers/net/ipa/ipa_endpoint.c | 13 ++++----- drivers/net/ipa/ipa_endpoint.h | 1 + drivers/net/ipa/ipa_reg.h | 48 ++++++++++++++++++++----------- 6 files changed, 51 insertions(+), 32 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c index 8fa10d0d9a4e7..fd2265d032cc8 100644 --- a/drivers/net/ipa/ipa_data-sc7180.c +++ b/drivers/net/ipa/ipa_data-sc7180.c @@ -31,7 +31,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 20, }, .endpoint = { - .seq_type = IPA_SEQ_DMA_ONLY, + .seq_type = IPA_SEQ_DMA, .config = { .resource_group = 0, .dma_mode = true, @@ -51,6 +51,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .seq_type = IPA_SEQ_INVALID, + .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 0, .aggregation = true, @@ -73,8 +74,8 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .filter_support = true, - .seq_type = - IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP, + .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, + .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, .config = { .resource_group = 0, .checksum = true, @@ -99,6 +100,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .seq_type = IPA_SEQ_INVALID, + .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 0, .checksum = true, diff --git a/drivers/net/ipa/ipa_data-sdm845.c b/drivers/net/ipa/ipa_data-sdm845.c index d9659fd22322a..7f7625cd96b0d 100644 --- a/drivers/net/ipa/ipa_data-sdm845.c +++ b/drivers/net/ipa/ipa_data-sdm845.c @@ -36,7 +36,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 20, }, .endpoint = { - .seq_type = IPA_SEQ_DMA_ONLY, + .seq_type = IPA_SEQ_DMA, .config = { .resource_group = 1, .dma_mode = true, @@ -56,6 +56,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .seq_type = IPA_SEQ_INVALID, + .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 1, .aggregation = true, @@ -78,8 +79,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .filter_support = true, - .seq_type = - IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, .config = { .resource_group = 1, .checksum = true, @@ -104,6 +104,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .seq_type = IPA_SEQ_INVALID, + .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 1, .checksum = true, diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index 4162c4722c00c..8808941f44afa 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -154,7 +154,8 @@ struct ipa_endpoint_config_data { /** * struct ipa_endpoint_data - IPA endpoint configuration data * @filter_support: whether endpoint supports filtering - * @seq_type: hardware sequencer type used for endpoint + * @seq_type: primary packet processing sequencer type + * @seq_rep_type: sequencer type for replication processing * @config: hardware configuration (see above) * * Not all endpoints support the IPA filtering capability. A filter table @@ -170,8 +171,9 @@ struct ipa_endpoint_config_data { */ struct ipa_endpoint_data { bool filter_support; - /* The next two are specified only for AP endpoints */ + /* The next three are specified only for AP endpoints */ enum ipa_seq_type seq_type; + enum ipa_seq_rep_type seq_rep_type; struct ipa_endpoint_config_data config; }; diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 7209ee3c31244..aab66bc4f2563 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -884,18 +884,16 @@ static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint) static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) { u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id); - u32 seq_type = endpoint->seq_type; u32 val = 0; if (!endpoint->toward_ipa) return; /* Register not valid for RX endpoints */ - /* Sequencer type is made up of four nibbles */ - val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK); - val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK); - /* The second two apply to replicated packets */ - val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK); - val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK); + /* Low-order byte configures primary packet processing */ + val |= u32_encode_bits(endpoint->seq_type, SEQ_TYPE_FMASK); + + /* Second byte configures replicated packet processing */ + val |= u32_encode_bits(endpoint->seq_rep_type, SEQ_REP_TYPE_FMASK); iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -1767,6 +1765,7 @@ static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name, endpoint->ipa = ipa; endpoint->ee_id = data->ee_id; endpoint->seq_type = data->endpoint.seq_type; + endpoint->seq_rep_type = data->endpoint.seq_rep_type; endpoint->channel_id = data->channel_id; endpoint->endpoint_id = data->endpoint_id; endpoint->toward_ipa = data->toward_ipa; diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h index 881ecc27bd6e3..c48f5324f83cc 100644 --- a/drivers/net/ipa/ipa_endpoint.h +++ b/drivers/net/ipa/ipa_endpoint.h @@ -47,6 +47,7 @@ enum ipa_endpoint_name { struct ipa_endpoint { struct ipa *ipa; enum ipa_seq_type seq_type; + enum ipa_seq_rep_type seq_rep_type; enum gsi_ee_id ee_id; u32 channel_id; u32 endpoint_id; diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 732e691e9aa62..a7ea11a5d2259 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -580,28 +580,42 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) /* Valid only for TX (IPA consumer) endpoints */ #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ (0x0000083c + 0x0070 * (txep)) -#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) -#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) -#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) -#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) +#define SEQ_TYPE_FMASK GENMASK(7, 0) +#define SEQ_REP_TYPE_FMASK GENMASK(15, 8) /** - * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N - * @IPA_SEQ_DMA_ONLY: only DMA is performed - * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: - * second packet processing pass + no decipher + microcontroller - * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: - * packet processing + no decipher + no uCP + HPS REP DMA parser - * @IPA_SEQ_INVALID: invalid sequencer type + * enum ipa_seq_type - HPS and DPS sequencer type * - * The values defined here are broken into 4-bit nibbles that are written - * into fields of the ENDP_INIT_SEQ registers. + * The low-order byte of the sequencer type register defines the number of + * passes a packet takes through the IPA pipeline. The last pass through can + * optionally skip the microprocessor. Deciphering is optional for all types; + * if enabled, an additional mask (two bits) is added to the type value. + * + * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are + * supported (or meaningful). */ +#define IPA_SEQ_DECIPHER 0x11 enum ipa_seq_type { - IPA_SEQ_DMA_ONLY = 0x0000, - IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, - IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, - IPA_SEQ_INVALID = 0xffff, + IPA_SEQ_DMA = 0x00, + IPA_SEQ_1_PASS = 0x02, + IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, + IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, + IPA_SEQ_2_PASS = 0x0a, + IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, + IPA_SEQ_INVALID = 0x0c, +}; + +/** + * enum ipa_seq_rep_type - replicated packet sequencer type + * + * This goes in the second byte of the endpoint sequencer type register. + * + * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are + * supported (or meaningful). + */ +enum ipa_seq_rep_type { + IPA_SEQ_REP_DMA_PARSER = 0x08, + IPA_SEQ_REP_INVALID = 0x0c, }; #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ From patchwork Sat Mar 20 15:57:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 405453 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2267491jai; Sat, 20 Mar 2021 08:59:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtBHq5wOje92Gpq7s0Tys0tq/wLcHVr3tweEvdNWf+MUUk33Ct5LQVhZYPYHDpW96pYS8U X-Received: by 2002:a05:6402:4309:: with SMTP id m9mr16768419edc.25.1616255958356; Sat, 20 Mar 2021 08:59:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616255958; cv=none; d=google.com; s=arc-20160816; b=PKnZfMkGNpgSB5dy9zrDg/I648D/h/iOKIV/Si3zRuvFloo6leHs00x4Gy8Y8FwkFV eiRneHAbH4iUt8roYKePNSfdWAAmyXF4YPJ09WaprVfH3U/vnGYeXULpTN+MofcclNlW JSFyaNs2iyP5YPbI3hY+YhMJ5yC7Axe1haSsMA+u+s7+ax7PPO82uoSFdVMZ613s9RgR 7zKF3968VsqRd0dvn15efC5zhRaSy8NlGkqf4mbXHhA5QgHMaQ+i64kX7obovrm39BW6 mtbITo1akSrvraQFh029pLuATf8HY+oJirMKQW/Buage7JEIVVWj8eRRIiOKzCNFyUT4 d+3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6UIku38z3Ht/kehA/YfFBbvS7rjr8VBg4gxX47vdPsw=; b=q+ye08Nec7DBSMTCUvES7ln0VajsokO8lalq5Je3tbCrE6qX7dbfX4CFswdrvaq2N/ fUooe/w8UNPmYTVWQLiUlfBoEWKN5TuSTFGJySEz2etRZ/FnjNMv2zE1vvvqRkM0yOBd Jd8ub4ObkV5w9gyRQX+pIAm4ICJFuEwfD2Yw3mUgR3Ga7FqXvQnHtlaSEUjTk49y9fX4 lkFWtR62m1Zsxl8zFCZcHhpnSfUy+D31KEJ6sZ5EzwI8bjNVLfsTLxkNe0VABYOeCpzj CFaiywmY7MDuCga79zz/y+maJcpDxcwGX/eUwbkGaC5B3yB4cUX3X70NwmnZQ89iAKzf uzOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iaSYtFu1; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id n16sm4501698ilq.71.2021.03.20.08.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:57:13 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net: ipa: sequencer type is for TX endpoints only Date: Sat, 20 Mar 2021 10:57:06 -0500 Message-Id: <20210320155707.2009962-5-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210320155707.2009962-1-elder@linaro.org> References: <20210320155707.2009962-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org We only program the sequencer type for TX endpoints. So move the definition of the sequencer type fields into the TX-specific portion of the endpoint configuration data. There's no need to maintain this in the IPA structure; we can extract it from the configuration data it points to in the one spot it's needed. We previously specified the sequencer type for RX endpoints with INVALID values. These are no longer needed, so get rid of them. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_data-sc7180.c | 12 +++++------- drivers/net/ipa/ipa_data-sdm845.c | 10 ++++------ drivers/net/ipa/ipa_data.h | 13 +++++-------- drivers/net/ipa/ipa_endpoint.c | 7 +++---- drivers/net/ipa/ipa_endpoint.h | 2 -- drivers/net/ipa/ipa_reg.h | 2 -- 6 files changed, 17 insertions(+), 29 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c index fd2265d032cc8..621ad15c9e67d 100644 --- a/drivers/net/ipa/ipa_data-sc7180.c +++ b/drivers/net/ipa/ipa_data-sc7180.c @@ -31,11 +31,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 20, }, .endpoint = { - .seq_type = IPA_SEQ_DMA, .config = { .resource_group = 0, .dma_mode = true, .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, }, }, }, @@ -50,8 +52,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 6, }, .endpoint = { - .seq_type = IPA_SEQ_INVALID, - .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 0, .aggregation = true, @@ -74,14 +74,14 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .filter_support = true, - .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, - .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, .config = { .resource_group = 0, .checksum = true, .qmap = true, .status_enable = true, .tx = { + .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, + .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, .status_endpoint = IPA_ENDPOINT_MODEM_AP_RX, }, @@ -99,8 +99,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 6, }, .endpoint = { - .seq_type = IPA_SEQ_INVALID, - .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 0, .checksum = true, diff --git a/drivers/net/ipa/ipa_data-sdm845.c b/drivers/net/ipa/ipa_data-sdm845.c index 7f7625cd96b0d..6b5173f474444 100644 --- a/drivers/net/ipa/ipa_data-sdm845.c +++ b/drivers/net/ipa/ipa_data-sdm845.c @@ -36,11 +36,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 20, }, .endpoint = { - .seq_type = IPA_SEQ_DMA, .config = { .resource_group = 1, .dma_mode = true, .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, }, }, }, @@ -55,8 +57,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 8, }, .endpoint = { - .seq_type = IPA_SEQ_INVALID, - .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 1, .aggregation = true, @@ -79,13 +79,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { }, .endpoint = { .filter_support = true, - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, .config = { .resource_group = 1, .checksum = true, .qmap = true, .status_enable = true, .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, .status_endpoint = IPA_ENDPOINT_MODEM_AP_RX, }, @@ -103,8 +103,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { .tlv_count = 8, }, .endpoint = { - .seq_type = IPA_SEQ_INVALID, - .seq_rep_type = IPA_SEQ_REP_INVALID, .config = { .resource_group = 1, .checksum = true, diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index 8808941f44afa..caf9b3f9577eb 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -97,12 +97,16 @@ struct gsi_channel_data { /** * struct ipa_endpoint_tx_data - configuration data for TX endpoints + * @seq_type: primary packet processing sequencer type + * @seq_rep_type: sequencer type for replication processing * @status_endpoint: endpoint to which status elements are sent * * The @status_endpoint is only valid if the endpoint's @status_enable * flag is set. */ struct ipa_endpoint_tx_data { + enum ipa_seq_type seq_type; + enum ipa_seq_rep_type seq_rep_type; enum ipa_endpoint_name status_endpoint; }; @@ -154,8 +158,6 @@ struct ipa_endpoint_config_data { /** * struct ipa_endpoint_data - IPA endpoint configuration data * @filter_support: whether endpoint supports filtering - * @seq_type: primary packet processing sequencer type - * @seq_rep_type: sequencer type for replication processing * @config: hardware configuration (see above) * * Not all endpoints support the IPA filtering capability. A filter table @@ -165,15 +167,10 @@ struct ipa_endpoint_config_data { * in the system, and indicate whether they support filtering. * * The remaining endpoint configuration data applies only to AP endpoints. - * The IPA hardware is implemented by sequencers, and the AP must program - * the type(s) of these sequencers at initialization time. The remaining - * endpoint configuration data is defined above. */ struct ipa_endpoint_data { bool filter_support; - /* The next three are specified only for AP endpoints */ - enum ipa_seq_type seq_type; - enum ipa_seq_rep_type seq_rep_type; + /* Everything else is specified only for AP endpoints */ struct ipa_endpoint_config_data config; }; diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index aab66bc4f2563..88310d3585574 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -890,10 +890,11 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) return; /* Register not valid for RX endpoints */ /* Low-order byte configures primary packet processing */ - val |= u32_encode_bits(endpoint->seq_type, SEQ_TYPE_FMASK); + val |= u32_encode_bits(endpoint->data->tx.seq_type, SEQ_TYPE_FMASK); /* Second byte configures replicated packet processing */ - val |= u32_encode_bits(endpoint->seq_rep_type, SEQ_REP_TYPE_FMASK); + val |= u32_encode_bits(endpoint->data->tx.seq_rep_type, + SEQ_REP_TYPE_FMASK); iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -1764,8 +1765,6 @@ static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name, endpoint->ipa = ipa; endpoint->ee_id = data->ee_id; - endpoint->seq_type = data->endpoint.seq_type; - endpoint->seq_rep_type = data->endpoint.seq_rep_type; endpoint->channel_id = data->channel_id; endpoint->endpoint_id = data->endpoint_id; endpoint->toward_ipa = data->toward_ipa; diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h index c48f5324f83cc..c6c55ea35394f 100644 --- a/drivers/net/ipa/ipa_endpoint.h +++ b/drivers/net/ipa/ipa_endpoint.h @@ -46,8 +46,6 @@ enum ipa_endpoint_name { */ struct ipa_endpoint { struct ipa *ipa; - enum ipa_seq_type seq_type; - enum ipa_seq_rep_type seq_rep_type; enum gsi_ee_id ee_id; u32 channel_id; u32 endpoint_id; diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index a7ea11a5d2259..36fe746575f6b 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -602,7 +602,6 @@ enum ipa_seq_type { IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, IPA_SEQ_2_PASS = 0x0a, IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, - IPA_SEQ_INVALID = 0x0c, }; /** @@ -615,7 +614,6 @@ enum ipa_seq_type { */ enum ipa_seq_rep_type { IPA_SEQ_REP_DMA_PARSER = 0x08, - IPA_SEQ_REP_INVALID = 0x0c, }; #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ From patchwork Sat Mar 20 15:57:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 405452 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2267489jai; Sat, 20 Mar 2021 08:59:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4jAIHY14dnrLB8HVwz4b/mhR3smLGSdmXV6vXqg78D75eu/d2U/1brtmeg1LKD7Z38u14 X-Received: by 2002:a05:6402:105a:: with SMTP id e26mr16103445edu.164.1616255957979; Sat, 20 Mar 2021 08:59:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616255957; cv=none; d=google.com; s=arc-20160816; b=LAlBmLNmUdCCLHtjpMTZIyh1IgNYqEDUYG+IKih6HUhMziXxMzPWWcpHiCh/Lty57S yEs9msKoU4eJSHcuWFg0expGOws0YUrETApJrkPLth2iV7LLNXSAOdN5XhlVInwnJAWF 8pss/Rk5KHGea4m8WCBbZUYZokfSVRXIVby/Hy72YGxyUSakJfQeMB0onLhAJ8/v2xBw wPSes/xgEMgKOI5EWDbqYHn1C9Low9LElbFCXCisMBjP1YgevzzYPXT/wbFHkF4AWHjB ReoXVGM9450m6++MFfNkRpp8RwpL0Og3Up7FNAFh3bQk68ud43fPNbj7iLFImuUHW5t0 RQzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dqBAhnvQZBZS9R5OnlTX21fRiOb56RVD97okeY10dMw=; b=LN9ShpB7XULzxPU8xLoH7FlXo6pSJa9VyoN0nPRcvUMkrYhfKslbJ5ALQy0xEOTegF oM1tPZmvWqh6y2Ebly3R9qF/R1JF+UXlJeQrQzrTSCLLs6vzYxHK4tic5xt1zc+3PHxs xzT9RnNyvao7PfUxZkZ1Rc69rD0wT19RjGb1ElhBa5xX7f+hjnI3LD7VyutTx/0ygohO KwZc2AoKx58oaipobYnlCubLzqKxh4CS5OuDxMepkPfJmYNXr1hgi6KOofQbCoDYXz4Z IPirM7AWrpNRsoheVMp9VGIXas9rqxQr8zGUtQbtJbAjzor9RgWYyU7wo1L1sNw5JrSo srPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=goyrhVJu; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id n16sm4501698ilq.71.2021.03.20.08.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Mar 2021 08:57:14 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/5] net: ipa: update some comments in "ipa_data.h" Date: Sat, 20 Mar 2021 10:57:07 -0500 Message-Id: <20210320155707.2009962-6-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210320155707.2009962-1-elder@linaro.org> References: <20210320155707.2009962-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Fix/expand some comments in "ipa_data.h". Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_data.h | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index caf9b3f9577eb..7816583fc14aa 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -18,8 +18,9 @@ * Boot-time configuration data is used to define the configuration of the * IPA and GSI resources to use for a given platform. This data is supplied * via the Device Tree match table, associated with a particular compatible - * string. The data defines information about resources, endpoints, and - * channels. + * string. The data defines information about how resources, endpoints and + * channels, memory, clocking and so on are allocated and used for the + * platform. * * Resources are data structures used internally by the IPA hardware. The * configuration data defines the number (or limits of the number) of various @@ -75,10 +76,10 @@ struct ipa_qsb_data { * * A GSI channel is a unidirectional means of transferring data to or * from (and through) the IPA. A GSI channel has a ring buffer made - * up of "transfer elements" (TREs) that specify individual data transfers - * or IPA immediate commands. TREs are filled by the AP, and control - * is passed to IPA hardware by writing the last written element - * into a doorbell register. + * up of "transfer ring elements" (TREs) that specify individual data + * transfers or IPA immediate commands. TREs are filled by the AP, + * and control is passed to IPA hardware by writing the last written + * element into a doorbell register. * * When data transfer commands have completed the GSI generates an * event (a structure of data) and optionally signals the AP with @@ -264,7 +265,7 @@ struct ipa_resource_data { * @imem_addr: physical address of IPA region within IMEM * @imem_size: size in bytes of IPA IMEM region * @smem_id: item identifier for IPA region within SMEM memory - * @imem_size: size in bytes of the IPA SMEM region + * @smem_size: size in bytes of the IPA SMEM region */ struct ipa_mem_data { u32 local_count; @@ -307,14 +308,14 @@ struct ipa_clock_data { * @endpoint_count: number of entries in the endpoint_data array * @endpoint_data: IPA endpoint/GSI channel data * @resource_data: IPA resource configuration data - * @mem_count: number of entries in the mem_data array - * @mem_data: IPA-local shared memory region data + * @mem_data: IPA memory region data + * @clock_data: IPA clock and interconnect data */ struct ipa_data { enum ipa_version version; - u32 qsb_count; /* # entries in qsb_data[] */ + u32 qsb_count; /* number of entries in qsb_data[] */ const struct ipa_qsb_data *qsb_data; - u32 endpoint_count; /* # entries in endpoint_data[] */ + u32 endpoint_count; /* number of entries in endpoint_data[] */ const struct ipa_gsi_endpoint_data *endpoint_data; const struct ipa_resource_data *resource_data; const struct ipa_mem_data *mem_data;