From patchwork Sun Mar 21 03:31:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiyong Tao X-Patchwork-Id: 405967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, RDNS_NONE, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (unknown [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32E6DC433E0 for ; Sun, 21 Mar 2021 03:33:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70EF1619A7 for ; Sun, 21 Mar 2021 03:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229863AbhCUDcv (ORCPT ); Sat, 20 Mar 2021 23:32:51 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:43907 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229766AbhCUDcX (ORCPT ); Sat, 20 Mar 2021 23:32:23 -0400 X-UUID: 68a4fdba93ae430aa3d84cafde72d6b8-20210321 X-UUID: 68a4fdba93ae430aa3d84cafde72d6b8-20210321 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 99678444; Sun, 21 Mar 2021 11:32:18 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 21 Mar 2021 11:31:55 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 21 Mar 2021 11:31:54 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH] pinctrl: add lock in mtk_rmw function. Date: Sun, 21 Mar 2021 11:31:50 +0800 Message-ID: <20210321033150.15380-2-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210321033150.15380-1-zhiyong.tao@mediatek.com> References: <20210321033150.15380-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: EF78D9D04B7ACC28C8390CE98C6ECE40209D1609D7CFD814B5CD4A3CF3C78F032000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org When multiple threads operate on the same register resource which include multiple pin, It will make the register resource wrong to control. So we add lock to avoid the case. Signed-off-by: Zhiyong Tao --- drivers/pinctrl/mediatek/pinctrl-moore.c | 2 ++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4 ++++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 ++ drivers/pinctrl/mediatek/pinctrl-paris.c | 2 ++ 4 files changed, 10 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 0fa7de43bc4c..f77921957f15 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -619,6 +619,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; + mutex_init(&hw->lock); + /* Copy from internal struct mtk_pin_desc to register to the core */ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), GFP_KERNEL); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 72f17f26acd8..fcf7c3eeee4a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -58,10 +58,14 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) { u32 val; + mutex_lock(&pctl->lock); + val = mtk_r32(pctl, i, reg); val &= ~mask; val |= set; mtk_w32(pctl, i, reg, val); + + mutex_unlock(&pctl->lock); } static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index e2aae285b5fc..65eac708a3b3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -251,6 +251,8 @@ struct mtk_pinctrl { struct mtk_eint *eint; struct mtk_pinctrl_group *groups; const char **grp_names; + /* lock pin's register resource to avoid multiple threads issue*/ + struct mutex lock; }; void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index da1f19288aa6..48e823f6d293 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -970,6 +970,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; + mutex_init(&hw->lock); + err = mtk_pctrl_build_state(pdev); if (err) { dev_err(&pdev->dev, "build state failed: %d\n", err);