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[45.79.69.94]) by smtp.gmail.com with ESMTPSA id z129-v6sm17482561pfb.108.2018.05.14.19.54.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 May 2018 19:54:21 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Jassi Brar , Arnd Bergmann , Olof Johansson , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Kaihua Zhong , Leo Yan Subject: [PATCH v2 1/5] arm64: dts: hi3660: Add mailbox node Date: Tue, 15 May 2018 10:53:11 +0800 Message-Id: <1526352795-6991-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> References: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kaihua Zhong Add the mailbox controller node for hi3660 platform. Signed-off-by: Kaihua Zhong Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index ec3eb8e..b9e7c91 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -274,6 +274,14 @@ #reset-cells = <2>; }; + mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = , + ; + #mbox-cells = <3>; + }; + dual_timer0: timer@fff14000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfff14000 0x0 0x1000>; From patchwork Tue May 15 02:53:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 135816 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp414305lji; Mon, 14 May 2018 19:54:53 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrSV2hVzVGgvWUoqc1yGxVj5TI73RqCko6nTCqBL2d4hU5u+sGtaQP8EF56VmzpUHjV78d+ X-Received: by 2002:a17:902:1744:: with SMTP id i62-v6mr12598477pli.267.1526352893331; Mon, 14 May 2018 19:54:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526352893; cv=none; d=google.com; s=arc-20160816; b=GBeMy0T967otshAsxGxVynmQBl+HZAlDPnqY7rUslAl4ZIBwnKedcD+2hlsWM5GCKY qK1/gBtKLhkVruZ+jO+ToebbYTOFmRmAB+UrzD/dt4Sv8K4AqnKxrKwE9CynRaG70kjP G/KD3ptIb8g6I4D0jsr+4MOfRSkVoEy9qXk7aZG8CoGEyKgtWW/EyRcuFsSqP3oI+nHK r+Eg3t5UEKYzISM2qTq3W6ZnYqZkOt1aozNz4FHhU0ODNJ5PmTSxTWtmJcQ0teEWTs1B mR0M4RoVCkJ6tuqcsujvs1DkDQyM1NxOIUeto3l/A7Dysvp/SgCjvjFkE78fvxqDE3Xo wh7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=oVVmeQejGmsCSRE6VtS51m6UKaVRcz0S5/gGvXxXyMA=; b=n73pC/VNan2I1ZMvh67mEO4DQ0Z3cF5Z45yhDdZ0URCXdcmkPlVRaa7e5jtx/iHcoG p+EaqIEElytcF5XoEmUoMOeJyP6/BM/aiaVU4/C4LHI6/hpWch/xQc4Q1s2AVmyzjjoP nJP0EvCI/TTt0fOC2OBiVcJu6autuMv/hR4b8CmRXFCvILzLArcP3XH42QcCW8xpmtV1 V7DvQ45W11NMM6tG8G8B3DB4oQ22QBr7xTfnGFbqSScFlUX6KtFDnSlOzVvWRPTTCwVQ bHampfKnG6HEkmMjAoh1eJrpl3yUvQhVuDU2AfcKppeiV0Nk00JPBZsdTrY3ZyRg2s9x +yLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EKsRBlme; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.79.69.94]) by smtp.gmail.com with ESMTPSA id z129-v6sm17482561pfb.108.2018.05.14.19.54.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 May 2018 19:54:47 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Jassi Brar , Arnd Bergmann , Olof Johansson , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Kaihua Zhong , Leo Yan Subject: [PATCH v2 2/5] arm64: dts: hi3660: Add stub clock node Date: Tue, 15 May 2018 10:53:12 +0800 Message-Id: <1526352795-6991-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> References: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kaihua Zhong Add stub clock node for hi3660 platform. Reviewed-by: Leo Yan Signed-off-by: Kaihua Zhong Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index b9e7c91..3a3bcff 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -282,6 +282,13 @@ #mbox-cells = <3>; }; + stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; + }; + dual_timer0: timer@fff14000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfff14000 0x0 0x1000>; From patchwork Tue May 15 02:53:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 135817 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp414468lji; Mon, 14 May 2018 19:55:04 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpd0Hl4U4NHlSJxqQ1wRZ6SSIkp3Zu6/ZUh21EghOWEmRUTB3FJcU+UubTX5/UAbk0Vlbm6 X-Received: by 2002:a17:902:b087:: with SMTP id p7-v6mr12419824plr.227.1526352904305; Mon, 14 May 2018 19:55:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526352904; cv=none; d=google.com; s=arc-20160816; b=u9KlXGYJKpDQD5R5F0N3PRq0vFZce/1tD5bmCyxSWNkX19Rt/oN//0RKYrtK+uZ+wy mnsIq5M/sTVKqTgV8FjGvbZc5zsWxAlKZ1duftcAN9NEnFS4CDNEYn964FzoZsahazr1 qnHohh31JBKupSn/7eQo9f/YjDn4rE03cFYFJ2VTsrjpGq9ah+pEUGpiTeD/zwAL+472 tnqupG0cWUeAnAtoh5pxfWyQgV+c4a1Xz9JXKn5HFZUqlWjIa4nd4KrHUQHFc4noMuWg GMHBqadvrgIYSlEQFNXbmtbjGKxLa4JZedP8ScwaIvS+OuwnEby3kInRiem4hTw0lNZD tD5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=eM6f+5RBONUcBLdLuAEczx07cLMcSgHu7g/S+NU8cyQ=; b=AZdDOB5Y8x8LFdtcUgq0hcZw1J/aLDBSv7gDgchad9kmZP7u4qFHRYtgHrOzCA7aue GJKrWthk/AwIkNND03RaNQyIYtSWrTRnmuQy4P2itykH0fZ1ic6crKfRXQ/YcWyO6Ylj jsNi5zXb5HS2Smfb9F30zQy/LQZpFp2phYbV/BauXUjapeMo6OEgSfbh+GGnbOkOm6Cr wJH3B4LRNxdKgKnhF5N6C1MpKxqzY8XKt8mHBfilEn/hpWCI5l69mUmxLVXJL8D7hsGj vv5J0EsvoYNZQdFJgRo9Jk/QDy7eEr5Cl7WAg6sR9Wt9Ijzrp/rAXUzcRZWWexzhA93M cVpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CmUK9oZ7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.79.69.94]) by smtp.gmail.com with ESMTPSA id z129-v6sm17482561pfb.108.2018.05.14.19.54.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 May 2018 19:54:58 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Jassi Brar , Arnd Bergmann , Olof Johansson , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Leo Yan Subject: [PATCH v2 3/5] arm64: dts: hi3660: Add CPU frequency scaling support Date: Tue, 15 May 2018 10:53:13 +0800 Message-Id: <1526352795-6991-4-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> References: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add two CPU OPP tables, one table is corresponding to one cluster, which allow CPU frequency scaling on hi3660 platforms. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 86 +++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3a3bcff..a39da09 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -62,6 +62,8 @@ next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -72,6 +74,8 @@ next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -82,6 +86,8 @@ next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -92,6 +98,8 @@ next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; + operating-points-v2 = <&cluster0_opp>; }; cpu4: cpu@100 { @@ -102,6 +110,8 @@ next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; + operating-points-v2 = <&cluster1_opp>; }; cpu5: cpu@101 { @@ -112,6 +122,8 @@ next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; + operating-points-v2 = <&cluster1_opp>; }; cpu6: cpu@102 { @@ -122,6 +134,8 @@ next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; + operating-points-v2 = <&cluster1_opp>; }; cpu7: cpu@103 { @@ -132,6 +146,8 @@ next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; + clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; + operating-points-v2 = <&cluster1_opp>; }; idle-states { @@ -174,6 +190,76 @@ }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <700000>; + clock-latency-ns = <300000>; + }; + + opp01 { + opp-hz = /bits/ 64 <999000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + + opp02 { + opp-hz = /bits/ 64 <1402000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + + opp03 { + opp-hz = /bits/ 64 <1709000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp04 { + opp-hz = /bits/ 64 <1844000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp10 { + opp-hz = /bits/ 64 <903000000>; + opp-microvolt = <700000>; + clock-latency-ns = <300000>; + }; + + opp11 { + opp-hz = /bits/ 64 <1421000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + + opp12 { + opp-hz = /bits/ 64 <1805000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + + opp13 { + opp-hz = /bits/ 64 <2112000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp14 { + opp-hz = /bits/ 64 <2362000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + }; + gic: interrupt-controller@e82b0000 { compatible = "arm,gic-400"; reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ From patchwork Tue May 15 02:53:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 135818 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp414699lji; Mon, 14 May 2018 19:55:21 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpxux/53wbmxGvVLd+1cZtbzshNLnXaGggA6kDKi3Kf7NCvLzwBEkdRne3G4hB+9ZRWQdAd X-Received: by 2002:a65:484c:: with SMTP id i12-v6mr10017859pgs.162.1526352921644; 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[45.79.69.94]) by smtp.gmail.com with ESMTPSA id z129-v6sm17482561pfb.108.2018.05.14.19.55.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 May 2018 19:55:13 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Jassi Brar , Arnd Bergmann , Olof Johansson , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Tao Wang , Leo Yan Subject: [PATCH v2 4/5] arm64: dts: hi3660: Add thermal cooling management Date: Tue, 15 May 2018 10:53:14 +0800 Message-Id: <1526352795-6991-5-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> References: <1526352795-6991-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tao Wang Add nodes and properties for thermal cooling management support. Signed-off-by: Tao Wang Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a39da09..e20edd9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "hisilicon,hi3660"; @@ -64,6 +65,8 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + dynamic-power-coefficient = <110>; }; cpu1: cpu@1 { @@ -112,6 +115,8 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; + dynamic-power-coefficient = <550>; }; cpu5: cpu@101 { @@ -1073,5 +1078,44 @@ interrupts = ; #thermal-sensor-cells = <1>; }; + + thermal-zones { + + cls0: cls0 { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <4500>; + + /* sensor ID */ + thermal-sensors = <&tsensor 1>; + + trips { + threshold: trip-point@0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + + target: trip-point@1 { + temperature = <75000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + contribution = <1024>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&target>; + contribution = <512>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; };