From patchwork Wed Mar 24 15:18:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407865 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp501854jai; Wed, 24 Mar 2021 08:19:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhwl5cUxsQDQxmOs5uGCuc4q4V67/R1XtmHwihcWA07EVBPGmHajYUbw1y0NGCmLurpfJq X-Received: by 2002:aa7:956d:0:b029:1f1:5ba6:2a58 with SMTP id x13-20020aa7956d0000b02901f15ba62a58mr3708509pfq.63.1616599160677; Wed, 24 Mar 2021 08:19:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599160; cv=none; d=google.com; s=arc-20160816; b=wlFEskzDc3cLNbYRZxXsU+CUA9QO8iGziY1inEfNhOLa9ah3CHQiaDFe8y7/sEddpn 28u5d37ZAmz0CN/LrxeLcAO16w8jVSjFm6wpgD4BCvHo+Qx8gMLMaUjNY2b6tosqpEbE 9b4Wc3iaXOeXr7sBU9O9Lx55+j0TvIWXCbntFVQgoaI/+gNv9V4CpdBVbLYyPmngpiG1 1j1MAom+7IUCZV940zAMsGAWLRnhNZi/bChtuzNuqyTnYeZJ+N6bU73VJSNGhr85+a8z 2RTKTXDGcmyT1nTWCU+MuLKBVXrM03ouscVHSSzzlFO8XBWl6CpT1ZzjN8A8tA8pHYoS SlyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=9dhBzSYBDKoEQa/4g+X1BAfk27Dp0AlOfHX5cjpTqrQ=; b=jdsrRPf/R7HNc/1kIbNIByUjLPVi4d7/X929f4EyTx1NU5RTNg/LLtCzvKgSWdZ53f O0Vw+Ct4DQ5XwSWrK+eSpJjH9xRhBkB3MSTsOsFMqexRXiZcN8TnWikfXeyMRIRQYvb/ 6bdFEcYdOztM7p68Wxdjo3AoPvQr+it6wUjj45sMGQVu3iidfHA8bOSB/HaZMkjg5td6 4hMgmn9nrvqwphamYtO29hOokwqXKdxaFapbidiniMgZyslOskTOcIXS2vmDWNvHHEku 6lv+lVpKuJl41fum3Pgk92g29RsVLmAK5C1F9tHy3Z8cy+0BesHtqycNmzAXRBhbpIz2 U9WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=umv8kGD2; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id d5si2376025pll.383.2021.03.24.08.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=umv8kGD2; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EFEF36EC69; Wed, 24 Mar 2021 15:19:12 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 381896EA1F for ; Wed, 24 Mar 2021 15:19:09 +0000 (UTC) Received: by mail-lf1-x12d.google.com with SMTP id o126so23037427lfa.0 for ; Wed, 24 Mar 2021 08:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7jEz8oihVJdadZw/hP+a4+zFOQ5LD0ulQWufz9UuUgQ=; b=umv8kGD2XAiabDM1eKGbsE+1QjsA7nf8WlZCAwm+jjA8SUY+de6PtmpOmplebBTrmK uR5yYJUbpQ1NTFSaeMDWa/4ENqtACs0W9iENlaa9EEJDeO/J/5WFR5f4qD50e3Ln/pEz AgXWxhqAONka76khzwgmVMTJbI5WoApWNS6PQyAfMlmXVRdP8M8Lku1pG6nGCKJRPWmE gPROGTT7Ka3bm0rbgD9ChWkbcHRQ+qIAdlvSqH8U1y92LguFTTBBtjlfvF98AxiO2uPk EaJVxwRRnkzO9RPmc++A4GExaAc9TSm4G7bP1OR/ZOEGgEFXlKzhXvsz/Kky3p2cWzOA QjLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7jEz8oihVJdadZw/hP+a4+zFOQ5LD0ulQWufz9UuUgQ=; b=iOJsOnl8CB/PRcLOxvXf1i+W3RqgnrdSRzJVZv6Yceb1myrnjS5pQ7zYtkZQycmS3L rUd6p5nZZpDd27h3VwHoca7tLfXvAUBxH+lnONS0FlvCew7/o1zg0MN8MqtvMF1VzsUQ vHt0hTiOcmOW1FsMUtyRXjMjaJosfsl8i4DLofF5mcymWBnGWp/mdfa78eD2QRhsIIj9 1C92IDPShPPIjGlTSCrXeLOAZvs2esEQ5yX2pNp/Q3s70HH5/8ikuGAK/i8FBrhVR1yN 9r47gds3F66cm79w0WcwAY4AYb518Kj2XK0IyRqu0x+WNjX2NMlOXZinR3vJa2yt0wKs 0yLQ== X-Gm-Message-State: AOAM53165/s99UJIsMG3U75GFeK1kfcTZZgVujeF5pQv/3ghCrXDIkV9 4+jaDd5Vc4zWK2zO971STadeEw== X-Received: by 2002:a05:6512:1192:: with SMTP id g18mr2136641lfr.408.1616599147684; Wed, 24 Mar 2021 08:19:07 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:06 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 01/28] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Date: Wed, 24 Mar 2021 18:18:19 +0300 Message-Id: <20210324151846.2774204-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, Daniel Palmer , dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Daniel Palmer Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally register fixed factor clocks for things like dividers don't need to manually unregister them on remove or if probe fails. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------ include/linux/clk-provider.h | 4 +++- 2 files changed, 36 insertions(+), 7 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 910e6e74ae90..4f7bf3929d6d 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); +static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res) +{ + clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor *)res)->hw); +} + static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, int index, - unsigned long flags, unsigned int mult, unsigned int div) + unsigned long flags, unsigned int mult, unsigned int div, + bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; @@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, struct clk_hw *hw; int ret; - fix = kmalloc(sizeof(*fix), GFP_KERNEL); + /* You can't use devm without a dev */ + if (devm && !dev) + return ERR_PTR(-EINVAL); + + if (devm) + fix = devres_alloc(devm_clk_hw_register_fixed_factor_release, + sizeof(*fix), GFP_KERNEL); + else + fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) return ERR_PTR(-ENOMEM); @@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else ret = of_clk_hw_register(np, hw); if (ret) { - kfree(fix); + if (devm) + devres_free(fix); + else + kfree(fix); hw = ERR_PTR(ret); - } + } else if (devm) + devres_add(dev, fix); return hw; } @@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, - flags, mult, div); + flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); @@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div) +{ + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, + flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); + #ifdef CONFIG_OF static const struct of_device_id set_rate_parent_matches[] = { { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" }, @@ -185,7 +212,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) flags |= CLK_SET_RATE_PARENT; hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0, - flags, mult, div); + flags, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index e4316890661a..58f6fe866ae9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); - +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); /** * struct clk_fractional_divider - adjustable fractional divider clock * From patchwork Wed Mar 24 15:18:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407863 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp501758jai; Wed, 24 Mar 2021 08:19:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzISe6lSFItmlLO2Q4Vhb0jKPIcq2HRfCCYuB+z6d7D14K9MI5qabZMruazyH3es/BYcc+H X-Received: by 2002:a63:5c07:: with SMTP id q7mr3503185pgb.52.1616599155478; Wed, 24 Mar 2021 08:19:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599155; cv=none; d=google.com; s=arc-20160816; b=CZrdEBi75GPvfxikUhFefkig08iI9XjkJw0TfsuyCPW1u1t98LnNhFGE9XcFua+HAi DjMGuzvbTf/iKBDKUtoI4dUpKxpbvPm2hJhTEhp90gGDZ5pezV6sqx+D6sbneUw7qI5d ip5QhwOIEH0SD9GSVnW7mLG7FCZGWTYUPBTofkW/7V98emheeMs0d1IwXq6zQFPN3scp X3ZZLJHLtIvKSa/5XqfEjHTsE+9jhycFFizFu3hyDtyC3yYde7I7h/tUs5wxIrh7U6H+ O6USNV1pKSctciMs8AXbux+n+OOq7Pqt4G3Kj+CmziKQwPNrYjDl+7CMeua9UzKWZrUD Cy0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=wQ8NYoh4OeanBM+lZvbjPzUJjjnKSL+j7zH1d1u08L8=; b=yIk+LC337oNU0XvcU0BA/BQo4kH76nAPJtDVfsIxTjDJEy/fQ09Z23yeGleWqPmk4q 1okFt97523CQYOLS83fm4kMPGxd5Uix/8QZ55xzcJ4bct6lRRZ/4F27/Uq8wWMxs/Rmh VAN33o1Pb7nQgBNvOPE62qWCvGZoRJ2XM73TzchCa+yO1llYbK7c5+78m/bGMScbEaEy AIlr8YPCu7e5ZI/E45uhJPTrAJRF+EPDx5mIc86IgZFiqEztdmsBY/9N0eU6jdZlL3mQ tr4MpUOGqgMOCUBVmwkP+9SlFuftXhQBgywOsTQqy2wm5alm1ZIqyek5JFhy0PMpXBCq 4G3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Ui/ozJrN"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id w1si2360165pfi.270.2021.03.24.08.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Ui/ozJrN"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24BD6EA39; Wed, 24 Mar 2021 15:19:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8959C6EA22 for ; Wed, 24 Mar 2021 15:19:10 +0000 (UTC) Received: by mail-lj1-x236.google.com with SMTP id a1so30713668ljp.2 for ; Wed, 24 Mar 2021 08:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fvhlkx4xo48Lrm5ulhQx7P9OeXo+UeYdR2FET2xIgts=; b=Ui/ozJrNvZxuonOcm0SDQcoC6WekUl443AjS6M5dIpQ2wT208WYxNbPs2Z/sk0PKBJ 112XOBtFRfuuJAD1WyN/Xkx8z7O46vaHkTLzmjzQW87nCupvS7zG/ELLfBff0qr6/F0b h45RZKolG+DtyEuiJyOgpPVz6zr/dGZFii9M9RONDjYSXDWxLbG0cu3hEs1FO6b9gr4S q6TRwksYAiGLGneTJj/D4yDiU6Bz9J4T9KgtbdEhknx7qiSGDL5QoH5DiNKCpkGL31gY PwtPpAb5BUbqEJanKcvKopJpiv7CN8e3yNF/AZ5+OOpoRMit68EDbdd2JYhziDx4opLx ce4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fvhlkx4xo48Lrm5ulhQx7P9OeXo+UeYdR2FET2xIgts=; b=UnxDg0+e4mb7bW0dwfXpQLWiGRKAnlFNSBfP0NHlg3nCy3hggJVhqJbt/gk+btyvv/ ZOJZWDpedV8dsanyPraAQDlka459Kf3j008zIEfk4k09fkde2CP2tW9G7AMZY1enEwc4 8tOpJfJJWPyeZxGErW5whehBHSK8SPQQfUXDuA18ZYoDdQuAwKEIvU8WyDVFx9lNNHzw kJQdATB9pmi5BpIzYfpLa6A2bQiytCfmCC2vGcIv3wXOg/3m6GpZg5mHRy1PR09jT9jt aCq3vRs5z5ILIK76slFn9F4XlkJwWfcVgy43kjgk7tV3kOPlvMPfnrGwBZ5Tq6aoGXHp 9LKw== X-Gm-Message-State: AOAM533FAN6nVJiX4DUkUCUGs0a/DWgrpFiRdxK7N0jBsEjubafTywhC 7wNnj/BK90ROTSidYmrNk4wmeg== X-Received: by 2002:a2e:581a:: with SMTP id m26mr2512908ljb.33.1616599149032; Wed, 24 Mar 2021 08:19:09 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:08 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 02/28] clk: mux: provide devm_clk_hw_register_mux() Date: Wed, 24 Mar 2021 18:18:20 +0300 Message-Id: <20210324151846.2774204-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add devm_clk_hw_register_mux() - devres-managed version of clk_hw_register_mux(). Signed-off-by: Dmitry Baryshkov --- drivers/clk/clk-mux.c | 35 +++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 13 +++++++++++++ 2 files changed, 48 insertions(+) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index e54e79714818..20582aae7a35 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -206,6 +207,40 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, } EXPORT_SYMBOL_GPL(__clk_hw_register_mux); +static void devm_clk_hw_release_mux(struct device *dev, void *res) +{ + clk_hw_unregister_mux(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, + const char *name, u8 num_parents, + const char * const *parent_names, + const struct clk_hw **parent_hws, + const struct clk_parent_data *parent_data, + unsigned long flags, void __iomem *reg, u8 shift, u32 mask, + u8 clk_mux_flags, u32 *table, spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, parent_hws, + parent_data, flags, reg, shift, mask, + clk_mux_flags, table, lock); + + if (!IS_ERR(hw)) { + *ptr = hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux); + struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 58f6fe866ae9..3eb15e0262f5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -868,6 +868,13 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); +struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, + const char *name, u8 num_parents, + const char * const *parent_names, + const struct clk_hw **parent_hws, + const struct clk_parent_data *parent_data, + unsigned long flags, void __iomem *reg, u8 shift, u32 mask, + u8 clk_mux_flags, u32 *table, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, @@ -902,6 +909,12 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ (parent_data), (flags), (reg), (shift), \ BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) +#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ + shift, width, clk_mux_flags, lock) \ + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ + (parent_names), NULL, NULL, (flags), (reg), \ + (shift), BIT((width)) - 1, (clk_mux_flags), \ + NULL, (lock)) int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val); From patchwork Wed Mar 24 15:18:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407864 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp501804jai; Wed, 24 Mar 2021 08:19:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEFdFqOtbcV1Q5RRlFM4z19rLrm/VZqt7Bh5izQQo3gI940ygKFNmrp3hUW0rH65KBqtdz X-Received: by 2002:a17:902:da81:b029:e5:de44:af5b with SMTP id j1-20020a170902da81b02900e5de44af5bmr4030954plx.27.1616599158087; Wed, 24 Mar 2021 08:19:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599158; cv=none; d=google.com; s=arc-20160816; b=yfu68CcAE9+yy8ukDIoeIkz0JdmFcDPdNti+gfxUaM29CXHoOXQB1Sn9kJXB9NDm4F q/S3OXydu5Kp7RmgQskaLE2rCy99hJhqn+l+Xn0UQ2BfZW6btxoJdSfDo2OsHt1TWXfL 5Y3lGETc222rEVKJUG54zIHPhGju9vizXvqt/5VVIdHkBq7gd9sGdO0E6Z/lowESAMld xigDS5LOsyD9X/C09XnT+8ge+p2KlWgekDEoqTlu5tcYQQKv3hLD6UTCFdllcSCI/CEm dRx4OeRijfxsSYE82hFgRkEj6+mfpeLO1apqynh7BX18IeZ+6/8P2ybiBmAUc5zDBFdL aWlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=SKOT36tiD63IWoJH2yc3UyGzig1CopoxFk37/pE0Mpo=; b=WrUgkaHuvbT7lSR/lrOOjZhc/zbme7LrrMW4YVinnIC95gwDOlYJTRILZVhBYWSBMd bFS8CwVjdWJyMQqtfEoHU0Cn6PovrbEik655V5Hhhq7OanR/1ZnULCngpBFwNAdUOpHA P6p6Q9LNSzMTqUFSUwbu4lfG358FgP88K6hLCaXG/ulvHXgkPOYkTDy1Nc3wP8HdcRJX 4GnUGxgj8VeF0G3qG3TYQ+dk8YjRJcnut/xdfwkCzmkMS0GquY6HarR7kvpe9/iUSvbg yDAOWMifTNUdniSArk6zhOzIjr4BzKN+YrTOi+nmql5j6Es3wT0cQfheWjw0gDK5j+sf dhRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=v97pfOc4; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id j7si2369488pfj.339.2021.03.24.08.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=v97pfOc4; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 469AD6EC1A; Wed, 24 Mar 2021 15:19:12 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE71C6EC1A for ; Wed, 24 Mar 2021 15:19:11 +0000 (UTC) Received: by mail-lj1-x236.google.com with SMTP id u20so30645294lja.13 for ; Wed, 24 Mar 2021 08:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PBXzeZeDyvQyLPoNa1KGeI/poAISjCxdb5q3SKcFJsU=; b=v97pfOc4wkHEYLNV13IKhZN4dNBeU79Lu9y2VS+lBjB12QYlkvwkgu5zYE9OCOosLl BBGF0NeD6RdbhyA4ZSLoAWj57W6+NeHbE4i9klTOV1u2ZYpSnl3jBmmAOF2jtqH+a6B5 7XIdCG37smDlqai4oAnutXmDnP5F7+xNN1t4Sqoqg61BMea2j9G+33R/V97EjyytAm4+ WTllpBHpiT/zceAldkY5KNC2sx6XJyJl8imGEpWR1Z84pSSwo4FJ3yJuGHsIjmd3RK+q hzrGdGq9n6RD9MQJKAZrDguHacli8bMQQd2tDY7UX62AbZbhdwV36Cdus3DI7C4D7ZXR +AuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PBXzeZeDyvQyLPoNa1KGeI/poAISjCxdb5q3SKcFJsU=; b=Xc3aPduSZee9Org4Rl4rEdZIAn8dJGMQxpJWvIMs/a4uZ70lF7c3ni18yDk3fEaXpj 1MU2TEzJ82iNx2W1PJ+mLPtBOXd+K3pteUKNgZl/aXYjZO5g8PO319zRjF3hC2gfpwFH /G/UsTEBaEcmo6MkzZZXGzDQJWzbc64ov9vPv4o2gn9z02uZH3mwGGcXjjTRmG5J/Lox I1RLKnyIkGTIYbEzMXz2Cv5EdoZmrW8TXH5Yjbd4zuMLwqm5D6ejYi5BAXIh11X3zY9V b60gktAzJHgglenIIyHqN+qQlim02UgOc028DSgsf63da9SW1u2w2EXcHbzmfiCMx0/N Ukvg== X-Gm-Message-State: AOAM531x3uZNIg9frvaKO87+gueFJkY8kiiif6XBwN1qIlTKzdVR+Odb vEP4l8SupHaYBjz4DXo5y/MM0w== X-Received: by 2002:a2e:7301:: with SMTP id o1mr2429148ljc.42.1616599150228; Wed, 24 Mar 2021 08:19:10 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:09 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 03/28] clk: divider: add devm_clk_hw_register_divider Date: Wed, 24 Mar 2021 18:18:21 +0300 Message-Id: <20210324151846.2774204-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by: Dmitry Baryshkov --- include/linux/clk-provider.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3eb15e0262f5..162a2e5546a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -785,6 +785,23 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, (parent_data), (flags), (reg), (shift), \ (width), (clk_divider_flags), (table), \ (lock)) +/** + * devm_clk_hw_register_divider - register a divider clock with the clock framework + * @dev: device registering this clock + * @name: name of this clock + * @parent_name: name of clock's parent + * @flags: framework-specific flags + * @reg: register address to adjust divider + * @shift: number of bits to shift the bitfield + * @width: width of the bitfield + * @clk_divider_flags: divider-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ + width, clk_divider_flags, lock) \ + __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ + NULL, (flags), (reg), (shift), (width), \ + (clk_divider_flags), NULL, (lock)) /** * devm_clk_hw_register_divider_table - register a table based divider clock * with the clock framework (devres variant) From patchwork Wed Mar 24 15:18:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407872 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502108jai; Wed, 24 Mar 2021 08:19:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4UwIJvZa/+A5gcUbSphqRaX06B49x4Z/44MvJHtOifnwbgECq28ZiTYJWr/hz/GaoPC1D X-Received: by 2002:a17:90a:9f4a:: with SMTP id q10mr4032498pjv.129.1616599179122; Wed, 24 Mar 2021 08:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599179; cv=none; d=google.com; s=arc-20160816; b=KF+/Gr+hz3RwONpILqSS8NTzztPaktiekFoyJQtC3aC3qkLZkqcOrcZm9/5LpRgx03 ipcsEt1oF94JUV3sJ/n7Ax+leXiJgwcmL6jwzNc0n9iMKOenSrRhPTF9ZbkX8/+d0sw/ Vou47WS7ZNBymWskHNtogt287FPdQsR+87+/SXZbeSOhO+7E2p7cpBSwbfkV6noWkPII Rw5dZ11kK4Nj/2nqpT/BAL2WjFB9Uf397EiFawTXaG53d+UWadYERu0qOTIfJ0DTf+oD QpTRpAUrvvKnoa9ULARjH4RWYWIwQ2bu0snpAs3xk3nicwoA+YcNzHUY/mJvKnhFBO8M mCxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=/Qf/p8ZuBo8t8jp0AcGLTePQRX61um9wKTWzLKIQQJA=; b=LNYGim/46Y6AvOySCNdscEi1N1P8voFTRBcxxyCzN8fMt31JZEitgRSJqHtC8j4xeD Y0gQDNwkvOze9I7GKXU7Mjc62rbFLzapB56vahTIyupdPtGVgK9x2v9tIwwUdKhhyhSI nVHnBKso/6J4/b9Sb5rN+i/Ai8BAWrJ9miqPxr5ptISXpW3ur/15P0Dx+fKygWd2zB4W 3knZx6h7+78wbu0wJBYl9pxjZPQcU9stOf/hNBzXeJy+hcx3ahztc5SiXeVhZvwEnEA8 UStoUJF51QSe/8Vf5kLkcfO98o1HEluVEl1D83qGd0ndXnDUyNJfn2uv1fxeAgGBY42y Mf+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="p/4IbeMb"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id hi20si2231997pjb.121.2021.03.24.08.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="p/4IbeMb"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DB676EC8B; Wed, 24 Mar 2021 15:19:27 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCB226EA22 for ; Wed, 24 Mar 2021 15:19:13 +0000 (UTC) Received: by mail-lf1-x12f.google.com with SMTP id g8so25420631lfv.12 for ; Wed, 24 Mar 2021 08:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iZKX57W7MesYRVmGUb+y9Z3mylmgwVBu68EprhTJpMw=; b=p/4IbeMbIpERsfoQZCq7x5B30xJw9U8Q4nuqQ7+0yTIztkEuCKiHUkPLXm34YTrj+e 5jmxJOpmX+gAbLo+fOTwk+zOiJSCtkSe8OdGdG9gUjtJrd+eqpWRVCiKZJVw/IzeEFJW Sk89+Th9v2KChUh7P5V60mFSwnm51saaNzyNiyPxqHR5fMTdYXG1OKQJU5o4A8qaWoF5 /f3jzFqx/w5/GslRhFw4HrEYDXIdqEtxksyz5U2V6RjC1+napdEX+ZBlel11xNgWB/Gr IZZXXM6asbWjZm88MJR1iUHZHT6Tzc1GnSPyMrxLOi8Hpxvq6WoWPXIHj3VDbqoTbodc uV+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iZKX57W7MesYRVmGUb+y9Z3mylmgwVBu68EprhTJpMw=; b=qr//JtqSx5lLYzB2y9bVNYVjFlOEveg9624dhvHlPrCEdd9WdrMam83AH9PeFyPfnl wyV/QU8t9tcWpYV3sHHe17r7D8ViWUDl2a36l5bwItBr9Vpra3xJESlPaad9oBZehFaQ KNAmGbj2WnzfxXTP3l2ztE96y9DJuj0v8CKjk8scQITUbyaOI8TB6gQsj7mSSRuOLXJO oqoYcN6CLuIMepJzwHfuh4wl9f9KMJmKnnp3jt/jCYTRUYc2bl0dISjbQKslcEVUjHdS 4eCaOMlTw24UFu5dB3K4VpSZmaM78kGOq1qBCOSfF+fHzsuEYoK720U66KB79mQDe0lF 52eA== X-Gm-Message-State: AOAM533l3dIi+gU5hDGbZCfzq922g7b3iZ10tdQ1zbvKZyJdYTZY18lR kvj9b1lQHFke9P+NqyujQZuqaA== X-Received: by 2002:ac2:4245:: with SMTP id m5mr2329842lfl.168.1616599152318; Wed, 24 Mar 2021 08:19:12 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:11 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 04/28] drm/msm/dsi: replace PHY's init callback with configurable data Date: Wed, 24 Mar 2021 18:18:22 +0300 Message-Id: <20210324151846.2774204-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane depending on the PHY type. Replace those callbacks with configuration options governing mapping those regions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 42 ++++++++----------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 19 +-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 19 +-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 +-- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 19 +-------- 8 files changed, 31 insertions(+), 82 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index e8c1a727179c..83eb0a630443 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -637,24 +637,6 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy) return -EINVAL; } -int msm_dsi_phy_init_common(struct msm_dsi_phy *phy) -{ - struct platform_device *pdev = phy->pdev; - int ret = 0; - - phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", - "DSI_PHY_REG"); - if (IS_ERR(phy->reg_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", - __func__); - ret = -ENOMEM; - goto fail; - } - -fail: - return ret; -} - static int dsi_phy_driver_probe(struct platform_device *pdev) { struct msm_dsi_phy *phy; @@ -691,6 +673,24 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + if (phy->cfg->has_phy_lane) { + phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE"); + if (IS_ERR(phy->lane_base)) { + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__); + ret = -ENOMEM; + goto fail; + } + } + + if (phy->cfg->has_phy_regulator) { + phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); + if (IS_ERR(phy->reg_base)) { + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__); + ret = -ENOMEM; + goto fail; + } + } + ret = dsi_phy_regulator_init(phy); if (ret) goto fail; @@ -702,12 +702,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } - if (phy->cfg->ops.init) { - ret = phy->cfg->ops.init(phy); - if (ret) - goto fail; - } - /* PLL init will call into clk_register which requires * register access, so we need to enable power and ahb clock. */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index d2bd74b6f357..03dfb08e7128 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -17,7 +17,6 @@ #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) struct msm_dsi_phy_ops { - int (*init) (struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, struct msm_dsi_phy_clk_request *clk_req); void (*disable)(struct msm_dsi_phy *phy); @@ -37,6 +36,8 @@ struct msm_dsi_phy_cfg { const resource_size_t io_start[DSI_MAX]; const int num_dsi_phy; const int quirks; + bool has_phy_regulator; + bool has_phy_lane; }; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; @@ -106,7 +107,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, u32 bit_mask); -int msm_dsi_phy_init_common(struct msm_dsi_phy *phy); #endif /* __DSI_PHY_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index d1b92d4dc197..655fa17a0452 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -216,24 +216,10 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) DBG("DSI%d PHY disabled", phy->id); } -static int dsi_10nm_phy_init(struct msm_dsi_phy *phy) -{ - struct platform_device *pdev = phy->pdev; - - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", - "DSI_PHY_LANE"); - if (IS_ERR(phy->lane_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", - __func__); - return -ENOMEM; - } - - return 0; -} - const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .type = MSM_DSI_PHY_10NM, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -243,7 +229,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, - .init = dsi_10nm_phy_init, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, @@ -252,6 +237,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .type = MSM_DSI_PHY_10NM, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -261,7 +247,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, - .init = dsi_10nm_phy_init, }, .io_start = { 0xc994400, 0xc996400 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 519400501bcd..6989730b5fbd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -129,24 +129,10 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) wmb(); } -static int dsi_14nm_phy_init(struct msm_dsi_phy *phy) -{ - struct platform_device *pdev = phy->pdev; - - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", - "DSI_PHY_LANE"); - if (IS_ERR(phy->lane_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", - __func__); - return -ENOMEM; - } - - return 0; -} - const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .type = MSM_DSI_PHY_14NM, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -156,7 +142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, - .init = dsi_14nm_phy_init, }, .io_start = { 0x994400, 0x996400 }, .num_dsi_phy = 2, @@ -165,6 +150,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .type = MSM_DSI_PHY_14NM, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -174,7 +160,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, - .init = dsi_14nm_phy_init, }, .io_start = { 0xc994400, 0xc996000 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index eca86bf448f7..b752636f7f21 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -127,6 +127,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { .type = MSM_DSI_PHY_20NM, .src_pll_truthtable = { {false, true}, {false, true} }, + .has_phy_regulator = true, .reg_cfg = { .num = 2, .regs = { @@ -137,7 +138,6 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { .ops = { .enable = dsi_20nm_phy_enable, .disable = dsi_20nm_phy_disable, - .init = msm_dsi_phy_init_common, }, .io_start = { 0xfd998500, 0xfd9a0500 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index c3c580cfd8b1..5bf79de0da67 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -153,6 +153,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .type = MSM_DSI_PHY_28NM_HPM, .src_pll_truthtable = { {true, true}, {false, true} }, + .has_phy_regulator = true, .reg_cfg = { .num = 1, .regs = { @@ -162,7 +163,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, - .init = msm_dsi_phy_init_common, }, .io_start = { 0xfd922b00, 0xfd923100 }, .num_dsi_phy = 2, @@ -171,6 +171,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .type = MSM_DSI_PHY_28NM_HPM, .src_pll_truthtable = { {true, true}, {false, true} }, + .has_phy_regulator = true, .reg_cfg = { .num = 1, .regs = { @@ -180,7 +181,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, - .init = msm_dsi_phy_init_common, }, .io_start = { 0x1a94400, 0x1a96400 }, .num_dsi_phy = 2, @@ -189,6 +189,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .type = MSM_DSI_PHY_28NM_LP, .src_pll_truthtable = { {true, true}, {true, true} }, + .has_phy_regulator = true, .reg_cfg = { .num = 1, .regs = { @@ -198,7 +199,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, - .init = msm_dsi_phy_init_common, }, .io_start = { 0x1a98500 }, .num_dsi_phy = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index f22583353957..5d33de27a0f4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -176,6 +176,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .type = MSM_DSI_PHY_28NM_8960, .src_pll_truthtable = { {true, true}, {false, true} }, + .has_phy_regulator = true, .reg_cfg = { .num = 1, .regs = { @@ -185,7 +186,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, - .init = msm_dsi_phy_init_common, }, .io_start = { 0x4700300, 0x5800300 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 79c034ae075d..cbfeec860e69 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -224,24 +224,10 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) DBG("DSI%d PHY disabled", phy->id); } -static int dsi_7nm_phy_init(struct msm_dsi_phy *phy) -{ - struct platform_device *pdev = phy->pdev; - - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", - "DSI_PHY_LANE"); - if (IS_ERR(phy->lane_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", - __func__); - return -ENOMEM; - } - - return 0; -} - const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .type = MSM_DSI_PHY_7NM_V4_1, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -251,7 +237,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, - .init = dsi_7nm_phy_init, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, @@ -260,6 +245,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .type = MSM_DSI_PHY_7NM, .src_pll_truthtable = { {false, false}, {true, false} }, + .has_phy_lane = true, .reg_cfg = { .num = 1, .regs = { @@ -269,7 +255,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, - .init = dsi_7nm_phy_init, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, From patchwork Wed Mar 24 15:18:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 408167 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp563015jai; Wed, 24 Mar 2021 09:39:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjwDGYhbmf/Tnw6layvNvpyUVgpnAB+J/qkQHOqqKOgefZXM5uAFcs0a0dHVBV8vOVEpG8 X-Received: by 2002:a17:90a:f2d5:: with SMTP id gt21mr4566579pjb.197.1616603971443; Wed, 24 Mar 2021 09:39:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616603971; cv=none; d=google.com; s=arc-20160816; b=hH+V9hv9f01C+pjEyyT9kgzZsT04n3q8Ss60JuvN3k3CJtUNcQpxw1vp/G+auJ4Q6r L0iD17In5zHDEfPsoyAHSWYmy+OP7dyFoV6IJ54TiI70j7NFSV6mHEn83MwIvTQmx0Od PMn1q7JDODc5YL7+AbXyNbnVLHtf4oxfOcJEj4tXehbQmMXCE/dgpZflyNbNrV6bSAcT Epc6yIySKnkt8BxgUneFIBWqldA5TVwvYTApoLcqQBlgDphYU1XGImiLtStgUB2TARYn pXImS6suBzjMSQb8h/6SGwa51odBGmvu5TJrj9EUMs4wFMNZqhQehU1NqMX62mZhBmC1 9fVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=EenrEu9lPir3XiO36VkfYY2BHu8CobxrTC29Kw6ZsIA=; b=DoY/ED4ElbgGftXGJvpd1lRWIu9ETwElsDL6WkQKpdAHSRIWPuMVAorp6TO3BQx2wA 7I/CPTqMqTTconKhiF1zNoAKI64Oh1SH5Gu66iDTvbn0v1oFnf4+rosLuh9deu8t8nIu A5mOxRSU804so/QEYKnYiQvJBqminV5vzWN/Ci/7lbr5rCB6befh5tbMCgAmWAWrTQX3 XTHm74Cghy3bn9JimU///L29vN7AQCi8uX4FiFyxEWNLent7qqrClSPtqoOxZ4NBLOj8 RtKuNu6s0qxZiKf85nGn+Fqe1wTl1sPERPdzMz2kFHSGY33d1P6bcQejZMkhelaakVFl R8Rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=vwnL8z9L; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id mm6si2366032pjb.97.2021.03.24.09.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 09:39:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=vwnL8z9L; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 624AE6EA47; Wed, 24 Mar 2021 16:39:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 283C76EC6B for ; Wed, 24 Mar 2021 15:19:17 +0000 (UTC) Received: by mail-lf1-x129.google.com with SMTP id b4so8595158lfi.6 for ; Wed, 24 Mar 2021 08:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DDL6AolkC9uAQOUXA38fBD6iXRiNsociyXDG+vvtI5E=; b=vwnL8z9LXOhAYjli7fQDP3AQoTUyffmXLEMlmcwCd6O2qRivA0/E9D3Vkyut0dsmWT u/PnlSpxfX2snYBPB1Bp2+1zqXrFiDLIYdwnIFBRD31l4mYBtbEan5Xy7aQNeNEzyCg6 JphhoS5jbHesJAdUr3mK1HEkh2jgJo6QWWE2Yi3CCoqlvlFc39XGXY6FihYyP5SOZuiN XTZe4KErxyvrKr0/dZNzJJ3s2GnDech4gWX9LHSobsnL12Pgqhzb9VMKJxJMw5j45tJN 6WyLX4LzxiGp4W2H1GjQ7yRc7A5z7/taF1ZnXoaRnC6M4EPRd4Y+khXvSoCYTAjQF2tM IW2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DDL6AolkC9uAQOUXA38fBD6iXRiNsociyXDG+vvtI5E=; b=Dt+9k/T0AjrhtHYTBhoJOf4PixJTkGQqwcWm1fLG7vLt2FEUH1oIY87gxdldF/VDp4 roGtp9AYK92TpygOVM0PVOq2ug44nMPx9MluEXKmfHlnmmK0QPLHsliDb+3hsY8OFb6W ShMA2FMkyqWmfUDrXeL7Y5qNxTclAZ68F1FlPa13S/cPgdPGGzVFcRUZYw96BKaJ6u84 7nwZLBKfuOQXBBIkV+EbTzNxFKEROJmmEv7IsKBLL1RlEwWUDWOyDxTIJQxDbn7jBLdN Zg3wCoi0sdHRzaQQ6nKe14l7Ms0RL5yPOtX5idRYtSc+HOStTyKArHmtqEGrCNkU2XD+ oJ5w== X-Gm-Message-State: AOAM530QLpELf2oxx+LHCorRO0xtBGAMtHjF14EkIw+deYBghIBspNOt 1ctH1w6qlOSB2h+PDd/Lz55iwA== X-Received: by 2002:ac2:4111:: with SMTP id b17mr2253775lfi.96.1616599154465; Wed, 24 Mar 2021 08:19:14 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:13 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 05/28] drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* code Date: Wed, 24 Mar 2021 18:18:23 +0300 Message-Id: <20210324151846.2774204-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 24 Mar 2021 16:39:29 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Each phy version is tightly coupled with the corresponding PLL code, there is no need to keep them separate. Fuse source files together in order to simplify DSI code. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Makefile | 9 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 873 +++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 1089 ++++++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 637 ++++++++++ .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 519 ++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 905 ++++++++++++++ .../gpu/drm/msm/dsi/{pll => phy}/dsi_pll.c | 0 .../gpu/drm/msm/dsi/{pll => phy}/dsi_pll.h | 0 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 881 ------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 1096 ----------------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 643 ---------- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 526 -------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 913 -------------- 13 files changed, 4024 insertions(+), 4067 deletions(-) rename drivers/gpu/drm/msm/dsi/{pll => phy}/dsi_pll.c (100%) rename drivers/gpu/drm/msm/dsi/{pll => phy}/dsi_pll.h (100%) delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c delete mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 3cc906121fb3..1be6996b80b7 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -136,13 +136,6 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o -ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) -msm-y += dsi/pll/dsi_pll.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o -msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o -msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o -msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o -endif +msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o obj-$(CONFIG_DRM_MSM) += msm.o diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 655fa17a0452..5da369b5c475 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -3,11 +3,884 @@ * Copyright (c) 2018, The Linux Foundation */ +#include +#include #include +#include "dsi_pll.h" #include "dsi_phy.h" #include "dsi.xml.h" +/* + * DSI PLL 10nm - clock diagram (eg: DSI0): + * + * dsi0_pll_out_div_clk dsi0_pll_bit_clk + * | | + * | | + * +---------+ | +----------+ | +----+ + * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk + * +---------+ | +----------+ | +----+ + * | | + * | | dsi0_pll_by_2_bit_clk + * | | | + * | | +----+ | |\ dsi0_pclk_mux + * | |--| /2 |--o--| \ | + * | | +----+ | \ | +---------+ + * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk + * |------------------------------| / +---------+ + * | +-----+ | / + * -----------| /4? |--o----------|/ + * +-----+ | | + * | |dsiclk_sel + * | + * dsi0_pll_post_out_div_clk + */ + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 19200000 + +struct dsi_pll_regs { + u32 pll_prop_gain_rate; + u32 pll_lockdet_rate; + u32 decimal_div_start; + u32 frac_div_start_low; + u32 frac_div_start_mid; + u32 frac_div_start_high; + u32 pll_clock_inverters; + u32 ssc_stepsize_low; + u32 ssc_stepsize_high; + u32 ssc_div_per_low; + u32 ssc_div_per_high; + u32 ssc_adjper_low; + u32 ssc_adjper_high; + u32 ssc_control; +}; + +struct dsi_pll_config { + u32 ref_freq; + bool div_override; + u32 output_div; + bool ignore_frac; + bool disable_prescaler; + bool enable_ssc; + bool ssc_center; + u32 dec_bits; + u32 frac_bits; + u32 lock_timer; + u32 ssc_freq; + u32 ssc_offset; + u32 ssc_adj_per; + u32 thresh_cycles; + u32 refclk_cycles; +}; + +struct pll_10nm_cached_state { + unsigned long vco_rate; + u8 bit_clk_div; + u8 pix_clk_div; + u8 pll_out_div; + u8 pll_mux; +}; + +struct dsi_pll_10nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + + void __iomem *phy_cmn_mmio; + void __iomem *mmio; + + u64 vco_ref_clk_rate; + u64 vco_current_rate; + + /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ + spinlock_t postdiv_lock; + + int vco_delay; + struct dsi_pll_config pll_configuration; + struct dsi_pll_regs reg_setup; + + /* private clocks: */ + struct clk_hw *out_div_clk_hw; + struct clk_hw *bit_clk_hw; + struct clk_hw *byte_clk_hw; + struct clk_hw *by_2_bit_clk_hw; + struct clk_hw *post_out_div_clk_hw; + struct clk_hw *pclk_mux_hw; + struct clk_hw *out_dsiclk_hw; + + /* clock-provider: */ + struct clk_hw_onecell_data *hw_data; + + struct pll_10nm_cached_state cached_state; + + enum msm_dsi_phy_usecase uc; + struct dsi_pll_10nm *slave; +}; + +#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base) + +/* + * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * mode, where the master PLL's clk_ops needs access the slave's private data + */ +static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX]; + +static void dsi_pll_setup_config(struct dsi_pll_10nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + + config->ref_freq = pll->vco_ref_clk_rate; + config->output_div = 1; + config->dec_bits = 8; + config->frac_bits = 18; + config->lock_timer = 64; + config->ssc_freq = 31500; + config->ssc_offset = 5000; + config->ssc_adj_per = 2; + config->thresh_cycles = 32; + config->refclk_cycles = 256; + + config->div_override = false; + config->ignore_frac = false; + config->disable_prescaler = false; + + config->enable_ssc = false; + config->ssc_center = 0; +} + +static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u64 fref = pll->vco_ref_clk_rate; + u64 pll_freq; + u64 divider; + u64 dec, dec_multiple; + u32 frac; + u64 multiplier; + + pll_freq = pll->vco_current_rate; + + if (config->disable_prescaler) + divider = fref; + else + divider = fref * 2; + + multiplier = 1 << config->frac_bits; + dec_multiple = div_u64(pll_freq * multiplier, divider); + dec = div_u64_rem(dec_multiple, multiplier, &frac); + + if (pll_freq <= 1900000000UL) + regs->pll_prop_gain_rate = 8; + else if (pll_freq <= 3000000000UL) + regs->pll_prop_gain_rate = 10; + else + regs->pll_prop_gain_rate = 12; + if (pll_freq < 1100000000UL) + regs->pll_clock_inverters = 8; + else + regs->pll_clock_inverters = 0; + + regs->pll_lockdet_rate = config->lock_timer; + regs->decimal_div_start = dec; + regs->frac_div_start_low = (frac & 0xff); + regs->frac_div_start_mid = (frac & 0xff00) >> 8; + regs->frac_div_start_high = (frac & 0x30000) >> 16; +} + +#define SSC_CENTER BIT(0) +#define SSC_EN BIT(1) + +static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u32 ssc_per; + u32 ssc_mod; + u64 ssc_step_size; + u64 frac; + + if (!config->enable_ssc) { + DBG("SSC not enabled\n"); + return; + } + + ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; + ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); + ssc_per -= ssc_mod; + + frac = regs->frac_div_start_low | + (regs->frac_div_start_mid << 8) | + (regs->frac_div_start_high << 16); + ssc_step_size = regs->decimal_div_start; + ssc_step_size *= (1 << config->frac_bits); + ssc_step_size += frac; + ssc_step_size *= config->ssc_offset; + ssc_step_size *= (config->ssc_adj_per + 1); + ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); + ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); + + regs->ssc_div_per_low = ssc_per & 0xFF; + regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; + regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); + regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); + regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; + regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; + + regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; + + pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", + regs->decimal_div_start, frac, config->frac_bits); + pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", + ssc_per, (u32)ssc_step_size, config->ssc_adj_per); +} + +static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) +{ + void __iomem *base = pll->mmio; + struct dsi_pll_regs *regs = &pll->reg_setup; + + if (pll->pll_configuration.enable_ssc) { + pr_debug("SSC is enabled\n"); + + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, + regs->ssc_stepsize_low); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, + regs->ssc_stepsize_high); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, + regs->ssc_div_per_low); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, + regs->ssc_div_per_high); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, + regs->ssc_adjper_low); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, + regs->ssc_adjper_high); + pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, + SSC_EN | regs->ssc_control); + } +} + +static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) +{ + void __iomem *base = pll->mmio; + + pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); + pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); + pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); + pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); + pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); + pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); + pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, + 0xba); + pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); + pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); + pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, + 0x4c); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); + pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); + pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); +} + +static void dsi_pll_commit(struct dsi_pll_10nm *pll) +{ + void __iomem *base = pll->mmio; + struct dsi_pll_regs *reg = &pll->reg_setup; + + pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); + pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, + reg->decimal_div_start); + pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, + reg->frac_div_start_low); + pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, + reg->frac_div_start_mid); + pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, + reg->frac_div_start_high); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, + reg->pll_lockdet_rate); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); + pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); + pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, + reg->pll_clock_inverters); +} + +static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate, + parent_rate); + + pll_10nm->vco_current_rate = rate; + pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + + dsi_pll_setup_config(pll_10nm); + + dsi_pll_calc_dec_frac(pll_10nm); + + dsi_pll_calc_ssc(pll_10nm); + + dsi_pll_commit(pll_10nm); + + dsi_pll_config_hzindep_reg(pll_10nm); + + dsi_pll_ssc_commit(pll_10nm); + + /* flush, ensure all register writes are done*/ + wmb(); + + return 0; +} + +static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) +{ + struct device *dev = &pll->pdev->dev; + int rc; + u32 status = 0; + u32 const delay_us = 100; + u32 const timeout_us = 5000; + + rc = readl_poll_timeout_atomic(pll->mmio + + REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE, + status, + ((status & BIT(0)) > 0), + delay_us, + timeout_us); + if (rc) + DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n", + pll->id, status); + + return rc; +} + +static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) +{ + u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + + pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); + pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + data & ~BIT(5)); + ndelay(250); +} + +static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) +{ + u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + + pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + data | BIT(5)); + pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + ndelay(250); +} + +static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) +{ + u32 data; + + data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data & ~BIT(5)); +} + +static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) +{ + u32 data; + + data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data | BIT(5)); +} + +static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct device *dev = &pll_10nm->pdev->dev; + int rc; + + dsi_pll_enable_pll_bias(pll_10nm); + if (pll_10nm->slave) + dsi_pll_enable_pll_bias(pll_10nm->slave); + + rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0); + if (rc) { + DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc); + return rc; + } + + /* Start PLL */ + pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, + 0x01); + + /* + * ensure all PLL configurations are written prior to checking + * for PLL lock. + */ + wmb(); + + /* Check for PLL lock */ + rc = dsi_pll_10nm_lock_status(pll_10nm); + if (rc) { + DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id); + goto error; + } + + pll->pll_on = true; + + dsi_pll_enable_global_clk(pll_10nm); + if (pll_10nm->slave) + dsi_pll_enable_global_clk(pll_10nm->slave); + + pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, + 0x01); + if (pll_10nm->slave) + pll_write(pll_10nm->slave->phy_cmn_mmio + + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); + +error: + return rc; +} + +static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) +{ + pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); + dsi_pll_disable_pll_bias(pll); +} + +static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + + /* + * To avoid any stray glitches while abruptly powering down the PLL + * make sure to gate the clock using the clock enable bit before + * powering down the PLL + */ + dsi_pll_disable_global_clk(pll_10nm); + pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); + dsi_pll_disable_sub(pll_10nm); + if (pll_10nm->slave) { + dsi_pll_disable_global_clk(pll_10nm->slave); + dsi_pll_disable_sub(pll_10nm->slave); + } + /* flush, ensure all register writes are done */ + wmb(); + pll->pll_on = false; +} + +static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_config *config = &pll_10nm->pll_configuration; + void __iomem *base = pll_10nm->mmio; + u64 ref_clk = pll_10nm->vco_ref_clk_rate; + u64 vco_rate = 0x0; + u64 multiplier; + u32 frac; + u32 dec; + u64 pll_freq, tmp64; + + dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); + dec &= 0xff; + + frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & + 0xff) << 8); + frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + 0x3) << 16); + + /* + * TODO: + * 1. Assumes prescaler is disabled + */ + multiplier = 1 << config->frac_bits; + pll_freq = dec * (ref_clk * 2); + tmp64 = (ref_clk * 2 * frac); + pll_freq += div_u64(tmp64, multiplier); + + vco_rate = pll_freq; + + DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", + pll_10nm->id, (unsigned long)vco_rate, dec, frac); + + return (unsigned long)vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_10nm_vco_set_rate, + .recalc_rate = dsi_pll_10nm_vco_recalc_rate, + .prepare = dsi_pll_10nm_vco_prepare, + .unprepare = dsi_pll_10nm_vco_unprepare, +}; + +/* + * PLL Callbacks + */ + +static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; + void __iomem *phy_base = pll_10nm->phy_cmn_mmio; + u32 cmn_clk_cfg0, cmn_clk_cfg1; + + cached->pll_out_div = pll_read(pll_10nm->mmio + + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + cached->pll_out_div &= 0x3; + + cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); + cached->bit_clk_div = cmn_clk_cfg0 & 0xf; + cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; + + cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + cached->pll_mux = cmn_clk_cfg1 & 0x3; + + DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", + pll_10nm->id, cached->pll_out_div, cached->bit_clk_div, + cached->pix_clk_div, cached->pll_mux); +} + +static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; + void __iomem *phy_base = pll_10nm->phy_cmn_mmio; + u32 val; + int ret; + + val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + val &= ~0x3; + val |= cached->pll_out_div; + pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); + + pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + cached->bit_clk_div | (cached->pix_clk_div << 4)); + + val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + val &= ~0x3; + val |= cached->pll_mux; + pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); + + ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); + if (ret) { + DRM_DEV_ERROR(&pll_10nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + DBG("DSI PLL%d", pll_10nm->id); + + return 0; +} + +static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, + enum msm_dsi_phy_usecase uc) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + void __iomem *base = pll_10nm->phy_cmn_mmio; + u32 data = 0x0; /* internal PLL */ + + DBG("DSI PLL%d", pll_10nm->id); + + switch (uc) { + case MSM_DSI_PHY_STANDALONE: + break; + case MSM_DSI_PHY_MASTER: + pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX]; + break; + case MSM_DSI_PHY_SLAVE: + data = 0x1; /* external PLL */ + break; + default: + return -EINVAL; + } + + /* set PLL src */ + pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); + + pll_10nm->uc = uc; + + return 0; +} + +static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; + + DBG("DSI PLL%d", pll_10nm->id); + + if (byte_clk_provider) + *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; + if (pixel_clk_provider) + *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; + + return 0; +} + +static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct device *dev = &pll_10nm->pdev->dev; + + DBG("DSI PLL%d", pll_10nm->id); + of_clk_del_provider(dev->of_node); + + clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); + clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); + clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); + clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); + clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); + clk_hw_unregister_divider(pll_10nm->bit_clk_hw); + clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); + clk_hw_unregister(&pll_10nm->base.clk_hw); +} + +/* + * The post dividers and mux clocks are created using the standard divider and + * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux + * state to follow the master PLL's divider/mux state. Therefore, we don't + * require special clock ops that also configure the slave PLL registers + */ +static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) +{ + char clk_name[32], parent[32], vco_name[32]; + char parent2[32], parent3[32], parent4[32]; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .name = vco_name, + .flags = CLK_IGNORE_UNUSED, + .ops = &clk_ops_dsi_pll_10nm_vco, + }; + struct device *dev = &pll_10nm->pdev->dev; + struct clk_hw_onecell_data *hw_data; + struct clk_hw *hw; + int ret; + + DBG("DSI%d", pll_10nm->id); + + hw_data = devm_kzalloc(dev, sizeof(*hw_data) + + NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); + pll_10nm->base.clk_hw.init = &vco_init; + + ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); + if (ret) + return ret; + + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id); + + hw = clk_hw_register_divider(dev, clk_name, + parent, CLK_SET_RATE_PARENT, + pll_10nm->mmio + + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, + 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_base_clk_hw; + } + + pll_10nm->out_div_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + + /* BIT CLK: DIV_CTRL_3_0 */ + hw = clk_hw_register_divider(dev, clk_name, parent, + CLK_SET_RATE_PARENT, + pll_10nm->phy_cmn_mmio + + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + 0, 4, CLK_DIVIDER_ONE_BASED, + &pll_10nm->postdiv_lock); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_out_div_clk_hw; + } + + pll_10nm->bit_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + + /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + CLK_SET_RATE_PARENT, 1, 8); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_bit_clk_hw; + } + + pll_10nm->byte_clk_hw = hw; + hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + 0, 1, 2); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_byte_clk_hw; + } + + pll_10nm->by_2_bit_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + 0, 1, 4); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_by_2_bit_clk_hw; + } + + pll_10nm->post_out_div_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); + + hw = clk_hw_register_mux(dev, clk_name, + ((const char *[]){ + parent, parent2, parent3, parent4 + }), 4, 0, pll_10nm->phy_cmn_mmio + + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + 0, 2, 0, NULL); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_post_out_div_clk_hw; + } + + pll_10nm->pclk_mux_hw = hw; + + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); + snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); + + /* PIX CLK DIV : DIV_CTRL_7_4*/ + hw = clk_hw_register_divider(dev, clk_name, parent, + 0, pll_10nm->phy_cmn_mmio + + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + 4, 4, CLK_DIVIDER_ONE_BASED, + &pll_10nm->postdiv_lock); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_pclk_mux_hw; + } + + pll_10nm->out_dsiclk_hw = hw; + hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; + + hw_data->num = NUM_PROVIDED_CLKS; + pll_10nm->hw_data = hw_data; + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + pll_10nm->hw_data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + goto err_dsiclk_hw; + } + + return 0; + +err_dsiclk_hw: + clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); +err_pclk_mux_hw: + clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); +err_post_out_div_clk_hw: + clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); +err_by_2_bit_clk_hw: + clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); +err_byte_clk_hw: + clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); +err_bit_clk_hw: + clk_hw_unregister_divider(pll_10nm->bit_clk_hw); +err_out_div_clk_hw: + clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); +err_base_clk_hw: + clk_hw_unregister(&pll_10nm->base.clk_hw); + + return ret; +} + +struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) +{ + struct dsi_pll_10nm *pll_10nm; + struct msm_dsi_pll *pll; + int ret; + + pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); + if (!pll_10nm) + return ERR_PTR(-ENOMEM); + + DBG("DSI PLL%d", id); + + pll_10nm->pdev = pdev; + pll_10nm->id = id; + pll_10nm_list[id] = pll_10nm; + + pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); + if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); + return ERR_PTR(-ENOMEM); + } + + pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_10nm->mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); + return ERR_PTR(-ENOMEM); + } + + spin_lock_init(&pll_10nm->postdiv_lock); + + pll = &pll_10nm->base; + pll->min_rate = 1000000000UL; + pll->max_rate = 3500000000UL; + pll->get_provider = dsi_pll_10nm_get_provider; + pll->destroy = dsi_pll_10nm_destroy; + pll->save_state = dsi_pll_10nm_save_state; + pll->restore_state = dsi_pll_10nm_restore_state; + pll->set_usecase = dsi_pll_10nm_set_usecase; + + pll_10nm->vco_delay = 1; + + ret = pll_10nm_register(pll_10nm); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + /* TODO: Remove this when we have proper display handover support */ + msm_dsi_pll_save_state(pll); + + return pll; +} + static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy) { void __iomem *base = phy->base; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 6989730b5fbd..6a63901da7a4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -3,13 +3,1102 @@ * Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +#include +#include #include #include "dsi_phy.h" +#include "dsi_pll.h" #include "dsi.xml.h" #define PHY_14NM_CKLN_IDX 4 +/* + * DSI PLL 14nm - clock diagram (eg: DSI0): + * + * dsi0n1_postdiv_clk + * | + * | + * +----+ | +----+ + * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte + * +----+ | +----+ + * | dsi0n1_postdivby2_clk + * | +----+ | + * o---| /2 |--o--|\ + * | +----+ | \ +----+ + * | | |--| n2 |-- dsi0pll + * o--------------| / +----+ + * |/ + */ + +#define POLL_MAX_READS 15 +#define POLL_TIMEOUT_US 1000 + +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 19200000 +#define VCO_MIN_RATE 1300000000UL +#define VCO_MAX_RATE 2600000000UL + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#define DSI_PLL_DEFAULT_VCO_POSTDIV 1 + +struct dsi_pll_input { + u32 fref; /* reference clk */ + u32 fdata; /* bit clock rate */ + u32 dsiclk_sel; /* Mux configuration (see diagram) */ + u32 ssc_en; /* SSC enable/disable */ + u32 ldo_en; + + /* fixed params */ + u32 refclk_dbler_en; + u32 vco_measure_time; + u32 kvco_measure_time; + u32 bandgap_timer; + u32 pll_wakeup_timer; + u32 plllock_cnt; + u32 plllock_rng; + u32 ssc_center; + u32 ssc_adj_period; + u32 ssc_spread; + u32 ssc_freq; + u32 pll_ie_trim; + u32 pll_ip_trim; + u32 pll_iptat_trim; + u32 pll_cpcset_cur; + u32 pll_cpmset_cur; + + u32 pll_icpmset; + u32 pll_icpcset; + + u32 pll_icpmset_p; + u32 pll_icpmset_m; + + u32 pll_icpcset_p; + u32 pll_icpcset_m; + + u32 pll_lpf_res1; + u32 pll_lpf_cap1; + u32 pll_lpf_cap2; + u32 pll_c3ctrl; + u32 pll_r3ctrl; +}; + +struct dsi_pll_output { + u32 pll_txclk_en; + u32 dec_start; + u32 div_frac_start; + u32 ssc_period; + u32 ssc_step_size; + u32 plllock_cmp; + u32 pll_vco_div_ref; + u32 pll_vco_count; + u32 pll_kvco_div_ref; + u32 pll_kvco_count; + u32 pll_misc1; + u32 pll_lpf2_postdiv; + u32 pll_resetsm_cntrl; + u32 pll_resetsm_cntrl2; + u32 pll_resetsm_cntrl5; + u32 pll_kvco_code; + + u32 cmn_clk_cfg0; + u32 cmn_clk_cfg1; + u32 cmn_ldo_cntrl; + + u32 pll_postdiv; + u32 fcvo; +}; + +struct pll_14nm_cached_state { + unsigned long vco_rate; + u8 n2postdiv; + u8 n1postdiv; +}; + +struct dsi_pll_14nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + + void __iomem *phy_cmn_mmio; + void __iomem *mmio; + + int vco_delay; + + struct dsi_pll_input in; + struct dsi_pll_output out; + + /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ + spinlock_t postdiv_lock; + + u64 vco_current_rate; + u64 vco_ref_clk_rate; + + /* private clocks: */ + struct clk_hw *hws[NUM_DSI_CLOCKS_MAX]; + u32 num_hws; + + /* clock-provider: */ + struct clk_hw_onecell_data *hw_data; + + struct pll_14nm_cached_state cached_state; + + enum msm_dsi_phy_usecase uc; + struct dsi_pll_14nm *slave; +}; + +#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base) + +/* + * Private struct for N1/N2 post-divider clocks. These clocks are similar to + * the generic clk_divider class of clocks. The only difference is that it + * also sets the slave DSI PLL's post-dividers if in Dual DSI mode + */ +struct dsi_pll_14nm_postdiv { + struct clk_hw hw; + + /* divider params */ + u8 shift; + u8 width; + u8 flags; /* same flags as used by clk_divider struct */ + + struct dsi_pll_14nm *pll; +}; + +#define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) + +/* + * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * mode, where the master PLL's clk_ops needs access the slave's private data + */ +static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; + +static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, + u32 nb_tries, u32 timeout_us) +{ + bool pll_locked = false; + void __iomem *base = pll_14nm->mmio; + u32 tries, val; + + tries = nb_tries; + while (tries--) { + val = pll_read(base + + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); + pll_locked = !!(val & BIT(5)); + + if (pll_locked) + break; + + udelay(timeout_us); + } + + if (!pll_locked) { + tries = nb_tries; + while (tries--) { + val = pll_read(base + + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); + pll_locked = !!(val & BIT(0)); + + if (pll_locked) + break; + + udelay(timeout_us); + } + } + + DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); + + return pll_locked; +} + +static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) +{ + pll->in.fref = pll->vco_ref_clk_rate; + pll->in.fdata = 0; + pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ + pll->in.ldo_en = 0; /* disabled for now */ + + /* fixed input */ + pll->in.refclk_dbler_en = 0; + pll->in.vco_measure_time = 5; + pll->in.kvco_measure_time = 5; + pll->in.bandgap_timer = 4; + pll->in.pll_wakeup_timer = 5; + pll->in.plllock_cnt = 1; + pll->in.plllock_rng = 0; + + /* + * SSC is enabled by default. We might need DT props for configuring + * some SSC params like PPM and center/down spread etc. + */ + pll->in.ssc_en = 1; + pll->in.ssc_center = 0; /* down spread by default */ + pll->in.ssc_spread = 5; /* PPM / 1000 */ + pll->in.ssc_freq = 31500; /* default recommended */ + pll->in.ssc_adj_period = 37; + + pll->in.pll_ie_trim = 4; + pll->in.pll_ip_trim = 4; + pll->in.pll_cpcset_cur = 1; + pll->in.pll_cpmset_cur = 1; + pll->in.pll_icpmset = 4; + pll->in.pll_icpcset = 4; + pll->in.pll_icpmset_p = 0; + pll->in.pll_icpmset_m = 0; + pll->in.pll_icpcset_p = 0; + pll->in.pll_icpcset_m = 0; + pll->in.pll_lpf_res1 = 3; + pll->in.pll_lpf_cap1 = 11; + pll->in.pll_lpf_cap2 = 1; + pll->in.pll_iptat_trim = 7; + pll->in.pll_c3ctrl = 2; + pll->in.pll_r3ctrl = 1; +} + +#define CEIL(x, y) (((x) + ((y) - 1)) / (y)) + +static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) +{ + u32 period, ssc_period; + u32 ref, rem; + u64 step_size; + + DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate); + + ssc_period = pll->in.ssc_freq / 500; + period = (u32)pll->vco_ref_clk_rate / 1000; + ssc_period = CEIL(period, ssc_period); + ssc_period -= 1; + pll->out.ssc_period = ssc_period; + + DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq, + pll->in.ssc_spread, pll->out.ssc_period); + + step_size = (u32)pll->vco_current_rate; + ref = pll->vco_ref_clk_rate; + ref /= 1000; + step_size = div_u64(step_size, ref); + step_size <<= 20; + step_size = div_u64(step_size, 1000); + step_size *= pll->in.ssc_spread; + step_size = div_u64(step_size, 1000); + step_size *= (pll->in.ssc_adj_period + 1); + + rem = 0; + step_size = div_u64_rem(step_size, ssc_period + 1, &rem); + if (rem) + step_size++; + + DBG("step_size=%lld", step_size); + + step_size &= 0x0ffff; /* take lower 16 bits */ + + pll->out.ssc_step_size = step_size; +} + +static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) +{ + struct dsi_pll_input *pin = &pll->in; + struct dsi_pll_output *pout = &pll->out; + u64 multiplier = BIT(20); + u64 dec_start_multiple, dec_start, pll_comp_val; + u32 duration, div_frac_start; + u64 vco_clk_rate = pll->vco_current_rate; + u64 fref = pll->vco_ref_clk_rate; + + DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); + + dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); + div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); + + dec_start = div_u64(dec_start_multiple, multiplier); + + pout->dec_start = (u32)dec_start; + pout->div_frac_start = div_frac_start; + + if (pin->plllock_cnt == 0) + duration = 1024; + else if (pin->plllock_cnt == 1) + duration = 256; + else if (pin->plllock_cnt == 2) + duration = 128; + else + duration = 32; + + pll_comp_val = duration * dec_start_multiple; + pll_comp_val = div_u64(pll_comp_val, multiplier); + do_div(pll_comp_val, 10); + + pout->plllock_cmp = (u32)pll_comp_val; + + pout->pll_txclk_en = 1; + pout->cmn_ldo_cntrl = 0x3c; +} + +static u32 pll_14nm_kvco_slop(u32 vrate) +{ + u32 slop = 0; + + if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL) + slop = 600; + else if (vrate > 1800000000UL && vrate < 2300000000UL) + slop = 400; + else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE) + slop = 280; + + return slop; +} + +static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) +{ + struct dsi_pll_input *pin = &pll->in; + struct dsi_pll_output *pout = &pll->out; + u64 vco_clk_rate = pll->vco_current_rate; + u64 fref = pll->vco_ref_clk_rate; + u64 data; + u32 cnt; + + data = fref * pin->vco_measure_time; + do_div(data, 1000000); + data &= 0x03ff; /* 10 bits */ + data -= 2; + pout->pll_vco_div_ref = data; + + data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ + data *= pin->vco_measure_time; + do_div(data, 10); + pout->pll_vco_count = data; + + data = fref * pin->kvco_measure_time; + do_div(data, 1000000); + data &= 0x03ff; /* 10 bits */ + data -= 1; + pout->pll_kvco_div_ref = data; + + cnt = pll_14nm_kvco_slop(vco_clk_rate); + cnt *= 2; + cnt /= 100; + cnt *= pin->kvco_measure_time; + pout->pll_kvco_count = cnt; + + pout->pll_misc1 = 16; + pout->pll_resetsm_cntrl = 48; + pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3; + pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer; + pout->pll_kvco_code = 0; +} + +static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) +{ + void __iomem *base = pll->mmio; + struct dsi_pll_input *pin = &pll->in; + struct dsi_pll_output *pout = &pll->out; + u8 data; + + data = pin->ssc_adj_period; + data &= 0x0ff; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); + data = (pin->ssc_adj_period >> 8); + data &= 0x03; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); + + data = pout->ssc_period; + data &= 0x0ff; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); + data = (pout->ssc_period >> 8); + data &= 0x0ff; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); + + data = pout->ssc_step_size; + data &= 0x0ff; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); + data = (pout->ssc_step_size >> 8); + data &= 0x0ff; + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); + + data = (pin->ssc_center & 0x01); + data <<= 1; + data |= 0x01; /* enable */ + pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); + + wmb(); /* make sure register committed */ +} + +static void pll_db_commit_common(struct dsi_pll_14nm *pll, + struct dsi_pll_input *pin, + struct dsi_pll_output *pout) +{ + void __iomem *base = pll->mmio; + u8 data; + + /* confgiure the non frequency dependent pll registers */ + data = 0; + pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); + + data = pout->pll_txclk_en; + pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); + + data = pout->pll_resetsm_cntrl; + pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); + data = pout->pll_resetsm_cntrl2; + pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); + data = pout->pll_resetsm_cntrl5; + pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); + + data = pout->pll_vco_div_ref & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); + data = (pout->pll_vco_div_ref >> 8) & 0x3; + pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); + + data = pout->pll_kvco_div_ref & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); + data = (pout->pll_kvco_div_ref >> 8) & 0x3; + pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); + + data = pout->pll_misc1; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); + + data = pin->pll_ie_trim; + pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); + + data = pin->pll_ip_trim; + pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); + + data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur; + pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); + + data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); + + data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); + + data = pin->pll_icpmset << 3 | pin->pll_icpcset; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); + + data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); + + data = pin->pll_iptat_trim; + pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); + + data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); +} + +static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) +{ + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + + /* de assert pll start and apply pll sw reset */ + + /* stop pll */ + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + + /* pll sw reset */ + pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); + wmb(); /* make sure register committed */ + + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); + wmb(); /* make sure register committed */ +} + +static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, + struct dsi_pll_input *pin, + struct dsi_pll_output *pout) +{ + void __iomem *base = pll->mmio; + void __iomem *cmn_base = pll->phy_cmn_mmio; + u8 data; + + DBG("DSI%d PLL", pll->id); + + data = pout->cmn_ldo_cntrl; + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); + + pll_db_commit_common(pll, pin, pout); + + pll_14nm_software_reset(pll); + + data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */ + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); + + data = 0xff; /* data, clk, pll normal operation */ + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); + + /* configure the frequency dependent pll registers */ + data = pout->dec_start; + pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); + + data = pout->div_frac_start & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); + data = (pout->div_frac_start >> 8) & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); + data = (pout->div_frac_start >> 16) & 0xf; + pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); + + data = pout->plllock_cmp & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); + + data = (pout->plllock_cmp >> 8) & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); + + data = (pout->plllock_cmp >> 16) & 0x3; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); + + data = pin->plllock_cnt << 1 | pin->plllock_rng << 3; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); + + data = pout->pll_vco_count & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); + data = (pout->pll_vco_count >> 8) & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); + + data = pout->pll_kvco_count & 0xff; + pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); + data = (pout->pll_kvco_count >> 8) & 0x3; + pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); + + data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1; + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); + + if (pin->ssc_en) + pll_db_commit_ssc(pll); + + wmb(); /* make sure register committed */ +} + +/* + * VCO clock Callbacks + */ +static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_input *pin = &pll_14nm->in; + struct dsi_pll_output *pout = &pll_14nm->out; + + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate, + parent_rate); + + pll_14nm->vco_current_rate = rate; + pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + + dsi_pll_14nm_input_init(pll_14nm); + + /* + * This configures the post divider internal to the VCO. It's + * fixed to divide by 1 for now. + * + * tx_band = pll_postdiv. + * 0: divided by 1 + * 1: divided by 2 + * 2: divided by 4 + * 3: divided by 8 + */ + pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV; + + pll_14nm_dec_frac_calc(pll_14nm); + + if (pin->ssc_en) + pll_14nm_ssc_calc(pll_14nm); + + pll_14nm_calc_vco_count(pll_14nm); + + /* commit the slave DSI PLL registers if we're master. Note that we + * don't lock the slave PLL. We just ensure that the PLL/PHY registers + * of the master and slave are identical + */ + if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; + + pll_db_commit_14nm(pll_14nm_slave, pin, pout); + } + + pll_db_commit_14nm(pll_14nm, pin, pout); + + return 0; +} + +static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *base = pll_14nm->mmio; + u64 vco_rate, multiplier = BIT(20); + u32 div_frac_start; + u32 dec_start; + u64 ref_clk = parent_rate; + + dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); + dec_start &= 0x0ff; + + DBG("dec_start = %x", dec_start); + + div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) + & 0xf) << 16; + div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) + & 0xff) << 8; + div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) + & 0xff; + + DBG("div_frac_start = %x", div_frac_start); + + vco_rate = ref_clk * dec_start; + + vco_rate += ((ref_clk * div_frac_start) / multiplier); + + /* + * Recalculating the rate from dec_start and frac_start doesn't end up + * the rate we originally set. Convert the freq to KHz, round it up and + * convert it back to MHz. + */ + vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000; + + DBG("returning vco rate = %lu", (unsigned long)vco_rate); + + return (unsigned long)vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_14nm_vco_set_rate, + .recalc_rate = dsi_pll_14nm_vco_recalc_rate, + .prepare = msm_dsi_pll_helper_clk_prepare, + .unprepare = msm_dsi_pll_helper_clk_unprepare, +}; + +/* + * N1 and N2 post-divider clock callbacks + */ +#define div_mask(width) ((1 << (width)) - 1) +static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); + struct dsi_pll_14nm *pll_14nm = postdiv->pll; + void __iomem *base = pll_14nm->phy_cmn_mmio; + u8 shift = postdiv->shift; + u8 width = postdiv->width; + u32 val; + + DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate); + + val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; + val &= div_mask(width); + + return divider_recalc_rate(hw, parent_rate, val, NULL, + postdiv->flags, width); +} + +static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); + struct dsi_pll_14nm *pll_14nm = postdiv->pll; + + DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate); + + return divider_round_rate(hw, rate, prate, NULL, + postdiv->width, + postdiv->flags); +} + +static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); + struct dsi_pll_14nm *pll_14nm = postdiv->pll; + void __iomem *base = pll_14nm->phy_cmn_mmio; + spinlock_t *lock = &pll_14nm->postdiv_lock; + u8 shift = postdiv->shift; + u8 width = postdiv->width; + unsigned int value; + unsigned long flags = 0; + u32 val; + + DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate, + parent_rate); + + value = divider_get_val(rate, parent_rate, NULL, postdiv->width, + postdiv->flags); + + spin_lock_irqsave(lock, flags); + + val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + val &= ~(div_mask(width) << shift); + + val |= value << shift; + pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + + /* If we're master in dual DSI mode, then the slave PLL's post-dividers + * follow the master's post dividers + */ + if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; + void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; + + pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + } + + spin_unlock_irqrestore(lock, flags); + + return 0; +} + +static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { + .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, + .round_rate = dsi_pll_14nm_postdiv_round_rate, + .set_rate = dsi_pll_14nm_postdiv_set_rate, +}; + +/* + * PLL Callbacks + */ + +static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *base = pll_14nm->mmio; + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + bool locked; + + DBG(""); + + pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); + + locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, + POLL_TIMEOUT_US); + + if (unlikely(!locked)) + DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL lock success"); + + return locked ? 0 : -EINVAL; +} + +static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + + DBG(""); + + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); +} + +static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + u32 data; + + data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + + cached_state->n1postdiv = data & 0xf; + cached_state->n2postdiv = (data >> 4) & 0xf; + + DBG("DSI%d PLL save state %x %x", pll_14nm->id, + cached_state->n1postdiv, cached_state->n2postdiv); + + cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); +} + +static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + u32 data; + int ret; + + ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, + cached_state->vco_rate, 0); + if (ret) { + DRM_DEV_ERROR(&pll_14nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); + + DBG("DSI%d PLL restore state %x %x", pll_14nm->id, + cached_state->n1postdiv, cached_state->n2postdiv); + + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + + /* also restore post-dividers for slave DSI PLL */ + if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; + void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; + + pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + } + + return 0; +} + +static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, + enum msm_dsi_phy_usecase uc) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *base = pll_14nm->mmio; + u32 clkbuflr_en, bandgap = 0; + + switch (uc) { + case MSM_DSI_PHY_STANDALONE: + clkbuflr_en = 0x1; + break; + case MSM_DSI_PHY_MASTER: + clkbuflr_en = 0x3; + pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX]; + break; + case MSM_DSI_PHY_SLAVE: + clkbuflr_en = 0x0; + bandgap = 0x3; + break; + default: + return -EINVAL; + } + + pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); + if (bandgap) + pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); + + pll_14nm->uc = uc; + + return 0; +} + +static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data; + + if (byte_clk_provider) + *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; + if (pixel_clk_provider) + *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; + + return 0; +} + +static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct platform_device *pdev = pll_14nm->pdev; + int num_hws = pll_14nm->num_hws; + + of_clk_del_provider(pdev->dev.of_node); + + while (num_hws--) + clk_hw_unregister(pll_14nm->hws[num_hws]); +} + +static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, + const char *name, + const char *parent_name, + unsigned long flags, + u8 shift) +{ + struct dsi_pll_14nm_postdiv *pll_postdiv; + struct device *dev = &pll_14nm->pdev->dev; + struct clk_init_data postdiv_init = { + .parent_names = (const char *[]) { parent_name }, + .num_parents = 1, + .name = name, + .flags = flags, + .ops = &clk_ops_dsi_pll_14nm_postdiv, + }; + int ret; + + pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL); + if (!pll_postdiv) + return ERR_PTR(-ENOMEM); + + pll_postdiv->pll = pll_14nm; + pll_postdiv->shift = shift; + /* both N1 and N2 postdividers are 4 bits wide */ + pll_postdiv->width = 4; + /* range of each divider is from 1 to 15 */ + pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; + pll_postdiv->hw.init = &postdiv_init; + + ret = clk_hw_register(dev, &pll_postdiv->hw); + if (ret) + return ERR_PTR(ret); + + return &pll_postdiv->hw; +} + +static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) +{ + char clk_name[32], parent[32], vco_name[32]; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .name = vco_name, + .flags = CLK_IGNORE_UNUSED, + .ops = &clk_ops_dsi_pll_14nm_vco, + }; + struct device *dev = &pll_14nm->pdev->dev; + struct clk_hw **hws = pll_14nm->hws; + struct clk_hw_onecell_data *hw_data; + struct clk_hw *hw; + int num = 0; + int ret; + + DBG("DSI%d", pll_14nm->id); + + hw_data = devm_kzalloc(dev, sizeof(*hw_data) + + NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); + pll_14nm->base.clk_hw.init = &vco_init; + + ret = clk_hw_register(dev, &pll_14nm->base.clk_hw); + if (ret) + return ret; + + hws[num++] = &pll_14nm->base.clk_hw; + + snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id); + + /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ + hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, + CLK_SET_RATE_PARENT, 0); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + hws[num++] = hw; + + snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id); + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); + + /* DSI Byte clock = VCO_CLK / N1 / 8 */ + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + CLK_SET_RATE_PARENT, 1, 8); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + hws[num++] = hw; + hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + + snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); + + /* + * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider + * on the way. Don't let it set parent. + */ + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + hws[num++] = hw; + + snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id); + snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); + + /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 + * This is the output of N2 post-divider, bits 4-7 in + * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. + */ + hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + hws[num++] = hw; + hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; + + pll_14nm->num_hws = num; + + hw_data->num = NUM_PROVIDED_CLKS; + pll_14nm->hw_data = hw_data; + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + pll_14nm->hw_data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + return ret; + } + + return 0; +} + +struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) +{ + struct dsi_pll_14nm *pll_14nm; + struct msm_dsi_pll *pll; + int ret; + + if (!pdev) + return ERR_PTR(-ENODEV); + + pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); + if (!pll_14nm) + return ERR_PTR(-ENOMEM); + + DBG("PLL%d", id); + + pll_14nm->pdev = pdev; + pll_14nm->id = id; + pll_14nm_list[id] = pll_14nm; + + pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); + if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); + return ERR_PTR(-ENOMEM); + } + + pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_14nm->mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); + return ERR_PTR(-ENOMEM); + } + + spin_lock_init(&pll_14nm->postdiv_lock); + + pll = &pll_14nm->base; + pll->min_rate = VCO_MIN_RATE; + pll->max_rate = VCO_MAX_RATE; + pll->get_provider = dsi_pll_14nm_get_provider; + pll->destroy = dsi_pll_14nm_destroy; + pll->disable_seq = dsi_pll_14nm_disable_seq; + pll->save_state = dsi_pll_14nm_save_state; + pll->restore_state = dsi_pll_14nm_restore_state; + pll->set_usecase = dsi_pll_14nm_set_usecase; + + pll_14nm->vco_delay = 1; + + pll->en_seq_cnt = 1; + pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; + + ret = pll_14nm_register(pll_14nm); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + return pll; +} + static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing, int lane_idx) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 5bf79de0da67..2f502efa4dd5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -3,9 +3,646 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include +#include + #include "dsi_phy.h" +#include "dsi_pll.h" #include "dsi.xml.h" +/* + * DSI PLL 28nm - clock diagram (eg: DSI0): + * + * dsi0analog_postdiv_clk + * | dsi0indirect_path_div2_clk + * | | + * +------+ | +----+ | |\ dsi0byte_mux + * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ | + * | +------+ +----+ | m| | +----+ + * | | u|--o--| /4 |-- dsi0pllbyte + * | | x| +----+ + * o--------------------------| / + * | |/ + * | +------+ + * o----------| DIV3 |------------------------- dsi0pll + * +------+ + */ + +#define POLL_MAX_READS 10 +#define POLL_TIMEOUT_US 50 + +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 19200000 +#define VCO_MIN_RATE 350000000 +#define VCO_MAX_RATE 750000000 + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#define LPFR_LUT_SIZE 10 +struct lpfr_cfg { + unsigned long vco_rate; + u32 resistance; +}; + +/* Loop filter resistance: */ +static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = { + { 479500000, 8 }, + { 480000000, 11 }, + { 575500000, 8 }, + { 576000000, 12 }, + { 610500000, 8 }, + { 659500000, 9 }, + { 671500000, 10 }, + { 672000000, 14 }, + { 708500000, 10 }, + { 750000000, 11 }, +}; + +struct pll_28nm_cached_state { + unsigned long vco_rate; + u8 postdiv3; + u8 postdiv1; + u8 byte_mux; +}; + +struct dsi_pll_28nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + void __iomem *mmio; + + int vco_delay; + + /* private clocks: */ + struct clk *clks[NUM_DSI_CLOCKS_MAX]; + u32 num_clks; + + /* clock-provider: */ + struct clk *provided_clks[NUM_PROVIDED_CLKS]; + struct clk_onecell_data clk_data; + + struct pll_28nm_cached_state cached_state; +}; + +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) + +static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, + u32 nb_tries, u32 timeout_us) +{ + bool pll_locked = false; + u32 val; + + while (nb_tries--) { + val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); + pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); + + if (pll_locked) + break; + + udelay(timeout_us); + } + DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); + + return pll_locked; +} + +static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) +{ + void __iomem *base = pll_28nm->mmio; + + /* + * Add HW recommended delays after toggling the software + * reset bit off and back on. + */ + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, + DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1); + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); +} + +/* + * Clock Callbacks + */ +static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + unsigned long div_fbx1000, gen_vco_clk; + u32 refclk_cfg, frac_n_mode, frac_n_value; + u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; + u32 cal_cfg10, cal_cfg11; + u32 rem; + int i; + + VERB("rate=%lu, parent's=%lu", rate, parent_rate); + + /* Force postdiv2 to be div-4 */ + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); + + /* Configure the Loop filter resistance */ + for (i = 0; i < LPFR_LUT_SIZE; i++) + if (rate <= lpfr_lut[i].vco_rate) + break; + if (i == LPFR_LUT_SIZE) { + DRM_DEV_ERROR(dev, "unable to get loop filter resistance. vco=%lu\n", + rate); + return -EINVAL; + } + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); + + /* Loop filter capacitance values : c1 and c2 */ + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); + + rem = rate % VCO_REF_CLK_RATE; + if (rem) { + refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; + frac_n_mode = 1; + div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); + gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + } else { + refclk_cfg = 0x0; + frac_n_mode = 0; + div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); + gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + } + + DBG("refclk_cfg = %d", refclk_cfg); + + rem = div_fbx1000 % 1000; + frac_n_value = (rem << 16) / 1000; + + DBG("div_fb = %lu", div_fbx1000); + DBG("frac_n_value = %d", frac_n_value); + + DBG("Generated VCO Clock: %lu", gen_vco_clk); + rem = 0; + sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); + sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; + if (frac_n_mode) { + sdm_cfg0 = 0x0; + sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); + sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( + (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); + sdm_cfg3 = frac_n_value >> 8; + sdm_cfg2 = frac_n_value & 0xff; + } else { + sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; + sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( + (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); + sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); + sdm_cfg2 = 0; + sdm_cfg3 = 0; + } + + DBG("sdm_cfg0=%d", sdm_cfg0); + DBG("sdm_cfg1=%d", sdm_cfg1); + DBG("sdm_cfg2=%d", sdm_cfg2); + DBG("sdm_cfg3=%d", sdm_cfg3); + + cal_cfg11 = (u32)(gen_vco_clk / (256 * 1000000)); + cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000); + DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); + + pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); + pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, + DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2)); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, + DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3)); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); + + /* Add hardware recommended delay for correct PLL configuration */ + if (pll_28nm->vco_delay) + udelay(pll_28nm->vco_delay); + + pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); + pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); + pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); + + return 0; +} + +static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, + POLL_TIMEOUT_US); +} + +static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + void __iomem *base = pll_28nm->mmio; + u32 sdm0, doubler, sdm_byp_div; + u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; + u32 ref_clk = VCO_REF_CLK_RATE; + unsigned long vco_rate; + + VERB("parent_rate=%lu", parent_rate); + + /* Check to see if the ref clk doubler is enabled */ + doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & + DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; + ref_clk += (doubler * VCO_REF_CLK_RATE); + + /* see if it is integer mode or sdm mode */ + sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); + if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { + /* integer mode */ + sdm_byp_div = FIELD( + pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), + DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; + vco_rate = ref_clk * sdm_byp_div; + } else { + /* sdm mode */ + sdm_dc_off = FIELD( + pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), + DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET); + DBG("sdm_dc_off = %d", sdm_dc_off); + sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), + DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0); + sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), + DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8); + sdm_freq_seed = (sdm3 << 8) | sdm2; + DBG("sdm_freq_seed = %d", sdm_freq_seed); + + vco_rate = (ref_clk * (sdm_dc_off + 1)) + + mult_frac(ref_clk, sdm_freq_seed, BIT(16)); + DBG("vco rate = %lu", vco_rate); + } + + DBG("returning vco rate = %lu", vco_rate); + + return vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = msm_dsi_pll_helper_clk_prepare, + .unprepare = msm_dsi_pll_helper_clk_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + +/* + * PLL Callbacks + */ +static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + + for (i = 0; i < 2; i++) { + /* DSI Uniphy lock detect setting */ + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + 0x0c, 100); + pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); + + val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + } + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + +static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + bool locked; + u32 max_reads = 10, timeout_us = 50; + u32 val; + + DBG("id=%d", pll_28nm->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | + DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + /* DSI PLL toggle lock detect setting */ + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); + + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL lock success"); + + return locked ? 0 : -EINVAL; +} + +static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + DBG("id=%d", pll_28nm->id); + pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); +} + +static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + + cached_state->postdiv3 = + pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); + cached_state->postdiv1 = + pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); + cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); + if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw)) + cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); + else + cached_state->vco_rate = 0; +} + +static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + int ret; + + ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, + cached_state->vco_rate, 0); + if (ret) { + DRM_DEV_ERROR(&pll_28nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, + cached_state->postdiv3); + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + cached_state->postdiv1); + pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, + cached_state->byte_mux); + + return 0; +} + +static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + if (byte_clk_provider) + *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; + if (pixel_clk_provider) + *pixel_clk_provider = + pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; + + return 0; +} + +static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + int i; + + msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, + pll_28nm->clks, pll_28nm->num_clks); + + for (i = 0; i < NUM_PROVIDED_CLKS; i++) + pll_28nm->provided_clks[i] = NULL; + + pll_28nm->num_clks = 0; + pll_28nm->clk_data.clks = NULL; + pll_28nm->clk_data.clk_num = 0; +} + +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +{ + char clk_name[32], parent1[32], parent2[32], vco_name[32]; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .name = vco_name, + .flags = CLK_IGNORE_UNUSED, + .ops = &clk_ops_dsi_pll_28nm_vco, + }; + struct device *dev = &pll_28nm->pdev->dev; + struct clk **clks = pll_28nm->clks; + struct clk **provided_clks = pll_28nm->provided_clks; + int num = 0; + int ret; + + DBG("%d", pll_28nm->id); + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); + pll_28nm->base.clk_hw.init = &vco_init; + clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); + + snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + clks[num++] = clk_register_divider(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, + pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + 0, 4, 0, NULL); + + snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); + snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); + clks[num++] = clk_register_fixed_factor(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, + 1, 2); + + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = + clk_register_divider(dev, clk_name, + parent1, 0, pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, + 0, 8, 0, NULL); + + snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); + clks[num++] = clk_register_mux(dev, clk_name, + ((const char *[]){ + parent1, parent2 + }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); + + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); + snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); + clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = + clk_register_fixed_factor(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, 1, 4); + + pll_28nm->num_clks = num; + + pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; + pll_28nm->clk_data.clks = provided_clks; + + ret = of_clk_add_provider(dev->of_node, + of_clk_src_onecell_get, &pll_28nm->clk_data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + return ret; + } + + return 0; +} + +struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) +{ + struct dsi_pll_28nm *pll_28nm; + struct msm_dsi_pll *pll; + int ret; + + if (!pdev) + return ERR_PTR(-ENODEV); + + pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); + if (!pll_28nm) + return ERR_PTR(-ENOMEM); + + pll_28nm->pdev = pdev; + pll_28nm->id = id; + + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_28nm->mmio)) { + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); + return ERR_PTR(-ENOMEM); + } + + pll = &pll_28nm->base; + pll->min_rate = VCO_MIN_RATE; + pll->max_rate = VCO_MAX_RATE; + pll->get_provider = dsi_pll_28nm_get_provider; + pll->destroy = dsi_pll_28nm_destroy; + pll->disable_seq = dsi_pll_28nm_disable_seq; + pll->save_state = dsi_pll_28nm_save_state; + pll->restore_state = dsi_pll_28nm_restore_state; + + if (type == MSM_DSI_PHY_28NM_HPM) { + pll_28nm->vco_delay = 1; + + pll->en_seq_cnt = 3; + pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm; + pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm; + pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm; + } else if (type == MSM_DSI_PHY_28NM_LP) { + pll_28nm->vco_delay = 1000; + + pll->en_seq_cnt = 1; + pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp; + } else { + DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type); + return ERR_PTR(-EINVAL); + } + + ret = pll_28nm_register(pll_28nm); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + return pll; +} + + static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 5d33de27a0f4..4a40513057e8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -3,11 +3,530 @@ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. */ +#include #include #include "dsi_phy.h" +#include "dsi_pll.h" #include "dsi.xml.h" +/* + * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1): + * + * + * +------+ + * dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock) + * F * byte_clk | +------+ + * | bit clock divider (F / 8) + * | + * | +------+ + * o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG + * | +------+ | (sets parent rate) + * | byte clock divider (F) | + * | | + * | o---> To esc RCG + * | (doesn't set parent rate) + * | + * | +------+ + * o-----| DIV3 |----dsi0pll------o---> To dsi RCG + * +------+ | (sets parent rate) + * dsi clock divider (F * magic) | + * | + * o---> To pixel rcg + * (doesn't set parent rate) + */ + +#define POLL_MAX_READS 8000 +#define POLL_TIMEOUT_US 1 + +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 27000000 +#define VCO_MIN_RATE 600000000 +#define VCO_MAX_RATE 1200000000 + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#define VCO_PREF_DIV_RATIO 27 + +struct pll_28nm_cached_state { + unsigned long vco_rate; + u8 postdiv3; + u8 postdiv2; + u8 postdiv1; +}; + +struct clk_bytediv { + struct clk_hw hw; + void __iomem *reg; +}; + +struct dsi_pll_28nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + void __iomem *mmio; + + /* custom byte clock divider */ + struct clk_bytediv *bytediv; + + /* private clocks: */ + struct clk *clks[NUM_DSI_CLOCKS_MAX]; + u32 num_clks; + + /* clock-provider: */ + struct clk *provided_clks[NUM_PROVIDED_CLKS]; + struct clk_onecell_data clk_data; + + struct pll_28nm_cached_state cached_state; +}; + +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) + +static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, + int nb_tries, int timeout_us) +{ + bool pll_locked = false; + u32 val; + + while (nb_tries--) { + val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); + pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); + + if (pll_locked) + break; + + udelay(timeout_us); + } + DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); + + return pll_locked; +} + +/* + * Clock Callbacks + */ +static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + void __iomem *base = pll_28nm->mmio; + u32 val, temp, fb_divider; + + DBG("rate=%lu, parent's=%lu", rate, parent_rate); + + temp = rate / 10; + val = VCO_REF_CLK_RATE / 10; + fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; + fb_divider = fb_divider / 2 - 1; + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, + fb_divider & 0xff); + + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); + + val |= (fb_divider >> 8) & 0x07; + + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, + val); + + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + + val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f; + + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, + val); + + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, + 0xf); + + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val |= 0x7 << 4; + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, + val); + + return 0; +} + +static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, + POLL_TIMEOUT_US); +} + +static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + void __iomem *base = pll_28nm->mmio; + unsigned long vco_rate; + u32 status, fb_divider, temp, ref_divider; + + VERB("parent_rate=%lu", parent_rate); + + status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); + + if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) { + fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); + fb_divider &= 0xff; + temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; + fb_divider = (temp << 8) | fb_divider; + fb_divider += 1; + + ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + ref_divider &= 0x3f; + ref_divider += 1; + + /* multiply by 2 */ + vco_rate = (parent_rate / ref_divider) * fb_divider * 2; + } else { + vco_rate = 0; + } + + DBG("returning vco rate = %lu", vco_rate); + + return vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = msm_dsi_pll_helper_clk_prepare, + .unprepare = msm_dsi_pll_helper_clk_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + +/* + * Custom byte clock divier clk_ops + * + * This clock is the entry point to configuring the PLL. The user (dsi host) + * will set this clock's rate to the desired byte clock rate. The VCO lock + * frequency is a multiple of the byte clock rate. The multiplication factor + * (shown as F in the diagram above) is a function of the byte clock rate. + * + * This custom divider clock ensures that its parent (VCO) is set to the + * desired rate, and that the byte clock postdivider (POSTDIV2) is configured + * accordingly + */ +#define to_clk_bytediv(_hw) container_of(_hw, struct clk_bytediv, hw) + +static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_bytediv *bytediv = to_clk_bytediv(hw); + unsigned int div; + + div = pll_read(bytediv->reg) & 0xff; + + return parent_rate / (div + 1); +} + +/* find multiplication factor(wrt byte clock) at which the VCO should be set */ +static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate) +{ + unsigned long bit_mhz; + + /* convert to bit clock in Mhz */ + bit_mhz = (byte_clk_rate * 8) / 1000000; + + if (bit_mhz < 125) + return 64; + else if (bit_mhz < 250) + return 32; + else if (bit_mhz < 600) + return 16; + else + return 8; +} + +static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long best_parent; + unsigned int factor; + + factor = get_vco_mul_factor(rate); + + best_parent = rate * factor; + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + + return *prate / factor; +} + +static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_bytediv *bytediv = to_clk_bytediv(hw); + u32 val; + unsigned int factor; + + factor = get_vco_mul_factor(rate); + + val = pll_read(bytediv->reg); + val |= (factor - 1) & 0xff; + pll_write(bytediv->reg, val); + + return 0; +} + +/* Our special byte clock divider ops */ +static const struct clk_ops clk_bytediv_ops = { + .round_rate = clk_bytediv_round_rate, + .set_rate = clk_bytediv_set_rate, + .recalc_rate = clk_bytediv_recalc_rate, +}; + +/* + * PLL Callbacks + */ +static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + bool locked; + unsigned int bit_div, byte_div; + int max_reads = 1000, timeout_us = 100; + u32 val; + + DBG("id=%d", pll_28nm->id); + + /* + * before enabling the PLL, configure the bit clock divider since we + * don't expose it as a clock to the outside world + * 1: read back the byte clock divider that should already be set + * 2: divide by 8 to get bit clock divider + * 3: write it to POSTDIV1 + */ + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + byte_div = val + 1; + bit_div = byte_div / 8; + + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val &= ~0xf; + val |= (bit_div - 1); + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); + + /* enable the PLL */ + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, + DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); + + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL lock success"); + + return locked ? 0 : -EINVAL; +} + +static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + DBG("id=%d", pll_28nm->id); + pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); +} + +static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + + cached_state->postdiv3 = + pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); + cached_state->postdiv2 = + pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + cached_state->postdiv1 = + pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + + cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); +} + +static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + int ret; + + ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, + cached_state->vco_rate, 0); + if (ret) { + DRM_DEV_ERROR(&pll_28nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, + cached_state->postdiv3); + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, + cached_state->postdiv2); + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, + cached_state->postdiv1); + + return 0; +} + +static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + if (byte_clk_provider) + *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; + if (pixel_clk_provider) + *pixel_clk_provider = + pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; + + return 0; +} + +static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, + pll_28nm->clks, pll_28nm->num_clks); +} + +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +{ + char *clk_name, *parent_name, *vco_name; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .flags = CLK_IGNORE_UNUSED, + .ops = &clk_ops_dsi_pll_28nm_vco, + }; + struct device *dev = &pll_28nm->pdev->dev; + struct clk **clks = pll_28nm->clks; + struct clk **provided_clks = pll_28nm->provided_clks; + struct clk_bytediv *bytediv; + struct clk_init_data bytediv_init = { }; + int ret, num = 0; + + DBG("%d", pll_28nm->id); + + bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL); + if (!bytediv) + return -ENOMEM; + + vco_name = devm_kzalloc(dev, 32, GFP_KERNEL); + if (!vco_name) + return -ENOMEM; + + parent_name = devm_kzalloc(dev, 32, GFP_KERNEL); + if (!parent_name) + return -ENOMEM; + + clk_name = devm_kzalloc(dev, 32, GFP_KERNEL); + if (!clk_name) + return -ENOMEM; + + pll_28nm->bytediv = bytediv; + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); + vco_init.name = vco_name; + + pll_28nm->base.clk_hw.init = &vco_init; + + clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); + + /* prepare and register bytediv */ + bytediv->hw.init = &bytediv_init; + bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; + + snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); + + bytediv_init.name = clk_name; + bytediv_init.ops = &clk_bytediv_ops; + bytediv_init.flags = CLK_SET_RATE_PARENT; + bytediv_init.parent_names = (const char * const *) &parent_name; + bytediv_init.num_parents = 1; + + /* DIV2 */ + clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = + clk_register(dev, &bytediv->hw); + + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); + /* DIV3 */ + clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = + clk_register_divider(dev, clk_name, + parent_name, 0, pll_28nm->mmio + + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, + 0, 8, 0, NULL); + + pll_28nm->num_clks = num; + + pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; + pll_28nm->clk_data.clks = provided_clks; + + ret = of_clk_add_provider(dev->of_node, + of_clk_src_onecell_get, &pll_28nm->clk_data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + return ret; + } + + return 0; +} + +struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, + int id) +{ + struct dsi_pll_28nm *pll_28nm; + struct msm_dsi_pll *pll; + int ret; + + if (!pdev) + return ERR_PTR(-ENODEV); + + pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); + if (!pll_28nm) + return ERR_PTR(-ENOMEM); + + pll_28nm->pdev = pdev; + pll_28nm->id = id + 1; + + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_28nm->mmio)) { + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); + return ERR_PTR(-ENOMEM); + } + + pll = &pll_28nm->base; + pll->min_rate = VCO_MIN_RATE; + pll->max_rate = VCO_MAX_RATE; + pll->get_provider = dsi_pll_28nm_get_provider; + pll->destroy = dsi_pll_28nm_destroy; + pll->disable_seq = dsi_pll_28nm_disable_seq; + pll->save_state = dsi_pll_28nm_save_state; + pll->restore_state = dsi_pll_28nm_restore_state; + + pll->en_seq_cnt = 1; + pll->enable_seqs[0] = dsi_pll_28nm_enable_seq; + + ret = pll_28nm_register(pll_28nm); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + return pll; +} + static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index cbfeec860e69..f9af9d70b56a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -3,11 +3,916 @@ * Copyright (c) 2018, The Linux Foundation */ +#include +#include #include +#include "dsi_pll.h" #include "dsi_phy.h" #include "dsi.xml.h" +/* + * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram + * + * dsi0_pll_out_div_clk dsi0_pll_bit_clk + * | | + * | | + * +---------+ | +----------+ | +----+ + * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk + * +---------+ | +----------+ | +----+ + * | | + * | | dsi0_pll_by_2_bit_clk + * | | | + * | | +----+ | |\ dsi0_pclk_mux + * | |--| /2 |--o--| \ | + * | | +----+ | \ | +---------+ + * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk + * |------------------------------| / +---------+ + * | +-----+ | / + * -----------| /4? |--o----------|/ + * +-----+ | | + * | |dsiclk_sel + * | + * dsi0_pll_post_out_div_clk + */ + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 19200000 + +struct dsi_pll_regs { + u32 pll_prop_gain_rate; + u32 pll_lockdet_rate; + u32 decimal_div_start; + u32 frac_div_start_low; + u32 frac_div_start_mid; + u32 frac_div_start_high; + u32 pll_clock_inverters; + u32 ssc_stepsize_low; + u32 ssc_stepsize_high; + u32 ssc_div_per_low; + u32 ssc_div_per_high; + u32 ssc_adjper_low; + u32 ssc_adjper_high; + u32 ssc_control; +}; + +struct dsi_pll_config { + u32 ref_freq; + bool div_override; + u32 output_div; + bool ignore_frac; + bool disable_prescaler; + bool enable_ssc; + bool ssc_center; + u32 dec_bits; + u32 frac_bits; + u32 lock_timer; + u32 ssc_freq; + u32 ssc_offset; + u32 ssc_adj_per; + u32 thresh_cycles; + u32 refclk_cycles; +}; + +struct pll_7nm_cached_state { + unsigned long vco_rate; + u8 bit_clk_div; + u8 pix_clk_div; + u8 pll_out_div; + u8 pll_mux; +}; + +struct dsi_pll_7nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + + void __iomem *phy_cmn_mmio; + void __iomem *mmio; + + u64 vco_ref_clk_rate; + u64 vco_current_rate; + + /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ + spinlock_t postdiv_lock; + + int vco_delay; + struct dsi_pll_config pll_configuration; + struct dsi_pll_regs reg_setup; + + /* private clocks: */ + struct clk_hw *out_div_clk_hw; + struct clk_hw *bit_clk_hw; + struct clk_hw *byte_clk_hw; + struct clk_hw *by_2_bit_clk_hw; + struct clk_hw *post_out_div_clk_hw; + struct clk_hw *pclk_mux_hw; + struct clk_hw *out_dsiclk_hw; + + /* clock-provider: */ + struct clk_hw_onecell_data *hw_data; + + struct pll_7nm_cached_state cached_state; + + enum msm_dsi_phy_usecase uc; + struct dsi_pll_7nm *slave; +}; + +#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base) + +/* + * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * mode, where the master PLL's clk_ops needs access the slave's private data + */ +static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; + +static void dsi_pll_setup_config(struct dsi_pll_7nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + + config->ref_freq = pll->vco_ref_clk_rate; + config->output_div = 1; + config->dec_bits = 8; + config->frac_bits = 18; + config->lock_timer = 64; + config->ssc_freq = 31500; + config->ssc_offset = 4800; + config->ssc_adj_per = 2; + config->thresh_cycles = 32; + config->refclk_cycles = 256; + + config->div_override = false; + config->ignore_frac = false; + config->disable_prescaler = false; + + /* TODO: ssc enable */ + config->enable_ssc = false; + config->ssc_center = 0; +} + +static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u64 fref = pll->vco_ref_clk_rate; + u64 pll_freq; + u64 divider; + u64 dec, dec_multiple; + u32 frac; + u64 multiplier; + + pll_freq = pll->vco_current_rate; + + if (config->disable_prescaler) + divider = fref; + else + divider = fref * 2; + + multiplier = 1 << config->frac_bits; + dec_multiple = div_u64(pll_freq * multiplier, divider); + div_u64_rem(dec_multiple, multiplier, &frac); + + dec = div_u64(dec_multiple, multiplier); + + if (pll->base.type != MSM_DSI_PHY_7NM_V4_1) + regs->pll_clock_inverters = 0x28; + else if (pll_freq <= 1000000000ULL) + regs->pll_clock_inverters = 0xa0; + else if (pll_freq <= 2500000000ULL) + regs->pll_clock_inverters = 0x20; + else if (pll_freq <= 3020000000ULL) + regs->pll_clock_inverters = 0x00; + else + regs->pll_clock_inverters = 0x40; + + regs->pll_lockdet_rate = config->lock_timer; + regs->decimal_div_start = dec; + regs->frac_div_start_low = (frac & 0xff); + regs->frac_div_start_mid = (frac & 0xff00) >> 8; + regs->frac_div_start_high = (frac & 0x30000) >> 16; +} + +#define SSC_CENTER BIT(0) +#define SSC_EN BIT(1) + +static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u32 ssc_per; + u32 ssc_mod; + u64 ssc_step_size; + u64 frac; + + if (!config->enable_ssc) { + DBG("SSC not enabled\n"); + return; + } + + ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; + ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); + ssc_per -= ssc_mod; + + frac = regs->frac_div_start_low | + (regs->frac_div_start_mid << 8) | + (regs->frac_div_start_high << 16); + ssc_step_size = regs->decimal_div_start; + ssc_step_size *= (1 << config->frac_bits); + ssc_step_size += frac; + ssc_step_size *= config->ssc_offset; + ssc_step_size *= (config->ssc_adj_per + 1); + ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); + ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); + + regs->ssc_div_per_low = ssc_per & 0xFF; + regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; + regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); + regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); + regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; + regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; + + regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; + + pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", + regs->decimal_div_start, frac, config->frac_bits); + pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", + ssc_per, (u32)ssc_step_size, config->ssc_adj_per); +} + +static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) +{ + void __iomem *base = pll->mmio; + struct dsi_pll_regs *regs = &pll->reg_setup; + + if (pll->pll_configuration.enable_ssc) { + pr_debug("SSC is enabled\n"); + + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, + regs->ssc_stepsize_low); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, + regs->ssc_stepsize_high); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, + regs->ssc_div_per_low); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, + regs->ssc_div_per_high); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, + regs->ssc_adjper_low); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, + regs->ssc_adjper_high); + pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, + SSC_EN | regs->ssc_control); + } +} + +static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) +{ + void __iomem *base = pll->mmio; + u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; + + if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { + if (pll->vco_current_rate >= 3100000000ULL) + analog_controls_five_1 = 0x03; + + if (pll->vco_current_rate < 1520000000ULL) + vco_config_1 = 0x08; + else if (pll->vco_current_rate < 2990000000ULL) + vco_config_1 = 0x01; + } + + pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, + analog_controls_five_1); + pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); + pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); + pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); + pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); + pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); + pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); + pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); + pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); + pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); + pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); + pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); + pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); + pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); + pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); + pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, + pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); + + if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { + pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + if (pll->slave) + pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + } +} + +static void dsi_pll_commit(struct dsi_pll_7nm *pll) +{ + void __iomem *base = pll->mmio; + struct dsi_pll_regs *reg = &pll->reg_setup; + + pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); + pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); + pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); + pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); + pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); + pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ + pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); +} + +static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate, + parent_rate); + + pll_7nm->vco_current_rate = rate; + pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + + dsi_pll_setup_config(pll_7nm); + + dsi_pll_calc_dec_frac(pll_7nm); + + dsi_pll_calc_ssc(pll_7nm); + + dsi_pll_commit(pll_7nm); + + dsi_pll_config_hzindep_reg(pll_7nm); + + dsi_pll_ssc_commit(pll_7nm); + + /* flush, ensure all register writes are done*/ + wmb(); + + return 0; +} + +static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) +{ + int rc; + u32 status = 0; + u32 const delay_us = 100; + u32 const timeout_us = 5000; + + rc = readl_poll_timeout_atomic(pll->mmio + + REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE, + status, + ((status & BIT(0)) > 0), + delay_us, + timeout_us); + if (rc) + pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", + pll->id, status); + + return rc; +} + +static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) +{ + u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + + pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); + ndelay(250); +} + +static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) +{ + u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); + pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + ndelay(250); +} + +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +{ + u32 data; + + data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); +} + +static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) +{ + u32 data; + + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); + + data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, + data | BIT(5) | BIT(4)); +} + +static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) +{ + /* + * Reset the PHY digital domain. This would be needed when + * coming out of a CX or analog rail power collapse while + * ensuring that the pads maintain LP00 or LP11 state + */ + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); + wmb(); /* Ensure that the reset is deasserted */ + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); + wmb(); /* Ensure that the reset is deasserted */ +} + +static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + int rc; + + dsi_pll_enable_pll_bias(pll_7nm); + if (pll_7nm->slave) + dsi_pll_enable_pll_bias(pll_7nm->slave); + + /* Start PLL */ + pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); + + /* + * ensure all PLL configurations are written prior to checking + * for PLL lock. + */ + wmb(); + + /* Check for PLL lock */ + rc = dsi_pll_7nm_lock_status(pll_7nm); + if (rc) { + pr_err("PLL(%d) lock failed\n", pll_7nm->id); + goto error; + } + + pll->pll_on = true; + + /* + * assert power on reset for PHY digital in case the PLL is + * enabled after CX of analog domain power collapse. This needs + * to be done before enabling the global clk. + */ + dsi_pll_phy_dig_reset(pll_7nm); + if (pll_7nm->slave) + dsi_pll_phy_dig_reset(pll_7nm->slave); + + dsi_pll_enable_global_clk(pll_7nm); + if (pll_7nm->slave) + dsi_pll_enable_global_clk(pll_7nm->slave); + +error: + return rc; +} + +static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) +{ + pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); + dsi_pll_disable_pll_bias(pll); +} + +static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + + /* + * To avoid any stray glitches while abruptly powering down the PLL + * make sure to gate the clock using the clock enable bit before + * powering down the PLL + */ + dsi_pll_disable_global_clk(pll_7nm); + pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); + dsi_pll_disable_sub(pll_7nm); + if (pll_7nm->slave) { + dsi_pll_disable_global_clk(pll_7nm->slave); + dsi_pll_disable_sub(pll_7nm->slave); + } + /* flush, ensure all register writes are done */ + wmb(); + pll->pll_on = false; +} + +static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_config *config = &pll_7nm->pll_configuration; + void __iomem *base = pll_7nm->mmio; + u64 ref_clk = pll_7nm->vco_ref_clk_rate; + u64 vco_rate = 0x0; + u64 multiplier; + u32 frac; + u32 dec; + u64 pll_freq, tmp64; + + dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); + dec &= 0xff; + + frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & + 0xff) << 8); + frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + 0x3) << 16); + + /* + * TODO: + * 1. Assumes prescaler is disabled + */ + multiplier = 1 << config->frac_bits; + pll_freq = dec * (ref_clk * 2); + tmp64 = (ref_clk * 2 * frac); + pll_freq += div_u64(tmp64, multiplier); + + vco_rate = pll_freq; + + DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", + pll_7nm->id, (unsigned long)vco_rate, dec, frac); + + return (unsigned long)vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_7nm_vco_set_rate, + .recalc_rate = dsi_pll_7nm_vco_recalc_rate, + .prepare = dsi_pll_7nm_vco_prepare, + .unprepare = dsi_pll_7nm_vco_unprepare, +}; + +/* + * PLL Callbacks + */ + +static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; + void __iomem *phy_base = pll_7nm->phy_cmn_mmio; + u32 cmn_clk_cfg0, cmn_clk_cfg1; + + cached->pll_out_div = pll_read(pll_7nm->mmio + + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + cached->pll_out_div &= 0x3; + + cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); + cached->bit_clk_div = cmn_clk_cfg0 & 0xf; + cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; + + cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + cached->pll_mux = cmn_clk_cfg1 & 0x3; + + DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", + pll_7nm->id, cached->pll_out_div, cached->bit_clk_div, + cached->pix_clk_div, cached->pll_mux); +} + +static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; + void __iomem *phy_base = pll_7nm->phy_cmn_mmio; + u32 val; + int ret; + + val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + val &= ~0x3; + val |= cached->pll_out_div; + pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); + + pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + cached->bit_clk_div | (cached->pix_clk_div << 4)); + + val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + val &= ~0x3; + val |= cached->pll_mux; + pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); + + ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); + if (ret) { + DRM_DEV_ERROR(&pll_7nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + DBG("DSI PLL%d", pll_7nm->id); + + return 0; +} + +static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, + enum msm_dsi_phy_usecase uc) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + void __iomem *base = pll_7nm->phy_cmn_mmio; + u32 data = 0x0; /* internal PLL */ + + DBG("DSI PLL%d", pll_7nm->id); + + switch (uc) { + case MSM_DSI_PHY_STANDALONE: + break; + case MSM_DSI_PHY_MASTER: + pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX]; + break; + case MSM_DSI_PHY_SLAVE: + data = 0x1; /* external PLL */ + break; + default: + return -EINVAL; + } + + /* set PLL src */ + pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); + + pll_7nm->uc = uc; + + return 0; +} + +static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data; + + DBG("DSI PLL%d", pll_7nm->id); + + if (byte_clk_provider) + *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; + if (pixel_clk_provider) + *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; + + return 0; +} + +static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct device *dev = &pll_7nm->pdev->dev; + + DBG("DSI PLL%d", pll_7nm->id); + of_clk_del_provider(dev->of_node); + + clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); + clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); + clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); + clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); + clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); + clk_hw_unregister_divider(pll_7nm->bit_clk_hw); + clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); + clk_hw_unregister(&pll_7nm->base.clk_hw); +} + +/* + * The post dividers and mux clocks are created using the standard divider and + * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux + * state to follow the master PLL's divider/mux state. Therefore, we don't + * require special clock ops that also configure the slave PLL registers + */ +static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) +{ + char clk_name[32], parent[32], vco_name[32]; + char parent2[32], parent3[32], parent4[32]; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .name = vco_name, + .flags = CLK_IGNORE_UNUSED, + .ops = &clk_ops_dsi_pll_7nm_vco, + }; + struct device *dev = &pll_7nm->pdev->dev; + struct clk_hw_onecell_data *hw_data; + struct clk_hw *hw; + int ret; + + DBG("DSI%d", pll_7nm->id); + + hw_data = devm_kzalloc(dev, sizeof(*hw_data) + + NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); + pll_7nm->base.clk_hw.init = &vco_init; + + ret = clk_hw_register(dev, &pll_7nm->base.clk_hw); + if (ret) + return ret; + + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id); + + hw = clk_hw_register_divider(dev, clk_name, + parent, CLK_SET_RATE_PARENT, + pll_7nm->mmio + + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, + 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_base_clk_hw; + } + + pll_7nm->out_div_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + + /* BIT CLK: DIV_CTRL_3_0 */ + hw = clk_hw_register_divider(dev, clk_name, parent, + CLK_SET_RATE_PARENT, + pll_7nm->phy_cmn_mmio + + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + 0, 4, CLK_DIVIDER_ONE_BASED, + &pll_7nm->postdiv_lock); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_out_div_clk_hw; + } + + pll_7nm->bit_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + + /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + CLK_SET_RATE_PARENT, 1, 8); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_bit_clk_hw; + } + + pll_7nm->byte_clk_hw = hw; + hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + 0, 1, 2); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_byte_clk_hw; + } + + pll_7nm->by_2_bit_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + + hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + 0, 1, 4); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_by_2_bit_clk_hw; + } + + pll_7nm->post_out_div_clk_hw = hw; + + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); + + hw = clk_hw_register_mux(dev, clk_name, + ((const char *[]){ + parent, parent2, parent3, parent4 + }), 4, 0, pll_7nm->phy_cmn_mmio + + REG_DSI_7nm_PHY_CMN_CLK_CFG1, + 0, 2, 0, NULL); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_post_out_div_clk_hw; + } + + pll_7nm->pclk_mux_hw = hw; + + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id); + snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id); + + /* PIX CLK DIV : DIV_CTRL_7_4*/ + hw = clk_hw_register_divider(dev, clk_name, parent, + 0, pll_7nm->phy_cmn_mmio + + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + 4, 4, CLK_DIVIDER_ONE_BASED, + &pll_7nm->postdiv_lock); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto err_pclk_mux_hw; + } + + pll_7nm->out_dsiclk_hw = hw; + hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; + + hw_data->num = NUM_PROVIDED_CLKS; + pll_7nm->hw_data = hw_data; + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + pll_7nm->hw_data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); + goto err_dsiclk_hw; + } + + return 0; + +err_dsiclk_hw: + clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); +err_pclk_mux_hw: + clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); +err_post_out_div_clk_hw: + clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); +err_by_2_bit_clk_hw: + clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); +err_byte_clk_hw: + clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); +err_bit_clk_hw: + clk_hw_unregister_divider(pll_7nm->bit_clk_hw); +err_out_div_clk_hw: + clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); +err_base_clk_hw: + clk_hw_unregister(&pll_7nm->base.clk_hw); + + return ret; +} + +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) +{ + struct dsi_pll_7nm *pll_7nm; + struct msm_dsi_pll *pll; + int ret; + + pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); + if (!pll_7nm) + return ERR_PTR(-ENOMEM); + + DBG("DSI PLL%d", id); + + pll_7nm->pdev = pdev; + pll_7nm->id = id; + pll_7nm_list[id] = pll_7nm; + + pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); + if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); + return ERR_PTR(-ENOMEM); + } + + pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_7nm->mmio)) { + DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); + return ERR_PTR(-ENOMEM); + } + + spin_lock_init(&pll_7nm->postdiv_lock); + + pll = &pll_7nm->base; + pll->min_rate = 1000000000UL; + pll->max_rate = 3500000000UL; + if (type == MSM_DSI_PHY_7NM_V4_1) { + pll->min_rate = 600000000UL; + pll->max_rate = (unsigned long)5000000000ULL; + /* workaround for max rate overflowing on 32-bit builds: */ + pll->max_rate = max(pll->max_rate, 0xffffffffUL); + } + pll->get_provider = dsi_pll_7nm_get_provider; + pll->destroy = dsi_pll_7nm_destroy; + pll->save_state = dsi_pll_7nm_save_state; + pll->restore_state = dsi_pll_7nm_restore_state; + pll->set_usecase = dsi_pll_7nm_set_usecase; + + pll_7nm->vco_delay = 1; + + ret = pll_7nm_register(pll_7nm); + if (ret) { + DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + /* TODO: Remove this when we have proper display handover support */ + msm_dsi_pll_save_state(pll); + + return pll; +} + static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) { void __iomem *base = phy->base; diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c similarity index 100% rename from drivers/gpu/drm/msm/dsi/pll/dsi_pll.c rename to drivers/gpu/drm/msm/dsi/phy/dsi_pll.c diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h similarity index 100% rename from drivers/gpu/drm/msm/dsi/pll/dsi_pll.h rename to drivers/gpu/drm/msm/dsi/phy/dsi_pll.h diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c deleted file mode 100644 index de3b802ccd3d..000000000000 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ /dev/null @@ -1,881 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 - * Copyright (c) 2018, The Linux Foundation - */ - -#include -#include -#include - -#include "dsi_pll.h" -#include "dsi.xml.h" - -/* - * DSI PLL 10nm - clock diagram (eg: DSI0): - * - * dsi0_pll_out_div_clk dsi0_pll_bit_clk - * | | - * | | - * +---------+ | +----------+ | +----+ - * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk - * +---------+ | +----------+ | +----+ - * | | - * | | dsi0_pll_by_2_bit_clk - * | | | - * | | +----+ | |\ dsi0_pclk_mux - * | |--| /2 |--o--| \ | - * | | +----+ | \ | +---------+ - * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk - * |------------------------------| / +---------+ - * | +-----+ | / - * -----------| /4? |--o----------|/ - * +-----+ | | - * | |dsiclk_sel - * | - * dsi0_pll_post_out_div_clk - */ - -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 -#define NUM_PROVIDED_CLKS 2 - -#define VCO_REF_CLK_RATE 19200000 - -struct dsi_pll_regs { - u32 pll_prop_gain_rate; - u32 pll_lockdet_rate; - u32 decimal_div_start; - u32 frac_div_start_low; - u32 frac_div_start_mid; - u32 frac_div_start_high; - u32 pll_clock_inverters; - u32 ssc_stepsize_low; - u32 ssc_stepsize_high; - u32 ssc_div_per_low; - u32 ssc_div_per_high; - u32 ssc_adjper_low; - u32 ssc_adjper_high; - u32 ssc_control; -}; - -struct dsi_pll_config { - u32 ref_freq; - bool div_override; - u32 output_div; - bool ignore_frac; - bool disable_prescaler; - bool enable_ssc; - bool ssc_center; - u32 dec_bits; - u32 frac_bits; - u32 lock_timer; - u32 ssc_freq; - u32 ssc_offset; - u32 ssc_adj_per; - u32 thresh_cycles; - u32 refclk_cycles; -}; - -struct pll_10nm_cached_state { - unsigned long vco_rate; - u8 bit_clk_div; - u8 pix_clk_div; - u8 pll_out_div; - u8 pll_mux; -}; - -struct dsi_pll_10nm { - struct msm_dsi_pll base; - - int id; - struct platform_device *pdev; - - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - - u64 vco_ref_clk_rate; - u64 vco_current_rate; - - /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ - spinlock_t postdiv_lock; - - int vco_delay; - struct dsi_pll_config pll_configuration; - struct dsi_pll_regs reg_setup; - - /* private clocks: */ - struct clk_hw *out_div_clk_hw; - struct clk_hw *bit_clk_hw; - struct clk_hw *byte_clk_hw; - struct clk_hw *by_2_bit_clk_hw; - struct clk_hw *post_out_div_clk_hw; - struct clk_hw *pclk_mux_hw; - struct clk_hw *out_dsiclk_hw; - - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - - struct pll_10nm_cached_state cached_state; - - enum msm_dsi_phy_usecase uc; - struct dsi_pll_10nm *slave; -}; - -#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base) - -/* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI - * mode, where the master PLL's clk_ops needs access the slave's private data - */ -static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX]; - -static void dsi_pll_setup_config(struct dsi_pll_10nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - - config->ref_freq = pll->vco_ref_clk_rate; - config->output_div = 1; - config->dec_bits = 8; - config->frac_bits = 18; - config->lock_timer = 64; - config->ssc_freq = 31500; - config->ssc_offset = 5000; - config->ssc_adj_per = 2; - config->thresh_cycles = 32; - config->refclk_cycles = 256; - - config->div_override = false; - config->ignore_frac = false; - config->disable_prescaler = false; - - config->enable_ssc = false; - config->ssc_center = 0; -} - -static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u64 fref = pll->vco_ref_clk_rate; - u64 pll_freq; - u64 divider; - u64 dec, dec_multiple; - u32 frac; - u64 multiplier; - - pll_freq = pll->vco_current_rate; - - if (config->disable_prescaler) - divider = fref; - else - divider = fref * 2; - - multiplier = 1 << config->frac_bits; - dec_multiple = div_u64(pll_freq * multiplier, divider); - dec = div_u64_rem(dec_multiple, multiplier, &frac); - - if (pll_freq <= 1900000000UL) - regs->pll_prop_gain_rate = 8; - else if (pll_freq <= 3000000000UL) - regs->pll_prop_gain_rate = 10; - else - regs->pll_prop_gain_rate = 12; - if (pll_freq < 1100000000UL) - regs->pll_clock_inverters = 8; - else - regs->pll_clock_inverters = 0; - - regs->pll_lockdet_rate = config->lock_timer; - regs->decimal_div_start = dec; - regs->frac_div_start_low = (frac & 0xff); - regs->frac_div_start_mid = (frac & 0xff00) >> 8; - regs->frac_div_start_high = (frac & 0x30000) >> 16; -} - -#define SSC_CENTER BIT(0) -#define SSC_EN BIT(1) - -static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u32 ssc_per; - u32 ssc_mod; - u64 ssc_step_size; - u64 frac; - - if (!config->enable_ssc) { - DBG("SSC not enabled\n"); - return; - } - - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; - ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); - ssc_per -= ssc_mod; - - frac = regs->frac_div_start_low | - (regs->frac_div_start_mid << 8) | - (regs->frac_div_start_high << 16); - ssc_step_size = regs->decimal_div_start; - ssc_step_size *= (1 << config->frac_bits); - ssc_step_size += frac; - ssc_step_size *= config->ssc_offset; - ssc_step_size *= (config->ssc_adj_per + 1); - ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); - ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); - - regs->ssc_div_per_low = ssc_per & 0xFF; - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; - - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; - - pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", - regs->decimal_div_start, frac, config->frac_bits); - pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", - ssc_per, (u32)ssc_step_size, config->ssc_adj_per); -} - -static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) -{ - void __iomem *base = pll->mmio; - struct dsi_pll_regs *regs = &pll->reg_setup; - - if (pll->pll_configuration.enable_ssc) { - pr_debug("SSC is enabled\n"); - - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - regs->ssc_stepsize_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - regs->ssc_stepsize_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, - regs->ssc_div_per_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - regs->ssc_div_per_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, - regs->ssc_adjper_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, - regs->ssc_adjper_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, - SSC_EN | regs->ssc_control); - } -} - -static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) -{ - void __iomem *base = pll->mmio; - - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, - 0xba); - pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, - 0x4c); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); - pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); -} - -static void dsi_pll_commit(struct dsi_pll_10nm *pll) -{ - void __iomem *base = pll->mmio; - struct dsi_pll_regs *reg = &pll->reg_setup; - - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, - reg->decimal_div_start); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, - reg->frac_div_start_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, - reg->frac_div_start_mid); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, - reg->frac_div_start_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, - reg->pll_lockdet_rate); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); - pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, - reg->pll_clock_inverters); -} - -static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate, - parent_rate); - - pll_10nm->vco_current_rate = rate; - pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - - dsi_pll_setup_config(pll_10nm); - - dsi_pll_calc_dec_frac(pll_10nm); - - dsi_pll_calc_ssc(pll_10nm); - - dsi_pll_commit(pll_10nm); - - dsi_pll_config_hzindep_reg(pll_10nm); - - dsi_pll_ssc_commit(pll_10nm); - - /* flush, ensure all register writes are done*/ - wmb(); - - return 0; -} - -static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) -{ - struct device *dev = &pll->pdev->dev; - int rc; - u32 status = 0; - u32 const delay_us = 100; - u32 const timeout_us = 5000; - - rc = readl_poll_timeout_atomic(pll->mmio + - REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE, - status, - ((status & BIT(0)) > 0), - delay_us, - timeout_us); - if (rc) - DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n", - pll->id, status); - - return rc; -} - -static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) -{ - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); - - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, - data & ~BIT(5)); - ndelay(250); -} - -static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) -{ - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); - - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, - data | BIT(5)); - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); - ndelay(250); -} - -static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) -{ - u32 data; - - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, - data & ~BIT(5)); -} - -static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) -{ - u32 data; - - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, - data | BIT(5)); -} - -static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct device *dev = &pll_10nm->pdev->dev; - int rc; - - dsi_pll_enable_pll_bias(pll_10nm); - if (pll_10nm->slave) - dsi_pll_enable_pll_bias(pll_10nm->slave); - - rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0); - if (rc) { - DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc); - return rc; - } - - /* Start PLL */ - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, - 0x01); - - /* - * ensure all PLL configurations are written prior to checking - * for PLL lock. - */ - wmb(); - - /* Check for PLL lock */ - rc = dsi_pll_10nm_lock_status(pll_10nm); - if (rc) { - DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id); - goto error; - } - - pll->pll_on = true; - - dsi_pll_enable_global_clk(pll_10nm); - if (pll_10nm->slave) - dsi_pll_enable_global_clk(pll_10nm->slave); - - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, - 0x01); - if (pll_10nm->slave) - pll_write(pll_10nm->slave->phy_cmn_mmio + - REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); - -error: - return rc; -} - -static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) -{ - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); - dsi_pll_disable_pll_bias(pll); -} - -static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - - /* - * To avoid any stray glitches while abruptly powering down the PLL - * make sure to gate the clock using the clock enable bit before - * powering down the PLL - */ - dsi_pll_disable_global_clk(pll_10nm); - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); - dsi_pll_disable_sub(pll_10nm); - if (pll_10nm->slave) { - dsi_pll_disable_global_clk(pll_10nm->slave); - dsi_pll_disable_sub(pll_10nm->slave); - } - /* flush, ensure all register writes are done */ - wmb(); - pll->pll_on = false; -} - -static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct dsi_pll_config *config = &pll_10nm->pll_configuration; - void __iomem *base = pll_10nm->mmio; - u64 ref_clk = pll_10nm->vco_ref_clk_rate; - u64 vco_rate = 0x0; - u64 multiplier; - u32 frac; - u32 dec; - u64 pll_freq, tmp64; - - dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); - dec &= 0xff; - - frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & - 0xff) << 8); - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & - 0x3) << 16); - - /* - * TODO: - * 1. Assumes prescaler is disabled - */ - multiplier = 1 << config->frac_bits; - pll_freq = dec * (ref_clk * 2); - tmp64 = (ref_clk * 2 * frac); - pll_freq += div_u64(tmp64, multiplier); - - vco_rate = pll_freq; - - DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", - pll_10nm->id, (unsigned long)vco_rate, dec, frac); - - return (unsigned long)vco_rate; -} - -static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_10nm_vco_set_rate, - .recalc_rate = dsi_pll_10nm_vco_recalc_rate, - .prepare = dsi_pll_10nm_vco_prepare, - .unprepare = dsi_pll_10nm_vco_unprepare, -}; - -/* - * PLL Callbacks - */ - -static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; - void __iomem *phy_base = pll_10nm->phy_cmn_mmio; - u32 cmn_clk_cfg0, cmn_clk_cfg1; - - cached->pll_out_div = pll_read(pll_10nm->mmio + - REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); - cached->pll_out_div &= 0x3; - - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); - cached->bit_clk_div = cmn_clk_cfg0 & 0xf; - cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; - - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - cached->pll_mux = cmn_clk_cfg1 & 0x3; - - DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", - pll_10nm->id, cached->pll_out_div, cached->bit_clk_div, - cached->pix_clk_div, cached->pll_mux); -} - -static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; - void __iomem *phy_base = pll_10nm->phy_cmn_mmio; - u32 val; - int ret; - - val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); - val &= ~0x3; - val |= cached->pll_out_div; - pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); - - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, - cached->bit_clk_div | (cached->pix_clk_div << 4)); - - val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - val &= ~0x3; - val |= cached->pll_mux; - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); - - ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); - if (ret) { - DRM_DEV_ERROR(&pll_10nm->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); - return ret; - } - - DBG("DSI PLL%d", pll_10nm->id); - - return 0; -} - -static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - void __iomem *base = pll_10nm->phy_cmn_mmio; - u32 data = 0x0; /* internal PLL */ - - DBG("DSI PLL%d", pll_10nm->id); - - switch (uc) { - case MSM_DSI_PHY_STANDALONE: - break; - case MSM_DSI_PHY_MASTER: - pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX]; - break; - case MSM_DSI_PHY_SLAVE: - data = 0x1; /* external PLL */ - break; - default: - return -EINVAL; - } - - /* set PLL src */ - pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); - - pll_10nm->uc = uc; - - return 0; -} - -static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; - - DBG("DSI PLL%d", pll_10nm->id); - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - -static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct device *dev = &pll_10nm->pdev->dev; - - DBG("DSI PLL%d", pll_10nm->id); - of_clk_del_provider(dev->of_node); - - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); - clk_hw_unregister_divider(pll_10nm->bit_clk_hw); - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); - clk_hw_unregister(&pll_10nm->base.clk_hw); -} - -/* - * The post dividers and mux clocks are created using the standard divider and - * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux - * state to follow the master PLL's divider/mux state. Therefore, we don't - * require special clock ops that also configure the slave PLL registers - */ -static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) -{ - char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; - struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .name = vco_name, - .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_10nm_vco, - }; - struct device *dev = &pll_10nm->pdev->dev; - struct clk_hw_onecell_data *hw_data; - struct clk_hw *hw; - int ret; - - DBG("DSI%d", pll_10nm->id); - - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); - pll_10nm->base.clk_hw.init = &vco_init; - - ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); - if (ret) - return ret; - - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id); - - hw = clk_hw_register_divider(dev, clk_name, - parent, CLK_SET_RATE_PARENT, - pll_10nm->mmio + - REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, - 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_base_clk_hw; - } - - pll_10nm->out_div_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - - /* BIT CLK: DIV_CTRL_3_0 */ - hw = clk_hw_register_divider(dev, clk_name, parent, - CLK_SET_RATE_PARENT, - pll_10nm->phy_cmn_mmio + - REG_DSI_10nm_PHY_CMN_CLK_CFG0, - 0, 4, CLK_DIVIDER_ONE_BASED, - &pll_10nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_out_div_clk_hw; - } - - pll_10nm->bit_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - - /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_bit_clk_hw; - } - - pll_10nm->byte_clk_hw = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; - - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 2); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_byte_clk_hw; - } - - pll_10nm->by_2_bit_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 4); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_by_2_bit_clk_hw; - } - - pll_10nm->post_out_div_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); - - hw = clk_hw_register_mux(dev, clk_name, - ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_10nm->phy_cmn_mmio + - REG_DSI_10nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_post_out_div_clk_hw; - } - - pll_10nm->pclk_mux_hw = hw; - - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); - - /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = clk_hw_register_divider(dev, clk_name, parent, - 0, pll_10nm->phy_cmn_mmio + - REG_DSI_10nm_PHY_CMN_CLK_CFG0, - 4, 4, CLK_DIVIDER_ONE_BASED, - &pll_10nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_pclk_mux_hw; - } - - pll_10nm->out_dsiclk_hw = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_10nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_10nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - goto err_dsiclk_hw; - } - - return 0; - -err_dsiclk_hw: - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); -err_pclk_mux_hw: - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); -err_post_out_div_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); -err_by_2_bit_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); -err_byte_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); -err_bit_clk_hw: - clk_hw_unregister_divider(pll_10nm->bit_clk_hw); -err_out_div_clk_hw: - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); -err_base_clk_hw: - clk_hw_unregister(&pll_10nm->base.clk_hw); - - return ret; -} - -struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) -{ - struct dsi_pll_10nm *pll_10nm; - struct msm_dsi_pll *pll; - int ret; - - pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); - if (!pll_10nm) - return ERR_PTR(-ENOMEM); - - DBG("DSI PLL%d", id); - - pll_10nm->pdev = pdev; - pll_10nm->id = id; - pll_10nm_list[id] = pll_10nm; - - pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); - } - - pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_10nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); - } - - spin_lock_init(&pll_10nm->postdiv_lock); - - pll = &pll_10nm->base; - pll->min_rate = 1000000000UL; - pll->max_rate = 3500000000UL; - pll->get_provider = dsi_pll_10nm_get_provider; - pll->destroy = dsi_pll_10nm_destroy; - pll->save_state = dsi_pll_10nm_save_state; - pll->restore_state = dsi_pll_10nm_restore_state; - pll->set_usecase = dsi_pll_10nm_set_usecase; - - pll_10nm->vco_delay = 1; - - ret = pll_10nm_register(pll_10nm); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - /* TODO: Remove this when we have proper display handover support */ - msm_dsi_pll_save_state(pll); - - return pll; -} diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c deleted file mode 100644 index f847376d501e..000000000000 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c +++ /dev/null @@ -1,1096 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -#include -#include - -#include "dsi_pll.h" -#include "dsi.xml.h" - -/* - * DSI PLL 14nm - clock diagram (eg: DSI0): - * - * dsi0n1_postdiv_clk - * | - * | - * +----+ | +----+ - * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte - * +----+ | +----+ - * | dsi0n1_postdivby2_clk - * | +----+ | - * o---| /2 |--o--|\ - * | +----+ | \ +----+ - * | | |--| n2 |-- dsi0pll - * o--------------| / +----+ - * |/ - */ - -#define POLL_MAX_READS 15 -#define POLL_TIMEOUT_US 1000 - -#define NUM_PROVIDED_CLKS 2 - -#define VCO_REF_CLK_RATE 19200000 -#define VCO_MIN_RATE 1300000000UL -#define VCO_MAX_RATE 2600000000UL - -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - -#define DSI_PLL_DEFAULT_VCO_POSTDIV 1 - -struct dsi_pll_input { - u32 fref; /* reference clk */ - u32 fdata; /* bit clock rate */ - u32 dsiclk_sel; /* Mux configuration (see diagram) */ - u32 ssc_en; /* SSC enable/disable */ - u32 ldo_en; - - /* fixed params */ - u32 refclk_dbler_en; - u32 vco_measure_time; - u32 kvco_measure_time; - u32 bandgap_timer; - u32 pll_wakeup_timer; - u32 plllock_cnt; - u32 plllock_rng; - u32 ssc_center; - u32 ssc_adj_period; - u32 ssc_spread; - u32 ssc_freq; - u32 pll_ie_trim; - u32 pll_ip_trim; - u32 pll_iptat_trim; - u32 pll_cpcset_cur; - u32 pll_cpmset_cur; - - u32 pll_icpmset; - u32 pll_icpcset; - - u32 pll_icpmset_p; - u32 pll_icpmset_m; - - u32 pll_icpcset_p; - u32 pll_icpcset_m; - - u32 pll_lpf_res1; - u32 pll_lpf_cap1; - u32 pll_lpf_cap2; - u32 pll_c3ctrl; - u32 pll_r3ctrl; -}; - -struct dsi_pll_output { - u32 pll_txclk_en; - u32 dec_start; - u32 div_frac_start; - u32 ssc_period; - u32 ssc_step_size; - u32 plllock_cmp; - u32 pll_vco_div_ref; - u32 pll_vco_count; - u32 pll_kvco_div_ref; - u32 pll_kvco_count; - u32 pll_misc1; - u32 pll_lpf2_postdiv; - u32 pll_resetsm_cntrl; - u32 pll_resetsm_cntrl2; - u32 pll_resetsm_cntrl5; - u32 pll_kvco_code; - - u32 cmn_clk_cfg0; - u32 cmn_clk_cfg1; - u32 cmn_ldo_cntrl; - - u32 pll_postdiv; - u32 fcvo; -}; - -struct pll_14nm_cached_state { - unsigned long vco_rate; - u8 n2postdiv; - u8 n1postdiv; -}; - -struct dsi_pll_14nm { - struct msm_dsi_pll base; - - int id; - struct platform_device *pdev; - - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - - int vco_delay; - - struct dsi_pll_input in; - struct dsi_pll_output out; - - /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ - spinlock_t postdiv_lock; - - u64 vco_current_rate; - u64 vco_ref_clk_rate; - - /* private clocks: */ - struct clk_hw *hws[NUM_DSI_CLOCKS_MAX]; - u32 num_hws; - - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - - struct pll_14nm_cached_state cached_state; - - enum msm_dsi_phy_usecase uc; - struct dsi_pll_14nm *slave; -}; - -#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base) - -/* - * Private struct for N1/N2 post-divider clocks. These clocks are similar to - * the generic clk_divider class of clocks. The only difference is that it - * also sets the slave DSI PLL's post-dividers if in Dual DSI mode - */ -struct dsi_pll_14nm_postdiv { - struct clk_hw hw; - - /* divider params */ - u8 shift; - u8 width; - u8 flags; /* same flags as used by clk_divider struct */ - - struct dsi_pll_14nm *pll; -}; - -#define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) - -/* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI - * mode, where the master PLL's clk_ops needs access the slave's private data - */ -static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; - -static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, - u32 nb_tries, u32 timeout_us) -{ - bool pll_locked = false; - void __iomem *base = pll_14nm->mmio; - u32 tries, val; - - tries = nb_tries; - while (tries--) { - val = pll_read(base + - REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); - pll_locked = !!(val & BIT(5)); - - if (pll_locked) - break; - - udelay(timeout_us); - } - - if (!pll_locked) { - tries = nb_tries; - while (tries--) { - val = pll_read(base + - REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); - pll_locked = !!(val & BIT(0)); - - if (pll_locked) - break; - - udelay(timeout_us); - } - } - - DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); - - return pll_locked; -} - -static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) -{ - pll->in.fref = pll->vco_ref_clk_rate; - pll->in.fdata = 0; - pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ - pll->in.ldo_en = 0; /* disabled for now */ - - /* fixed input */ - pll->in.refclk_dbler_en = 0; - pll->in.vco_measure_time = 5; - pll->in.kvco_measure_time = 5; - pll->in.bandgap_timer = 4; - pll->in.pll_wakeup_timer = 5; - pll->in.plllock_cnt = 1; - pll->in.plllock_rng = 0; - - /* - * SSC is enabled by default. We might need DT props for configuring - * some SSC params like PPM and center/down spread etc. - */ - pll->in.ssc_en = 1; - pll->in.ssc_center = 0; /* down spread by default */ - pll->in.ssc_spread = 5; /* PPM / 1000 */ - pll->in.ssc_freq = 31500; /* default recommended */ - pll->in.ssc_adj_period = 37; - - pll->in.pll_ie_trim = 4; - pll->in.pll_ip_trim = 4; - pll->in.pll_cpcset_cur = 1; - pll->in.pll_cpmset_cur = 1; - pll->in.pll_icpmset = 4; - pll->in.pll_icpcset = 4; - pll->in.pll_icpmset_p = 0; - pll->in.pll_icpmset_m = 0; - pll->in.pll_icpcset_p = 0; - pll->in.pll_icpcset_m = 0; - pll->in.pll_lpf_res1 = 3; - pll->in.pll_lpf_cap1 = 11; - pll->in.pll_lpf_cap2 = 1; - pll->in.pll_iptat_trim = 7; - pll->in.pll_c3ctrl = 2; - pll->in.pll_r3ctrl = 1; -} - -#define CEIL(x, y) (((x) + ((y) - 1)) / (y)) - -static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) -{ - u32 period, ssc_period; - u32 ref, rem; - u64 step_size; - - DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate); - - ssc_period = pll->in.ssc_freq / 500; - period = (u32)pll->vco_ref_clk_rate / 1000; - ssc_period = CEIL(period, ssc_period); - ssc_period -= 1; - pll->out.ssc_period = ssc_period; - - DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq, - pll->in.ssc_spread, pll->out.ssc_period); - - step_size = (u32)pll->vco_current_rate; - ref = pll->vco_ref_clk_rate; - ref /= 1000; - step_size = div_u64(step_size, ref); - step_size <<= 20; - step_size = div_u64(step_size, 1000); - step_size *= pll->in.ssc_spread; - step_size = div_u64(step_size, 1000); - step_size *= (pll->in.ssc_adj_period + 1); - - rem = 0; - step_size = div_u64_rem(step_size, ssc_period + 1, &rem); - if (rem) - step_size++; - - DBG("step_size=%lld", step_size); - - step_size &= 0x0ffff; /* take lower 16 bits */ - - pll->out.ssc_step_size = step_size; -} - -static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) -{ - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; - u64 multiplier = BIT(20); - u64 dec_start_multiple, dec_start, pll_comp_val; - u32 duration, div_frac_start; - u64 vco_clk_rate = pll->vco_current_rate; - u64 fref = pll->vco_ref_clk_rate; - - DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); - - dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); - div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); - - dec_start = div_u64(dec_start_multiple, multiplier); - - pout->dec_start = (u32)dec_start; - pout->div_frac_start = div_frac_start; - - if (pin->plllock_cnt == 0) - duration = 1024; - else if (pin->plllock_cnt == 1) - duration = 256; - else if (pin->plllock_cnt == 2) - duration = 128; - else - duration = 32; - - pll_comp_val = duration * dec_start_multiple; - pll_comp_val = div_u64(pll_comp_val, multiplier); - do_div(pll_comp_val, 10); - - pout->plllock_cmp = (u32)pll_comp_val; - - pout->pll_txclk_en = 1; - pout->cmn_ldo_cntrl = 0x3c; -} - -static u32 pll_14nm_kvco_slop(u32 vrate) -{ - u32 slop = 0; - - if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL) - slop = 600; - else if (vrate > 1800000000UL && vrate < 2300000000UL) - slop = 400; - else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE) - slop = 280; - - return slop; -} - -static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) -{ - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; - u64 vco_clk_rate = pll->vco_current_rate; - u64 fref = pll->vco_ref_clk_rate; - u64 data; - u32 cnt; - - data = fref * pin->vco_measure_time; - do_div(data, 1000000); - data &= 0x03ff; /* 10 bits */ - data -= 2; - pout->pll_vco_div_ref = data; - - data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ - data *= pin->vco_measure_time; - do_div(data, 10); - pout->pll_vco_count = data; - - data = fref * pin->kvco_measure_time; - do_div(data, 1000000); - data &= 0x03ff; /* 10 bits */ - data -= 1; - pout->pll_kvco_div_ref = data; - - cnt = pll_14nm_kvco_slop(vco_clk_rate); - cnt *= 2; - cnt /= 100; - cnt *= pin->kvco_measure_time; - pout->pll_kvco_count = cnt; - - pout->pll_misc1 = 16; - pout->pll_resetsm_cntrl = 48; - pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3; - pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer; - pout->pll_kvco_code = 0; -} - -static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) -{ - void __iomem *base = pll->mmio; - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; - u8 data; - - data = pin->ssc_adj_period; - data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); - data = (pin->ssc_adj_period >> 8); - data &= 0x03; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); - - data = pout->ssc_period; - data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); - data = (pout->ssc_period >> 8); - data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); - - data = pout->ssc_step_size; - data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); - data = (pout->ssc_step_size >> 8); - data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); - - data = (pin->ssc_center & 0x01); - data <<= 1; - data |= 0x01; /* enable */ - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); - - wmb(); /* make sure register committed */ -} - -static void pll_db_commit_common(struct dsi_pll_14nm *pll, - struct dsi_pll_input *pin, - struct dsi_pll_output *pout) -{ - void __iomem *base = pll->mmio; - u8 data; - - /* confgiure the non frequency dependent pll registers */ - data = 0; - pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); - - data = pout->pll_txclk_en; - pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); - - data = pout->pll_resetsm_cntrl; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); - data = pout->pll_resetsm_cntrl2; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); - data = pout->pll_resetsm_cntrl5; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); - - data = pout->pll_vco_div_ref & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); - data = (pout->pll_vco_div_ref >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); - - data = pout->pll_kvco_div_ref & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); - data = (pout->pll_kvco_div_ref >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); - - data = pout->pll_misc1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); - - data = pin->pll_ie_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); - - data = pin->pll_ip_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); - - data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur; - pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); - - data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); - - data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); - - data = pin->pll_icpmset << 3 | pin->pll_icpcset; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); - - data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); - - data = pin->pll_iptat_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); - - data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); -} - -static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) -{ - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - - /* de assert pll start and apply pll sw reset */ - - /* stop pll */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); - - /* pll sw reset */ - pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); - wmb(); /* make sure register committed */ - - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); - wmb(); /* make sure register committed */ -} - -static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, - struct dsi_pll_input *pin, - struct dsi_pll_output *pout) -{ - void __iomem *base = pll->mmio; - void __iomem *cmn_base = pll->phy_cmn_mmio; - u8 data; - - DBG("DSI%d PLL", pll->id); - - data = pout->cmn_ldo_cntrl; - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); - - pll_db_commit_common(pll, pin, pout); - - pll_14nm_software_reset(pll); - - data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); - - data = 0xff; /* data, clk, pll normal operation */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); - - /* configure the frequency dependent pll registers */ - data = pout->dec_start; - pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); - - data = pout->div_frac_start & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); - data = (pout->div_frac_start >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); - data = (pout->div_frac_start >> 16) & 0xf; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); - - data = pout->plllock_cmp & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); - - data = (pout->plllock_cmp >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); - - data = (pout->plllock_cmp >> 16) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); - - data = pin->plllock_cnt << 1 | pin->plllock_rng << 3; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); - - data = pout->pll_vco_count & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); - data = (pout->pll_vco_count >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); - - data = pout->pll_kvco_count & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); - data = (pout->pll_kvco_count >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); - - data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); - - if (pin->ssc_en) - pll_db_commit_ssc(pll); - - wmb(); /* make sure register committed */ -} - -/* - * VCO clock Callbacks - */ -static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct dsi_pll_input *pin = &pll_14nm->in; - struct dsi_pll_output *pout = &pll_14nm->out; - - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate, - parent_rate); - - pll_14nm->vco_current_rate = rate; - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - - dsi_pll_14nm_input_init(pll_14nm); - - /* - * This configures the post divider internal to the VCO. It's - * fixed to divide by 1 for now. - * - * tx_band = pll_postdiv. - * 0: divided by 1 - * 1: divided by 2 - * 2: divided by 4 - * 3: divided by 8 - */ - pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV; - - pll_14nm_dec_frac_calc(pll_14nm); - - if (pin->ssc_en) - pll_14nm_ssc_calc(pll_14nm); - - pll_14nm_calc_vco_count(pll_14nm); - - /* commit the slave DSI PLL registers if we're master. Note that we - * don't lock the slave PLL. We just ensure that the PLL/PHY registers - * of the master and slave are identical - */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { - struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - - pll_db_commit_14nm(pll_14nm_slave, pin, pout); - } - - pll_db_commit_14nm(pll_14nm, pin, pout); - - return 0; -} - -static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *base = pll_14nm->mmio; - u64 vco_rate, multiplier = BIT(20); - u32 div_frac_start; - u32 dec_start; - u64 ref_clk = parent_rate; - - dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); - dec_start &= 0x0ff; - - DBG("dec_start = %x", dec_start); - - div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) - & 0xf) << 16; - div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) - & 0xff) << 8; - div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) - & 0xff; - - DBG("div_frac_start = %x", div_frac_start); - - vco_rate = ref_clk * dec_start; - - vco_rate += ((ref_clk * div_frac_start) / multiplier); - - /* - * Recalculating the rate from dec_start and frac_start doesn't end up - * the rate we originally set. Convert the freq to KHz, round it up and - * convert it back to MHz. - */ - vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000; - - DBG("returning vco rate = %lu", (unsigned long)vco_rate); - - return (unsigned long)vco_rate; -} - -static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_14nm_vco_set_rate, - .recalc_rate = dsi_pll_14nm_vco_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, -}; - -/* - * N1 and N2 post-divider clock callbacks - */ -#define div_mask(width) ((1 << (width)) - 1) -static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); - struct dsi_pll_14nm *pll_14nm = postdiv->pll; - void __iomem *base = pll_14nm->phy_cmn_mmio; - u8 shift = postdiv->shift; - u8 width = postdiv->width; - u32 val; - - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate); - - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; - val &= div_mask(width); - - return divider_recalc_rate(hw, parent_rate, val, NULL, - postdiv->flags, width); -} - -static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) -{ - struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); - struct dsi_pll_14nm *pll_14nm = postdiv->pll; - - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate); - - return divider_round_rate(hw, rate, prate, NULL, - postdiv->width, - postdiv->flags); -} - -static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); - struct dsi_pll_14nm *pll_14nm = postdiv->pll; - void __iomem *base = pll_14nm->phy_cmn_mmio; - spinlock_t *lock = &pll_14nm->postdiv_lock; - u8 shift = postdiv->shift; - u8 width = postdiv->width; - unsigned int value; - unsigned long flags = 0; - u32 val; - - DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate, - parent_rate); - - value = divider_get_val(rate, parent_rate, NULL, postdiv->width, - postdiv->flags); - - spin_lock_irqsave(lock, flags); - - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); - val &= ~(div_mask(width) << shift); - - val |= value << shift; - pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); - - /* If we're master in dual DSI mode, then the slave PLL's post-dividers - * follow the master's post dividers - */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { - struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; - - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); - } - - spin_unlock_irqrestore(lock, flags); - - return 0; -} - -static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { - .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, - .round_rate = dsi_pll_14nm_postdiv_round_rate, - .set_rate = dsi_pll_14nm_postdiv_set_rate, -}; - -/* - * PLL Callbacks - */ - -static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *base = pll_14nm->mmio; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - bool locked; - - DBG(""); - - pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); - - locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, - POLL_TIMEOUT_US); - - if (unlikely(!locked)) - DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); - - return locked ? 0 : -EINVAL; -} - -static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - - DBG(""); - - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); -} - -static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - u32 data; - - data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); - - cached_state->n1postdiv = data & 0xf; - cached_state->n2postdiv = (data >> 4) & 0xf; - - DBG("DSI%d PLL save state %x %x", pll_14nm->id, - cached_state->n1postdiv, cached_state->n2postdiv); - - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); -} - -static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - u32 data; - int ret; - - ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, - cached_state->vco_rate, 0); - if (ret) { - DRM_DEV_ERROR(&pll_14nm->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); - return ret; - } - - data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); - - DBG("DSI%d PLL restore state %x %x", pll_14nm->id, - cached_state->n1postdiv, cached_state->n2postdiv); - - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); - - /* also restore post-dividers for slave DSI PLL */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { - struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; - - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); - } - - return 0; -} - -static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *base = pll_14nm->mmio; - u32 clkbuflr_en, bandgap = 0; - - switch (uc) { - case MSM_DSI_PHY_STANDALONE: - clkbuflr_en = 0x1; - break; - case MSM_DSI_PHY_MASTER: - clkbuflr_en = 0x3; - pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX]; - break; - case MSM_DSI_PHY_SLAVE: - clkbuflr_en = 0x0; - bandgap = 0x3; - break; - default: - return -EINVAL; - } - - pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); - if (bandgap) - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); - - pll_14nm->uc = uc; - - return 0; -} - -static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data; - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - -static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct platform_device *pdev = pll_14nm->pdev; - int num_hws = pll_14nm->num_hws; - - of_clk_del_provider(pdev->dev.of_node); - - while (num_hws--) - clk_hw_unregister(pll_14nm->hws[num_hws]); -} - -static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, - const char *name, - const char *parent_name, - unsigned long flags, - u8 shift) -{ - struct dsi_pll_14nm_postdiv *pll_postdiv; - struct device *dev = &pll_14nm->pdev->dev; - struct clk_init_data postdiv_init = { - .parent_names = (const char *[]) { parent_name }, - .num_parents = 1, - .name = name, - .flags = flags, - .ops = &clk_ops_dsi_pll_14nm_postdiv, - }; - int ret; - - pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL); - if (!pll_postdiv) - return ERR_PTR(-ENOMEM); - - pll_postdiv->pll = pll_14nm; - pll_postdiv->shift = shift; - /* both N1 and N2 postdividers are 4 bits wide */ - pll_postdiv->width = 4; - /* range of each divider is from 1 to 15 */ - pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; - pll_postdiv->hw.init = &postdiv_init; - - ret = clk_hw_register(dev, &pll_postdiv->hw); - if (ret) - return ERR_PTR(ret); - - return &pll_postdiv->hw; -} - -static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) -{ - char clk_name[32], parent[32], vco_name[32]; - struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .name = vco_name, - .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_14nm_vco, - }; - struct device *dev = &pll_14nm->pdev->dev; - struct clk_hw **hws = pll_14nm->hws; - struct clk_hw_onecell_data *hw_data; - struct clk_hw *hw; - int num = 0; - int ret; - - DBG("DSI%d", pll_14nm->id); - - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); - pll_14nm->base.clk_hw.init = &vco_init; - - ret = clk_hw_register(dev, &pll_14nm->base.clk_hw); - if (ret) - return ret; - - hws[num++] = &pll_14nm->base.clk_hw; - - snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id); - - /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ - hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, - CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - - snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); - - /* DSI Byte clock = VCO_CLK / N1 / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; - - snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); - - /* - * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider - * on the way. Don't let it set parent. - */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - - snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); - - /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 - * This is the output of N2 post-divider, bits 4-7 in - * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. - */ - hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; - - pll_14nm->num_hws = num; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_14nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_14nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) -{ - struct dsi_pll_14nm *pll_14nm; - struct msm_dsi_pll *pll; - int ret; - - if (!pdev) - return ERR_PTR(-ENODEV); - - pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); - if (!pll_14nm) - return ERR_PTR(-ENOMEM); - - DBG("PLL%d", id); - - pll_14nm->pdev = pdev; - pll_14nm->id = id; - pll_14nm_list[id] = pll_14nm; - - pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); - } - - pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_14nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); - } - - spin_lock_init(&pll_14nm->postdiv_lock); - - pll = &pll_14nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_14nm_get_provider; - pll->destroy = dsi_pll_14nm_destroy; - pll->disable_seq = dsi_pll_14nm_disable_seq; - pll->save_state = dsi_pll_14nm_save_state; - pll->restore_state = dsi_pll_14nm_restore_state; - pll->set_usecase = dsi_pll_14nm_set_usecase; - - pll_14nm->vco_delay = 1; - - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; - - ret = pll_14nm_register(pll_14nm); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - return pll; -} diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c deleted file mode 100644 index 37a1f996a588..000000000000 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ /dev/null @@ -1,643 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include - -#include "dsi_pll.h" -#include "dsi.xml.h" - -/* - * DSI PLL 28nm - clock diagram (eg: DSI0): - * - * dsi0analog_postdiv_clk - * | dsi0indirect_path_div2_clk - * | | - * +------+ | +----+ | |\ dsi0byte_mux - * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ | - * | +------+ +----+ | m| | +----+ - * | | u|--o--| /4 |-- dsi0pllbyte - * | | x| +----+ - * o--------------------------| / - * | |/ - * | +------+ - * o----------| DIV3 |------------------------- dsi0pll - * +------+ - */ - -#define POLL_MAX_READS 10 -#define POLL_TIMEOUT_US 50 - -#define NUM_PROVIDED_CLKS 2 - -#define VCO_REF_CLK_RATE 19200000 -#define VCO_MIN_RATE 350000000 -#define VCO_MAX_RATE 750000000 - -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - -#define LPFR_LUT_SIZE 10 -struct lpfr_cfg { - unsigned long vco_rate; - u32 resistance; -}; - -/* Loop filter resistance: */ -static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = { - { 479500000, 8 }, - { 480000000, 11 }, - { 575500000, 8 }, - { 576000000, 12 }, - { 610500000, 8 }, - { 659500000, 9 }, - { 671500000, 10 }, - { 672000000, 14 }, - { 708500000, 10 }, - { 750000000, 11 }, -}; - -struct pll_28nm_cached_state { - unsigned long vco_rate; - u8 postdiv3; - u8 postdiv1; - u8 byte_mux; -}; - -struct dsi_pll_28nm { - struct msm_dsi_pll base; - - int id; - struct platform_device *pdev; - void __iomem *mmio; - - int vco_delay; - - /* private clocks: */ - struct clk *clks[NUM_DSI_CLOCKS_MAX]; - u32 num_clks; - - /* clock-provider: */ - struct clk *provided_clks[NUM_PROVIDED_CLKS]; - struct clk_onecell_data clk_data; - - struct pll_28nm_cached_state cached_state; -}; - -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) - -static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, - u32 nb_tries, u32 timeout_us) -{ - bool pll_locked = false; - u32 val; - - while (nb_tries--) { - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); - pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); - - if (pll_locked) - break; - - udelay(timeout_us); - } - DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); - - return pll_locked; -} - -static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) -{ - void __iomem *base = pll_28nm->mmio; - - /* - * Add HW recommended delays after toggling the software - * reset bit off and back on. - */ - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, - DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1); - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); -} - -/* - * Clock Callbacks - */ -static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; - unsigned long div_fbx1000, gen_vco_clk; - u32 refclk_cfg, frac_n_mode, frac_n_value; - u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; - u32 cal_cfg10, cal_cfg11; - u32 rem; - int i; - - VERB("rate=%lu, parent's=%lu", rate, parent_rate); - - /* Force postdiv2 to be div-4 */ - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); - - /* Configure the Loop filter resistance */ - for (i = 0; i < LPFR_LUT_SIZE; i++) - if (rate <= lpfr_lut[i].vco_rate) - break; - if (i == LPFR_LUT_SIZE) { - DRM_DEV_ERROR(dev, "unable to get loop filter resistance. vco=%lu\n", - rate); - return -EINVAL; - } - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); - - /* Loop filter capacitance values : c1 and c2 */ - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); - - rem = rate % VCO_REF_CLK_RATE; - if (rem) { - refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - frac_n_mode = 1; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); - } else { - refclk_cfg = 0x0; - frac_n_mode = 0; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); - } - - DBG("refclk_cfg = %d", refclk_cfg); - - rem = div_fbx1000 % 1000; - frac_n_value = (rem << 16) / 1000; - - DBG("div_fb = %lu", div_fbx1000); - DBG("frac_n_value = %d", frac_n_value); - - DBG("Generated VCO Clock: %lu", gen_vco_clk); - rem = 0; - sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); - sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; - if (frac_n_mode) { - sdm_cfg0 = 0x0; - sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); - sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( - (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); - sdm_cfg3 = frac_n_value >> 8; - sdm_cfg2 = frac_n_value & 0xff; - } else { - sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; - sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( - (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); - sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); - sdm_cfg2 = 0; - sdm_cfg3 = 0; - } - - DBG("sdm_cfg0=%d", sdm_cfg0); - DBG("sdm_cfg1=%d", sdm_cfg1); - DBG("sdm_cfg2=%d", sdm_cfg2); - DBG("sdm_cfg3=%d", sdm_cfg3); - - cal_cfg11 = (u32)(gen_vco_clk / (256 * 1000000)); - cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000); - DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); - - pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); - - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, - DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2)); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, - DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3)); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); - - /* Add hardware recommended delay for correct PLL configuration */ - if (pll_28nm->vco_delay) - udelay(pll_28nm->vco_delay); - - pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); - pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); - pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); - - return 0; -} - -static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, - POLL_TIMEOUT_US); -} - -static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - void __iomem *base = pll_28nm->mmio; - u32 sdm0, doubler, sdm_byp_div; - u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; - u32 ref_clk = VCO_REF_CLK_RATE; - unsigned long vco_rate; - - VERB("parent_rate=%lu", parent_rate); - - /* Check to see if the ref clk doubler is enabled */ - doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & - DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - ref_clk += (doubler * VCO_REF_CLK_RATE); - - /* see if it is integer mode or sdm mode */ - sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); - if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { - /* integer mode */ - sdm_byp_div = FIELD( - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), - DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; - vco_rate = ref_clk * sdm_byp_div; - } else { - /* sdm mode */ - sdm_dc_off = FIELD( - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), - DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET); - DBG("sdm_dc_off = %d", sdm_dc_off); - sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), - DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0); - sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), - DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8); - sdm_freq_seed = (sdm3 << 8) | sdm2; - DBG("sdm_freq_seed = %d", sdm_freq_seed); - - vco_rate = (ref_clk * (sdm_dc_off + 1)) + - mult_frac(ref_clk, sdm_freq_seed, BIT(16)); - DBG("vco rate = %lu", vco_rate); - } - - DBG("returning vco rate = %lu", vco_rate); - - return vco_rate; -} - -static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_28nm_clk_set_rate, - .recalc_rate = dsi_pll_28nm_clk_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, - .is_enabled = dsi_pll_28nm_clk_is_enabled, -}; - -/* - * PLL Callbacks - */ -static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; - u32 max_reads = 5, timeout_us = 100; - bool locked; - u32 val; - int i; - - DBG("id=%d", pll_28nm->id); - - pll_28nm_software_reset(pll_28nm); - - /* - * PLL power up sequence. - * Add necessary delays recommended by hardware. - */ - val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); - - for (i = 0; i < 2; i++) { - /* DSI Uniphy lock detect setting */ - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, - 0x0c, 100); - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); - - /* poll for PLL ready status */ - locked = pll_28nm_poll_for_ready(pll_28nm, - max_reads, timeout_us); - if (locked) - break; - - pll_28nm_software_reset(pll_28nm); - - /* - * PLL power up sequence. - * Add necessary delays recommended by hardware. - */ - val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); - - val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); - } - - if (unlikely(!locked)) - DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL Lock success"); - - return locked ? 0 : -EINVAL; -} - -static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; - bool locked; - u32 max_reads = 10, timeout_us = 50; - u32 val; - - DBG("id=%d", pll_28nm->id); - - pll_28nm_software_reset(pll_28nm); - - /* - * PLL power up sequence. - * Add necessary delays recommended by hardware. - */ - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); - - val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); - - val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | - DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); - - /* DSI PLL toggle lock detect setting */ - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); - - locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); - - if (unlikely(!locked)) - DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); - - return locked ? 0 : -EINVAL; -} - -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - DBG("id=%d", pll_28nm->id); - pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); -} - -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; - - cached_state->postdiv3 = - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); - cached_state->postdiv1 = - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); - cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); - if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw)) - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); - else - cached_state->vco_rate = 0; -} - -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; - int ret; - - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, - cached_state->vco_rate, 0); - if (ret) { - DRM_DEV_ERROR(&pll_28nm->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); - return ret; - } - - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, - cached_state->postdiv3); - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, - cached_state->postdiv1); - pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, - cached_state->byte_mux); - - return 0; -} - -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - if (byte_clk_provider) - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; - if (pixel_clk_provider) - *pixel_clk_provider = - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; - - return 0; -} - -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - int i; - - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, - pll_28nm->clks, pll_28nm->num_clks); - - for (i = 0; i < NUM_PROVIDED_CLKS; i++) - pll_28nm->provided_clks[i] = NULL; - - pll_28nm->num_clks = 0; - pll_28nm->clk_data.clks = NULL; - pll_28nm->clk_data.clk_num = 0; -} - -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) -{ - char clk_name[32], parent1[32], parent2[32], vco_name[32]; - struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .name = vco_name, - .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_28nm_vco, - }; - struct device *dev = &pll_28nm->pdev->dev; - struct clk **clks = pll_28nm->clks; - struct clk **provided_clks = pll_28nm->provided_clks; - int num = 0; - int ret; - - DBG("%d", pll_28nm->id); - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); - pll_28nm->base.clk_hw.init = &vco_init; - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); - - snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = clk_register_divider(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, - pll_28nm->mmio + - REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, - 0, 4, 0, NULL); - - snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); - snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); - clks[num++] = clk_register_fixed_factor(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, - 1, 2); - - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = - clk_register_divider(dev, clk_name, - parent1, 0, pll_28nm->mmio + - REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, - 0, 8, 0, NULL); - - snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); - clks[num++] = clk_register_mux(dev, clk_name, - ((const char *[]){ - parent1, parent2 - }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + - REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); - - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); - snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = - clk_register_fixed_factor(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, 1, 4); - - pll_28nm->num_clks = num; - - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; - pll_28nm->clk_data.clks = provided_clks; - - ret = of_clk_add_provider(dev->of_node, - of_clk_src_onecell_get, &pll_28nm->clk_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) -{ - struct dsi_pll_28nm *pll_28nm; - struct msm_dsi_pll *pll; - int ret; - - if (!pdev) - return ERR_PTR(-ENODEV); - - pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); - if (!pll_28nm) - return ERR_PTR(-ENOMEM); - - pll_28nm->pdev = pdev; - pll_28nm->id = id; - - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_28nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return ERR_PTR(-ENOMEM); - } - - pll = &pll_28nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_28nm_get_provider; - pll->destroy = dsi_pll_28nm_destroy; - pll->disable_seq = dsi_pll_28nm_disable_seq; - pll->save_state = dsi_pll_28nm_save_state; - pll->restore_state = dsi_pll_28nm_restore_state; - - if (type == MSM_DSI_PHY_28NM_HPM) { - pll_28nm->vco_delay = 1; - - pll->en_seq_cnt = 3; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm; - pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm; - pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm; - } else if (type == MSM_DSI_PHY_28NM_LP) { - pll_28nm->vco_delay = 1000; - - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp; - } else { - DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type); - return ERR_PTR(-EINVAL); - } - - ret = pll_28nm_register(pll_28nm); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - return pll; -} - diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c deleted file mode 100644 index a6e7a2525fe0..000000000000 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ /dev/null @@ -1,526 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. - */ - -#include - -#include "dsi_pll.h" -#include "dsi.xml.h" - -/* - * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1): - * - * - * +------+ - * dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock) - * F * byte_clk | +------+ - * | bit clock divider (F / 8) - * | - * | +------+ - * o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG - * | +------+ | (sets parent rate) - * | byte clock divider (F) | - * | | - * | o---> To esc RCG - * | (doesn't set parent rate) - * | - * | +------+ - * o-----| DIV3 |----dsi0pll------o---> To dsi RCG - * +------+ | (sets parent rate) - * dsi clock divider (F * magic) | - * | - * o---> To pixel rcg - * (doesn't set parent rate) - */ - -#define POLL_MAX_READS 8000 -#define POLL_TIMEOUT_US 1 - -#define NUM_PROVIDED_CLKS 2 - -#define VCO_REF_CLK_RATE 27000000 -#define VCO_MIN_RATE 600000000 -#define VCO_MAX_RATE 1200000000 - -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - -#define VCO_PREF_DIV_RATIO 27 - -struct pll_28nm_cached_state { - unsigned long vco_rate; - u8 postdiv3; - u8 postdiv2; - u8 postdiv1; -}; - -struct clk_bytediv { - struct clk_hw hw; - void __iomem *reg; -}; - -struct dsi_pll_28nm { - struct msm_dsi_pll base; - - int id; - struct platform_device *pdev; - void __iomem *mmio; - - /* custom byte clock divider */ - struct clk_bytediv *bytediv; - - /* private clocks: */ - struct clk *clks[NUM_DSI_CLOCKS_MAX]; - u32 num_clks; - - /* clock-provider: */ - struct clk *provided_clks[NUM_PROVIDED_CLKS]; - struct clk_onecell_data clk_data; - - struct pll_28nm_cached_state cached_state; -}; - -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) - -static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, - int nb_tries, int timeout_us) -{ - bool pll_locked = false; - u32 val; - - while (nb_tries--) { - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); - pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); - - if (pll_locked) - break; - - udelay(timeout_us); - } - DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); - - return pll_locked; -} - -/* - * Clock Callbacks - */ -static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - void __iomem *base = pll_28nm->mmio; - u32 val, temp, fb_divider; - - DBG("rate=%lu, parent's=%lu", rate, parent_rate); - - temp = rate / 10; - val = VCO_REF_CLK_RATE / 10; - fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; - fb_divider = fb_divider / 2 - 1; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, - fb_divider & 0xff); - - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); - - val |= (fb_divider >> 8) & 0x07; - - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, - val); - - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); - - val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f; - - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, - val); - - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, - 0xf); - - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - val |= 0x7 << 4; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, - val); - - return 0; -} - -static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, - POLL_TIMEOUT_US); -} - -static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - void __iomem *base = pll_28nm->mmio; - unsigned long vco_rate; - u32 status, fb_divider, temp, ref_divider; - - VERB("parent_rate=%lu", parent_rate); - - status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); - - if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) { - fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); - fb_divider &= 0xff; - temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; - fb_divider = (temp << 8) | fb_divider; - fb_divider += 1; - - ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); - ref_divider &= 0x3f; - ref_divider += 1; - - /* multiply by 2 */ - vco_rate = (parent_rate / ref_divider) * fb_divider * 2; - } else { - vco_rate = 0; - } - - DBG("returning vco rate = %lu", vco_rate); - - return vco_rate; -} - -static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_28nm_clk_set_rate, - .recalc_rate = dsi_pll_28nm_clk_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, - .is_enabled = dsi_pll_28nm_clk_is_enabled, -}; - -/* - * Custom byte clock divier clk_ops - * - * This clock is the entry point to configuring the PLL. The user (dsi host) - * will set this clock's rate to the desired byte clock rate. The VCO lock - * frequency is a multiple of the byte clock rate. The multiplication factor - * (shown as F in the diagram above) is a function of the byte clock rate. - * - * This custom divider clock ensures that its parent (VCO) is set to the - * desired rate, and that the byte clock postdivider (POSTDIV2) is configured - * accordingly - */ -#define to_clk_bytediv(_hw) container_of(_hw, struct clk_bytediv, hw) - -static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_bytediv *bytediv = to_clk_bytediv(hw); - unsigned int div; - - div = pll_read(bytediv->reg) & 0xff; - - return parent_rate / (div + 1); -} - -/* find multiplication factor(wrt byte clock) at which the VCO should be set */ -static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate) -{ - unsigned long bit_mhz; - - /* convert to bit clock in Mhz */ - bit_mhz = (byte_clk_rate * 8) / 1000000; - - if (bit_mhz < 125) - return 64; - else if (bit_mhz < 250) - return 32; - else if (bit_mhz < 600) - return 16; - else - return 8; -} - -static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long best_parent; - unsigned int factor; - - factor = get_vco_mul_factor(rate); - - best_parent = rate * factor; - *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); - - return *prate / factor; -} - -static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_bytediv *bytediv = to_clk_bytediv(hw); - u32 val; - unsigned int factor; - - factor = get_vco_mul_factor(rate); - - val = pll_read(bytediv->reg); - val |= (factor - 1) & 0xff; - pll_write(bytediv->reg, val); - - return 0; -} - -/* Our special byte clock divider ops */ -static const struct clk_ops clk_bytediv_ops = { - .round_rate = clk_bytediv_round_rate, - .set_rate = clk_bytediv_set_rate, - .recalc_rate = clk_bytediv_recalc_rate, -}; - -/* - * PLL Callbacks - */ -static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; - bool locked; - unsigned int bit_div, byte_div; - int max_reads = 1000, timeout_us = 100; - u32 val; - - DBG("id=%d", pll_28nm->id); - - /* - * before enabling the PLL, configure the bit clock divider since we - * don't expose it as a clock to the outside world - * 1: read back the byte clock divider that should already be set - * 2: divide by 8 to get bit clock divider - * 3: write it to POSTDIV1 - */ - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); - byte_div = val + 1; - bit_div = byte_div / 8; - - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - val &= ~0xf; - val |= (bit_div - 1); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); - - /* enable the PLL */ - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, - DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); - - locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); - - if (unlikely(!locked)) - DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); - - return locked ? 0 : -EINVAL; -} - -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - DBG("id=%d", pll_28nm->id); - pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); -} - -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; - - cached_state->postdiv3 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); - cached_state->postdiv2 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); - cached_state->postdiv1 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); -} - -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; - int ret; - - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, - cached_state->vco_rate, 0); - if (ret) { - DRM_DEV_ERROR(&pll_28nm->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); - return ret; - } - - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, - cached_state->postdiv3); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, - cached_state->postdiv2); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, - cached_state->postdiv1); - - return 0; -} - -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - if (byte_clk_provider) - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; - if (pixel_clk_provider) - *pixel_clk_provider = - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; - - return 0; -} - -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, - pll_28nm->clks, pll_28nm->num_clks); -} - -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) -{ - char *clk_name, *parent_name, *vco_name; - struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_28nm_vco, - }; - struct device *dev = &pll_28nm->pdev->dev; - struct clk **clks = pll_28nm->clks; - struct clk **provided_clks = pll_28nm->provided_clks; - struct clk_bytediv *bytediv; - struct clk_init_data bytediv_init = { }; - int ret, num = 0; - - DBG("%d", pll_28nm->id); - - bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL); - if (!bytediv) - return -ENOMEM; - - vco_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!vco_name) - return -ENOMEM; - - parent_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!parent_name) - return -ENOMEM; - - clk_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!clk_name) - return -ENOMEM; - - pll_28nm->bytediv = bytediv; - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); - vco_init.name = vco_name; - - pll_28nm->base.clk_hw.init = &vco_init; - - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); - - /* prepare and register bytediv */ - bytediv->hw.init = &bytediv_init; - bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; - - snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); - - bytediv_init.name = clk_name; - bytediv_init.ops = &clk_bytediv_ops; - bytediv_init.flags = CLK_SET_RATE_PARENT; - bytediv_init.parent_names = (const char * const *) &parent_name; - bytediv_init.num_parents = 1; - - /* DIV2 */ - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = - clk_register(dev, &bytediv->hw); - - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); - /* DIV3 */ - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = - clk_register_divider(dev, clk_name, - parent_name, 0, pll_28nm->mmio + - REG_DSI_28nm_8960_PHY_PLL_CTRL_10, - 0, 8, 0, NULL); - - pll_28nm->num_clks = num; - - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; - pll_28nm->clk_data.clks = provided_clks; - - ret = of_clk_add_provider(dev->of_node, - of_clk_src_onecell_get, &pll_28nm->clk_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, - int id) -{ - struct dsi_pll_28nm *pll_28nm; - struct msm_dsi_pll *pll; - int ret; - - if (!pdev) - return ERR_PTR(-ENODEV); - - pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); - if (!pll_28nm) - return ERR_PTR(-ENOMEM); - - pll_28nm->pdev = pdev; - pll_28nm->id = id + 1; - - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_28nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return ERR_PTR(-ENOMEM); - } - - pll = &pll_28nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_28nm_get_provider; - pll->destroy = dsi_pll_28nm_destroy; - pll->disable_seq = dsi_pll_28nm_disable_seq; - pll->save_state = dsi_pll_28nm_save_state; - pll->restore_state = dsi_pll_28nm_restore_state; - - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq; - - ret = pll_28nm_register(pll_28nm); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - return pll; -} diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c deleted file mode 100644 index e29b3bfd63d1..000000000000 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ /dev/null @@ -1,913 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 - * Copyright (c) 2018, The Linux Foundation - */ - -#include -#include -#include - -#include "dsi_pll.h" -#include "dsi.xml.h" - -/* - * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram - * - * dsi0_pll_out_div_clk dsi0_pll_bit_clk - * | | - * | | - * +---------+ | +----------+ | +----+ - * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk - * +---------+ | +----------+ | +----+ - * | | - * | | dsi0_pll_by_2_bit_clk - * | | | - * | | +----+ | |\ dsi0_pclk_mux - * | |--| /2 |--o--| \ | - * | | +----+ | \ | +---------+ - * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk - * |------------------------------| / +---------+ - * | +-----+ | / - * -----------| /4? |--o----------|/ - * +-----+ | | - * | |dsiclk_sel - * | - * dsi0_pll_post_out_div_clk - */ - -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 -#define NUM_PROVIDED_CLKS 2 - -#define VCO_REF_CLK_RATE 19200000 - -struct dsi_pll_regs { - u32 pll_prop_gain_rate; - u32 pll_lockdet_rate; - u32 decimal_div_start; - u32 frac_div_start_low; - u32 frac_div_start_mid; - u32 frac_div_start_high; - u32 pll_clock_inverters; - u32 ssc_stepsize_low; - u32 ssc_stepsize_high; - u32 ssc_div_per_low; - u32 ssc_div_per_high; - u32 ssc_adjper_low; - u32 ssc_adjper_high; - u32 ssc_control; -}; - -struct dsi_pll_config { - u32 ref_freq; - bool div_override; - u32 output_div; - bool ignore_frac; - bool disable_prescaler; - bool enable_ssc; - bool ssc_center; - u32 dec_bits; - u32 frac_bits; - u32 lock_timer; - u32 ssc_freq; - u32 ssc_offset; - u32 ssc_adj_per; - u32 thresh_cycles; - u32 refclk_cycles; -}; - -struct pll_7nm_cached_state { - unsigned long vco_rate; - u8 bit_clk_div; - u8 pix_clk_div; - u8 pll_out_div; - u8 pll_mux; -}; - -struct dsi_pll_7nm { - struct msm_dsi_pll base; - - int id; - struct platform_device *pdev; - - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - - u64 vco_ref_clk_rate; - u64 vco_current_rate; - - /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ - spinlock_t postdiv_lock; - - int vco_delay; - struct dsi_pll_config pll_configuration; - struct dsi_pll_regs reg_setup; - - /* private clocks: */ - struct clk_hw *out_div_clk_hw; - struct clk_hw *bit_clk_hw; - struct clk_hw *byte_clk_hw; - struct clk_hw *by_2_bit_clk_hw; - struct clk_hw *post_out_div_clk_hw; - struct clk_hw *pclk_mux_hw; - struct clk_hw *out_dsiclk_hw; - - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - - struct pll_7nm_cached_state cached_state; - - enum msm_dsi_phy_usecase uc; - struct dsi_pll_7nm *slave; -}; - -#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base) - -/* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI - * mode, where the master PLL's clk_ops needs access the slave's private data - */ -static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; - -static void dsi_pll_setup_config(struct dsi_pll_7nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - - config->ref_freq = pll->vco_ref_clk_rate; - config->output_div = 1; - config->dec_bits = 8; - config->frac_bits = 18; - config->lock_timer = 64; - config->ssc_freq = 31500; - config->ssc_offset = 4800; - config->ssc_adj_per = 2; - config->thresh_cycles = 32; - config->refclk_cycles = 256; - - config->div_override = false; - config->ignore_frac = false; - config->disable_prescaler = false; - - /* TODO: ssc enable */ - config->enable_ssc = false; - config->ssc_center = 0; -} - -static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u64 fref = pll->vco_ref_clk_rate; - u64 pll_freq; - u64 divider; - u64 dec, dec_multiple; - u32 frac; - u64 multiplier; - - pll_freq = pll->vco_current_rate; - - if (config->disable_prescaler) - divider = fref; - else - divider = fref * 2; - - multiplier = 1 << config->frac_bits; - dec_multiple = div_u64(pll_freq * multiplier, divider); - div_u64_rem(dec_multiple, multiplier, &frac); - - dec = div_u64(dec_multiple, multiplier); - - if (pll->base.type != MSM_DSI_PHY_7NM_V4_1) - regs->pll_clock_inverters = 0x28; - else if (pll_freq <= 1000000000ULL) - regs->pll_clock_inverters = 0xa0; - else if (pll_freq <= 2500000000ULL) - regs->pll_clock_inverters = 0x20; - else if (pll_freq <= 3020000000ULL) - regs->pll_clock_inverters = 0x00; - else - regs->pll_clock_inverters = 0x40; - - regs->pll_lockdet_rate = config->lock_timer; - regs->decimal_div_start = dec; - regs->frac_div_start_low = (frac & 0xff); - regs->frac_div_start_mid = (frac & 0xff00) >> 8; - regs->frac_div_start_high = (frac & 0x30000) >> 16; -} - -#define SSC_CENTER BIT(0) -#define SSC_EN BIT(1) - -static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) -{ - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u32 ssc_per; - u32 ssc_mod; - u64 ssc_step_size; - u64 frac; - - if (!config->enable_ssc) { - DBG("SSC not enabled\n"); - return; - } - - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; - ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); - ssc_per -= ssc_mod; - - frac = regs->frac_div_start_low | - (regs->frac_div_start_mid << 8) | - (regs->frac_div_start_high << 16); - ssc_step_size = regs->decimal_div_start; - ssc_step_size *= (1 << config->frac_bits); - ssc_step_size += frac; - ssc_step_size *= config->ssc_offset; - ssc_step_size *= (config->ssc_adj_per + 1); - ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); - ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); - - regs->ssc_div_per_low = ssc_per & 0xFF; - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; - - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; - - pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", - regs->decimal_div_start, frac, config->frac_bits); - pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", - ssc_per, (u32)ssc_step_size, config->ssc_adj_per); -} - -static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) -{ - void __iomem *base = pll->mmio; - struct dsi_pll_regs *regs = &pll->reg_setup; - - if (pll->pll_configuration.enable_ssc) { - pr_debug("SSC is enabled\n"); - - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - regs->ssc_stepsize_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - regs->ssc_stepsize_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, - regs->ssc_div_per_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - regs->ssc_div_per_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, - regs->ssc_adjper_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, - regs->ssc_adjper_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, - SSC_EN | regs->ssc_control); - } -} - -static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) -{ - void __iomem *base = pll->mmio; - u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { - if (pll->vco_current_rate >= 3100000000ULL) - analog_controls_five_1 = 0x03; - - if (pll->vco_current_rate < 1520000000ULL) - vco_config_1 = 0x08; - else if (pll->vco_current_rate < 2990000000ULL) - vco_config_1 = 0x01; - } - - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, - analog_controls_five_1); - pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); - pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); - - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { - pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); - if (pll->slave) - pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); - } -} - -static void dsi_pll_commit(struct dsi_pll_7nm *pll) -{ - void __iomem *base = pll->mmio; - struct dsi_pll_regs *reg = &pll->reg_setup; - - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ - pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); -} - -static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate, - parent_rate); - - pll_7nm->vco_current_rate = rate; - pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - - dsi_pll_setup_config(pll_7nm); - - dsi_pll_calc_dec_frac(pll_7nm); - - dsi_pll_calc_ssc(pll_7nm); - - dsi_pll_commit(pll_7nm); - - dsi_pll_config_hzindep_reg(pll_7nm); - - dsi_pll_ssc_commit(pll_7nm); - - /* flush, ensure all register writes are done*/ - wmb(); - - return 0; -} - -static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) -{ - int rc; - u32 status = 0; - u32 const delay_us = 100; - u32 const timeout_us = 5000; - - rc = readl_poll_timeout_atomic(pll->mmio + - REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE, - status, - ((status & BIT(0)) > 0), - delay_us, - timeout_us); - if (rc) - pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", - pll->id, status); - - return rc; -} - -static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) -{ - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); - - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); - ndelay(250); -} - -static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) -{ - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); - - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); - ndelay(250); -} - -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) -{ - u32 data; - - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); -} - -static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) -{ - u32 data; - - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); - - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, - data | BIT(5) | BIT(4)); -} - -static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) -{ - /* - * Reset the PHY digital domain. This would be needed when - * coming out of a CX or analog rail power collapse while - * ensuring that the pads maintain LP00 or LP11 state - */ - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); - wmb(); /* Ensure that the reset is deasserted */ - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); - wmb(); /* Ensure that the reset is deasserted */ -} - -static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - int rc; - - dsi_pll_enable_pll_bias(pll_7nm); - if (pll_7nm->slave) - dsi_pll_enable_pll_bias(pll_7nm->slave); - - /* Start PLL */ - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); - - /* - * ensure all PLL configurations are written prior to checking - * for PLL lock. - */ - wmb(); - - /* Check for PLL lock */ - rc = dsi_pll_7nm_lock_status(pll_7nm); - if (rc) { - pr_err("PLL(%d) lock failed\n", pll_7nm->id); - goto error; - } - - pll->pll_on = true; - - /* - * assert power on reset for PHY digital in case the PLL is - * enabled after CX of analog domain power collapse. This needs - * to be done before enabling the global clk. - */ - dsi_pll_phy_dig_reset(pll_7nm); - if (pll_7nm->slave) - dsi_pll_phy_dig_reset(pll_7nm->slave); - - dsi_pll_enable_global_clk(pll_7nm); - if (pll_7nm->slave) - dsi_pll_enable_global_clk(pll_7nm->slave); - -error: - return rc; -} - -static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) -{ - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); - dsi_pll_disable_pll_bias(pll); -} - -static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - - /* - * To avoid any stray glitches while abruptly powering down the PLL - * make sure to gate the clock using the clock enable bit before - * powering down the PLL - */ - dsi_pll_disable_global_clk(pll_7nm); - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); - dsi_pll_disable_sub(pll_7nm); - if (pll_7nm->slave) { - dsi_pll_disable_global_clk(pll_7nm->slave); - dsi_pll_disable_sub(pll_7nm->slave); - } - /* flush, ensure all register writes are done */ - wmb(); - pll->pll_on = false; -} - -static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct dsi_pll_config *config = &pll_7nm->pll_configuration; - void __iomem *base = pll_7nm->mmio; - u64 ref_clk = pll_7nm->vco_ref_clk_rate; - u64 vco_rate = 0x0; - u64 multiplier; - u32 frac; - u32 dec; - u64 pll_freq, tmp64; - - dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); - dec &= 0xff; - - frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & - 0xff) << 8); - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & - 0x3) << 16); - - /* - * TODO: - * 1. Assumes prescaler is disabled - */ - multiplier = 1 << config->frac_bits; - pll_freq = dec * (ref_clk * 2); - tmp64 = (ref_clk * 2 * frac); - pll_freq += div_u64(tmp64, multiplier); - - vco_rate = pll_freq; - - DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", - pll_7nm->id, (unsigned long)vco_rate, dec, frac); - - return (unsigned long)vco_rate; -} - -static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_7nm_vco_set_rate, - .recalc_rate = dsi_pll_7nm_vco_recalc_rate, - .prepare = dsi_pll_7nm_vco_prepare, - .unprepare = dsi_pll_7nm_vco_unprepare, -}; - -/* - * PLL Callbacks - */ - -static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; - void __iomem *phy_base = pll_7nm->phy_cmn_mmio; - u32 cmn_clk_cfg0, cmn_clk_cfg1; - - cached->pll_out_div = pll_read(pll_7nm->mmio + - REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); - cached->pll_out_div &= 0x3; - - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); - cached->bit_clk_div = cmn_clk_cfg0 & 0xf; - cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; - - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - cached->pll_mux = cmn_clk_cfg1 & 0x3; - - DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", - pll_7nm->id, cached->pll_out_div, cached->bit_clk_div, - cached->pix_clk_div, cached->pll_mux); -} - -static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; - void __iomem *phy_base = pll_7nm->phy_cmn_mmio; - u32 val; - int ret; - - val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); - val &= ~0x3; - val |= cached->pll_out_div; - pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); - - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, - cached->bit_clk_div | (cached->pix_clk_div << 4)); - - val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - val &= ~0x3; - val |= cached->pll_mux; - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); - - ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); - if (ret) { - DRM_DEV_ERROR(&pll_7nm->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); - return ret; - } - - DBG("DSI PLL%d", pll_7nm->id); - - return 0; -} - -static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - void __iomem *base = pll_7nm->phy_cmn_mmio; - u32 data = 0x0; /* internal PLL */ - - DBG("DSI PLL%d", pll_7nm->id); - - switch (uc) { - case MSM_DSI_PHY_STANDALONE: - break; - case MSM_DSI_PHY_MASTER: - pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX]; - break; - case MSM_DSI_PHY_SLAVE: - data = 0x1; /* external PLL */ - break; - default: - return -EINVAL; - } - - /* set PLL src */ - pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); - - pll_7nm->uc = uc; - - return 0; -} - -static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data; - - DBG("DSI PLL%d", pll_7nm->id); - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - -static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct device *dev = &pll_7nm->pdev->dev; - - DBG("DSI PLL%d", pll_7nm->id); - of_clk_del_provider(dev->of_node); - - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); - clk_hw_unregister_divider(pll_7nm->bit_clk_hw); - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); - clk_hw_unregister(&pll_7nm->base.clk_hw); -} - -/* - * The post dividers and mux clocks are created using the standard divider and - * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux - * state to follow the master PLL's divider/mux state. Therefore, we don't - * require special clock ops that also configure the slave PLL registers - */ -static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) -{ - char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; - struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .name = vco_name, - .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_7nm_vco, - }; - struct device *dev = &pll_7nm->pdev->dev; - struct clk_hw_onecell_data *hw_data; - struct clk_hw *hw; - int ret; - - DBG("DSI%d", pll_7nm->id); - - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); - pll_7nm->base.clk_hw.init = &vco_init; - - ret = clk_hw_register(dev, &pll_7nm->base.clk_hw); - if (ret) - return ret; - - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id); - - hw = clk_hw_register_divider(dev, clk_name, - parent, CLK_SET_RATE_PARENT, - pll_7nm->mmio + - REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, - 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_base_clk_hw; - } - - pll_7nm->out_div_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - - /* BIT CLK: DIV_CTRL_3_0 */ - hw = clk_hw_register_divider(dev, clk_name, parent, - CLK_SET_RATE_PARENT, - pll_7nm->phy_cmn_mmio + - REG_DSI_7nm_PHY_CMN_CLK_CFG0, - 0, 4, CLK_DIVIDER_ONE_BASED, - &pll_7nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_out_div_clk_hw; - } - - pll_7nm->bit_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - - /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_bit_clk_hw; - } - - pll_7nm->byte_clk_hw = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; - - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 2); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_byte_clk_hw; - } - - pll_7nm->by_2_bit_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 4); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_by_2_bit_clk_hw; - } - - pll_7nm->post_out_div_clk_hw = hw; - - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); - - hw = clk_hw_register_mux(dev, clk_name, - ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_7nm->phy_cmn_mmio + - REG_DSI_7nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_post_out_div_clk_hw; - } - - pll_7nm->pclk_mux_hw = hw; - - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id); - - /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = clk_hw_register_divider(dev, clk_name, parent, - 0, pll_7nm->phy_cmn_mmio + - REG_DSI_7nm_PHY_CMN_CLK_CFG0, - 4, 4, CLK_DIVIDER_ONE_BASED, - &pll_7nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto err_pclk_mux_hw; - } - - pll_7nm->out_dsiclk_hw = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_7nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_7nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - goto err_dsiclk_hw; - } - - return 0; - -err_dsiclk_hw: - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); -err_pclk_mux_hw: - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); -err_post_out_div_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); -err_by_2_bit_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); -err_byte_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); -err_bit_clk_hw: - clk_hw_unregister_divider(pll_7nm->bit_clk_hw); -err_out_div_clk_hw: - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); -err_base_clk_hw: - clk_hw_unregister(&pll_7nm->base.clk_hw); - - return ret; -} - -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) -{ - struct dsi_pll_7nm *pll_7nm; - struct msm_dsi_pll *pll; - int ret; - - pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); - if (!pll_7nm) - return ERR_PTR(-ENOMEM); - - DBG("DSI PLL%d", id); - - pll_7nm->pdev = pdev; - pll_7nm->id = id; - pll_7nm_list[id] = pll_7nm; - - pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); - } - - pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_7nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); - } - - spin_lock_init(&pll_7nm->postdiv_lock); - - pll = &pll_7nm->base; - pll->min_rate = 1000000000UL; - pll->max_rate = 3500000000UL; - if (type == MSM_DSI_PHY_7NM_V4_1) { - pll->min_rate = 600000000UL; - pll->max_rate = (unsigned long)5000000000ULL; - /* workaround for max rate overflowing on 32-bit builds: */ - pll->max_rate = max(pll->max_rate, 0xffffffffUL); - } - pll->get_provider = dsi_pll_7nm_get_provider; - pll->destroy = dsi_pll_7nm_destroy; - pll->save_state = dsi_pll_7nm_save_state; - pll->restore_state = dsi_pll_7nm_restore_state; - pll->set_usecase = dsi_pll_7nm_set_usecase; - - pll_7nm->vco_delay = 1; - - ret = pll_7nm_register(pll_7nm); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); - } - - /* TODO: Remove this when we have proper display handover support */ - msm_dsi_pll_save_state(pll); - - return pll; -} From patchwork Wed Mar 24 15:18:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407866 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp501958jai; Wed, 24 Mar 2021 08:19:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/Uvs7JMQM9zgTZ/PObLOUlvkZBq7nl3FGKf3pRZNnRSRYPHzW5rWQaJIHMZbPpLEALpsI X-Received: by 2002:a17:90a:4104:: with SMTP id u4mr3880109pjf.81.1616599167270; Wed, 24 Mar 2021 08:19:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599167; cv=none; d=google.com; s=arc-20160816; b=a1qhbsRA9BAlfmhLP8v2okPWuz7+btnrJJlk/cFkCqeFg2kFS4p2nu1kJqw42BzuLr zvU4B6a3lZHtCRygYOWtxAZobGmMmHuHImIOXfdUrGhEgu31xaAPtuSlYG4u5KvAhAgq Be4DeSWvnwykWM3cv0Ek3mXSM4nrUsEZLPtLUlpSuRVangKt6cIRMo3Rkkg6K6TPHdH2 qV64DkfZ+lQFoPgg8lDCULNwTVoXdAuayOo5tHlinAAunBOH0Uie4ktwa0WIVJnQHb7h pSO0N4kr3Czj6aIRkxPEjbITyc68GwHJ+ky75YBnhW8+C2MR4fv2+Y1IxFYxvXivTkPY CkOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=FXzEhXH0eceq86nL3VBWqVC4bteKemq6OJNlxqMNN/g=; b=PJuGq1NG90xfQSN55FlJqJDNyHu4JrlL24JqEA5DiXB8dc2nzDvTxAiY91+IsLs/FJ okUhko9unRSp2Y0gHr13wwBTgiZdLCUhf1z3Itdjl0nyvgVr2urU3K7RYM/ZWwMs6hGB VkuAzId8Rpcg2M77tGlT3ddMDycGForbWoJN9KgYu72aUCKop7R8vHTt4q0iP7rYT5LJ wyuUMNnYwq8xwafuEdCeJxB95sBB9Bi0RHvG//nbsm42ZL4WTlL7jkPYrzOmOxF6hVTi elsacfFjBZ3vAtX4QXcqqsO54/y9h+ZUAF8TIL8x3q/DaypJGhGwp7C3YlUDHq4PhiaR fEDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=rG6mF1kw; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id v19si2382926ple.193.2021.03.24.08.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=rG6mF1kw; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7BD96EC71; Wed, 24 Mar 2021 15:19:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EB8F6EC6E for ; Wed, 24 Mar 2021 15:19:17 +0000 (UTC) Received: by mail-lf1-x131.google.com with SMTP id v15so2359962lfq.5 for ; Wed, 24 Mar 2021 08:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+G6RajVDTexx6T3+eLMEAHUipQEnluOhy+kbnsltVko=; b=rG6mF1kw7DwvEo3ge82WEUpCo3/YQYrxkzIu/d/vWrD6/xqfc54tbh518JH7NukZH8 KordxQoeI1MU7UPM/qhqc813hk0gO1GCCBmgHWUHjWT4SWuCZ88R7zWohro6K8QrCKwp PwSNy0LQtQ8G94ynwfXi5Xd0cyIDgfO1HlivQGLeqlgQSx358uLoILh0T5VRl+vKdDL6 dEWAhSupdiHbgpmSEqsqSMRm38fKgkGqGB7H/RplOO49vvlRyivf6RWaRGm5dFqr+DUr qnZcNps7BEMkXhL5VgWc2NyoWPkX7FZG0mMQAFEXcDO4YMxGoUeWVhm0jg283zmp+h+J FaQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+G6RajVDTexx6T3+eLMEAHUipQEnluOhy+kbnsltVko=; b=WaNo2ivr0LA4N8JHRL3bgFQGFw7lRMaxfdkjqZzTwwfX2CKA+vzCTDU1+hnmi161MX hY73y3WlhyccyTbI33lK9FCWHxWuiLfPJ/tU1TYJOfUQMxtq00DW2C8FPdKIMgpxgK44 JPhY6rai9WF2EaWynqhsdIUExoPDJfEXvAor/+rt5LEHE/9EyKTVBlErg9YLFJfW9FWd sZ3Y+U6ROW0tHBOuYWL+ZTzprEbEJEelFd88f+dVsL7bE/4zaRj4DK5K3FVRioanDktl TvY1j7Ae151VukbV/ULwKTWWjzwOf/0X70e8S0GOsSxYq8Sq0XOtgHmtZPyqCX1qUOGV pw5w== X-Gm-Message-State: AOAM5328oUivUK4YIlNZfaOwddUYf2Qc4i7IjvM4H24xNAS3PojL4Cw1 ZlxDcJg3aMDqkeDmI3LR5MRN3g== X-Received: by 2002:a05:6512:1108:: with SMTP id l8mr2343371lfg.592.1616599155725; Wed, 24 Mar 2021 08:19:15 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:15 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 06/28] drm/msm/dsi: drop multiple pll enable_seq support Date: Wed, 24 Mar 2021 18:18:24 +0300 Message-Id: <20210324151846.2774204-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The only PLL using multiple enable sequences is the 28nm PLL, which just does the single step in the loop. Push that support back into the PLL code. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 23 +++++-- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 65 +++++++------------ drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 +- 5 files changed, 42 insertions(+), 56 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 6a63901da7a4..4386edfa91fe 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1087,8 +1087,7 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll_14nm->vco_delay = 1; - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; + pll->enable_seq = dsi_pll_14nm_enable_seq; ret = pll_14nm_register(pll_14nm); if (ret) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 2f502efa4dd5..760cf7956fa2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -311,7 +311,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { /* * PLL Callbacks */ -static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; @@ -386,6 +386,19 @@ static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) return locked ? 0 : -EINVAL; } +static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +{ + int i, ret; + + for (i = 0; i < 3; i++) { + ret = _dsi_pll_28nm_enable_seq_hpm(pll); + if (!ret) + return 0; + } + + return ret; +} + static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); @@ -619,15 +632,11 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, if (type == MSM_DSI_PHY_28NM_HPM) { pll_28nm->vco_delay = 1; - pll->en_seq_cnt = 3; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm; - pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm; - pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm; + pll->enable_seq = dsi_pll_28nm_enable_seq_hpm; } else if (type == MSM_DSI_PHY_28NM_LP) { pll_28nm->vco_delay = 1000; - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp; + pll->enable_seq = dsi_pll_28nm_enable_seq_lp; } else { DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type); return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 4a40513057e8..2cfb7edf91d8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -515,8 +515,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll->save_state = dsi_pll_28nm_save_state; pll->restore_state = dsi_pll_28nm_restore_state; - pll->en_seq_cnt = 1; - pll->enable_seqs[0] = dsi_pll_28nm_enable_seq; + pll->enable_seq = dsi_pll_28nm_enable_seq; ret = pll_28nm_register(pll_28nm); if (ret) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 3dc65877fa10..9e9fa90bf504 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -5,46 +5,6 @@ #include "dsi_pll.h" -static int dsi_pll_enable(struct msm_dsi_pll *pll) -{ - int i, ret = 0; - - /* - * Certain PLLs do not allow VCO rate update when it is on. - * Keep track of their status to turn on/off after set rate success. - */ - if (unlikely(pll->pll_on)) - return 0; - - /* Try all enable sequences until one succeeds */ - for (i = 0; i < pll->en_seq_cnt; i++) { - ret = pll->enable_seqs[i](pll); - DBG("DSI PLL %s after sequence #%d", - ret ? "unlocked" : "locked", i + 1); - if (!ret) - break; - } - - if (ret) { - DRM_ERROR("DSI PLL failed to lock\n"); - return ret; - } - - pll->pll_on = true; - - return 0; -} - -static void dsi_pll_disable(struct msm_dsi_pll *pll) -{ - if (unlikely(!pll->pll_on)) - return; - - pll->disable_seq(pll); - - pll->pll_on = false; -} - /* * DSI PLL Helper functions */ @@ -64,15 +24,36 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + int ret = 0; - return dsi_pll_enable(pll); + /* + * Certain PLLs do not allow VCO rate update when it is on. + * Keep track of their status to turn on/off after set rate success. + */ + if (unlikely(pll->pll_on)) + return 0; + + ret = pll->enable_seq(pll); + if (ret) { + DRM_ERROR("DSI PLL failed to lock\n"); + return ret; + } + + pll->pll_on = true; + + return 0; } void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - dsi_pll_disable(pll); + if (unlikely(!pll->pll_on)) + return; + + pll->disable_seq(pll); + + pll->pll_on = false; } void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index bbecb1de5678..eebf90671eec 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -12,7 +12,6 @@ #include "dsi.h" #define NUM_DSI_CLOCKS_MAX 6 -#define MAX_DSI_PLL_EN_SEQS 10 struct msm_dsi_pll { enum msm_dsi_phy_type type; @@ -23,9 +22,8 @@ struct msm_dsi_pll { unsigned long min_rate; unsigned long max_rate; - u32 en_seq_cnt; - int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll); + int (*enable_seq)(struct msm_dsi_pll *pll); void (*disable_seq)(struct msm_dsi_pll *pll); int (*get_provider)(struct msm_dsi_pll *pll, struct clk **byte_clk_provider, From patchwork Wed Mar 24 15:18:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407867 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp501994jai; Wed, 24 Mar 2021 08:19:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0gF3E9fCpCQou4bXhb5g8foLqe0ojnArotExJAzmjmIIQ/VHhw9qt6yAPVX6XWHYRyr5o X-Received: by 2002:a63:2507:: with SMTP id l7mr3525826pgl.198.1616599169551; Wed, 24 Mar 2021 08:19:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599169; cv=none; d=google.com; s=arc-20160816; b=Bkci7tXa5pyOxKMxYt3bzvtOb9n/WBDCD6Sgqip1mvJifG33tGnZFFTbxezP14LCbq cNY1q18uhySYuTiU9D07t2SQpxVJPWdw8Qre9Fi+0Dtm2uUu0rXD205cCer+k4pd1tbZ tCcCVGuXr2j+uJKE/hF7JQYhbTF05U/48lQUUjIgu1JbMj5+N6bj1vZGYa+1g5zhPyBy aIjWMbfcs4mwB0EIKUBJNuWdkoWf4FN5MaatR7mQx9C3x0oM0CHpv2xBASHlJ31Ink21 PE21RHL6TdFgQil10BxSDRgH3XPTKAOp1Ml7qIAmHkJpit8hGGQSwdRpV+xHjYmPmvdR KCGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=kVnLRlycN5Le6A2jFW7jUA/j3feNe+gx9/3I60d8XlQ=; b=IU1cvue6LOU7ypTlSaBcHFazNuiaNF084q/N8wokTn1i4hKP+Gv4BnWuzKbKazRE2G L+ZTQ+IL3x6dfBpCD4j9emgkBmDb+v77gXfAKkS/vxEX8SjwEADKHo3Ue9BlKfkXAKqF a3K1nAWmdiF58dIHl40xIjBgXb/18Uyts6/9LmQhoL4SyXcOcWcoYPSlqa6upAU3LIci /bS0X9Afj7e60lrmXu8EP0jszzBUgvWFKCV2omRHVl+dZ88klIgCpLiFJ7cwhBEwKsa0 X00J4OoQ9IWNdKPJ8mzYUkJ1dF7yC6t7YFNl7jstio61LGvs258WltoXHfnMo7vGJyOJ nt4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TDA1JkA6; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id b3si2461001pfo.97.2021.03.24.08.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TDA1JkA6; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E480D6EC6B; Wed, 24 Mar 2021 15:19:21 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCBF86EC6B for ; Wed, 24 Mar 2021 15:19:18 +0000 (UTC) Received: by mail-lf1-x131.google.com with SMTP id b4so8595303lfi.6 for ; Wed, 24 Mar 2021 08:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WP+g9ax6k3KQgOXxN36ac/1BC7z8Hqe9Ma9GDA/uoJw=; b=TDA1JkA64Ok4rMX01AZVDOCXJuQTmntW8NdzipHRJTJ0NceEhcz0FlHDNBL+UDPcbh qp+6iBBOSWlH4fyOZDldvguHtJfINGzYuLERNKFyhLooCRKx3Zob9No6pu+KxcglLUNK KQYp71Lwjtv0SHuiO09KtvIbluGHC6L5oinYJ9dR20/d7lL8Tzsjwc717FHAMeSSB+p1 VOI2ZwrAF8wtz956it8JPli3hjCziD1II5Uw+Z9rCyZHdf7+35ta6dcc1vfp+X0OGsed Vb1xHnVWECOjFkqmt8cAvicznSxehzkf4qTMM6H67cj54OHyzywBr1phSLG6xhuOIBqz X2Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WP+g9ax6k3KQgOXxN36ac/1BC7z8Hqe9Ma9GDA/uoJw=; b=L6x0pwuLFDqwFALwJtozczbhYUQGA9ib8j7+CRr5JpzhyrjJcWE0SH8DBpJDFJIiQg M1+kYA3Bzxw3Z0aMxBGuAbHLKlGiOFSfA4L4HTZIMZLIbsDrYYvxyM1q9d+HoVryJ6+2 3dm7mMh9PuxiZ823CosvfcrOdR55JbZVAo8152IXc3LTN19pqag9NGuG+z2LXQPq7d6W rvVfggAYD2Caahp34V/PK/RtVzc68SpzurQAFyhhiUdRIELXX6M6CgS3tWihqCqm/pe8 KlyZJkGu6KsLcRc0zAVRRV6mbfhLf69Z77BLXh+jZa3gyLcoeOHGokImAPmJGwa1Gubk Txhg== X-Gm-Message-State: AOAM531vhXH7Y+Oz4bofIZ6EYzyegxqqPAhed/khcrFMuk+2oQTIOhmF orna6t/8IpfvDsODYbYbi/DwOw== X-Received: by 2002:ac2:446c:: with SMTP id y12mr2268914lfl.66.1616599157069; Wed, 24 Mar 2021 08:19:17 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:16 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 07/28] drm/msm/dsi: move all PLL callbacks into PHY config struct Date: Wed, 24 Mar 2021 18:18:25 +0300 Message-Id: <20210324151846.2774204-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits the amount of data in the struct msm_dsi_pll. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 6 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 14 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 15 +++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 38 ++++++++--- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 47 ++++++++----- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 65 ++++++++++++------ .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 33 +++++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 49 +++++++++----- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 67 ++++--------------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 67 +------------------ 10 files changed, 191 insertions(+), 210 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 78ef5d4ed922..21cf883fb6f1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -107,8 +107,6 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); /* dsi pll */ struct msm_dsi_pll; #ifdef CONFIG_DRM_MSM_DSI_PLL -struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int dsi_id); void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, struct clk **byte_clk_provider, struct clk **pixel_clk_provider); @@ -117,10 +115,6 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, enum msm_dsi_phy_usecase uc); #else -static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) { - return ERR_PTR(-ENODEV); -} static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) { } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 83eb0a630443..5f153b683521 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -709,12 +709,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) if (ret) goto fail; - phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); - if (IS_ERR_OR_NULL(phy->pll)) { - DRM_DEV_INFO(dev, - "%s: pll init failed: %ld, need separate pll clk driver\n", - __func__, PTR_ERR(phy->pll)); - phy->pll = NULL; + if (phy->cfg->ops.pll_init) { + ret = phy->cfg->ops.pll_init(phy); + if (ret) { + DRM_DEV_INFO(dev, + "%s: pll init failed: %d, need separate pll clk driver\n", + __func__, ret); + goto fail; + } } dsi_phy_disable_resource(phy); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 03dfb08e7128..244d2c900d40 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -17,15 +17,30 @@ #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) struct msm_dsi_phy_ops { + int (*pll_init)(struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, struct msm_dsi_phy_clk_request *clk_req); void (*disable)(struct msm_dsi_phy *phy); }; +struct msm_dsi_pll_ops { + int (*enable_seq)(struct msm_dsi_pll *pll); + void (*disable_seq)(struct msm_dsi_pll *pll); + int (*get_provider)(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider); + void (*destroy)(struct msm_dsi_pll *pll); + void (*save_state)(struct msm_dsi_pll *pll); + int (*restore_state)(struct msm_dsi_pll *pll); + int (*set_usecase)(struct msm_dsi_pll *pll, + enum msm_dsi_phy_usecase uc); +}; + struct msm_dsi_phy_cfg { enum msm_dsi_phy_type type; struct dsi_reg_config reg_cfg; struct msm_dsi_phy_ops ops; + const struct msm_dsi_pll_ops pll_ops; /* * Each cell {phy_id, pll_id} of the truth table indicates diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 5da369b5c475..f697ff9a0d8e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -828,15 +828,17 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) return ret; } -struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) +static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) { + struct platform_device *pdev = phy->pdev; + int id = phy->id; struct dsi_pll_10nm *pll_10nm; struct msm_dsi_pll *pll; int ret; pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); if (!pll_10nm) - return ERR_PTR(-ENOMEM); + return -ENOMEM; DBG("DSI PLL%d", id); @@ -847,13 +849,13 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_10nm->mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } spin_lock_init(&pll_10nm->postdiv_lock); @@ -861,24 +863,22 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll = &pll_10nm->base; pll->min_rate = 1000000000UL; pll->max_rate = 3500000000UL; - pll->get_provider = dsi_pll_10nm_get_provider; - pll->destroy = dsi_pll_10nm_destroy; - pll->save_state = dsi_pll_10nm_save_state; - pll->restore_state = dsi_pll_10nm_restore_state; - pll->set_usecase = dsi_pll_10nm_set_usecase; + pll->cfg = phy->cfg; pll_10nm->vco_delay = 1; ret = pll_10nm_register(pll_10nm); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); + return ret; } + phy->pll = pll; + /* TODO: Remove this when we have proper display handover support */ msm_dsi_pll_save_state(pll); - return pll; + return 0; } static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy) @@ -1102,6 +1102,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, + .pll_init = dsi_pll_10nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_10nm_get_provider, + .destroy = dsi_pll_10nm_destroy, + .save_state = dsi_pll_10nm_save_state, + .restore_state = dsi_pll_10nm_restore_state, + .set_usecase = dsi_pll_10nm_set_usecase, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, @@ -1120,6 +1128,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, + .pll_init = dsi_pll_10nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_10nm_get_provider, + .destroy = dsi_pll_10nm_destroy, + .save_state = dsi_pll_10nm_save_state, + .restore_state = dsi_pll_10nm_restore_state, + .set_usecase = dsi_pll_10nm_set_usecase, }, .io_start = { 0xc994400, 0xc996400 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 4386edfa91fe..011d285bf2c0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1042,18 +1042,20 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) return 0; } -struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) +static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) { + struct platform_device *pdev = phy->pdev; + int id = phy->id; struct dsi_pll_14nm *pll_14nm; struct msm_dsi_pll *pll; int ret; if (!pdev) - return ERR_PTR(-ENODEV); + return -ENODEV; pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); if (!pll_14nm) - return ERR_PTR(-ENOMEM); + return -ENOMEM; DBG("PLL%d", id); @@ -1064,13 +1066,13 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_14nm->mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } spin_lock_init(&pll_14nm->postdiv_lock); @@ -1078,24 +1080,19 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll = &pll_14nm->base; pll->min_rate = VCO_MIN_RATE; pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_14nm_get_provider; - pll->destroy = dsi_pll_14nm_destroy; - pll->disable_seq = dsi_pll_14nm_disable_seq; - pll->save_state = dsi_pll_14nm_save_state; - pll->restore_state = dsi_pll_14nm_restore_state; - pll->set_usecase = dsi_pll_14nm_set_usecase; + pll->cfg = phy->cfg; pll_14nm->vco_delay = 1; - pll->enable_seq = dsi_pll_14nm_enable_seq; - ret = pll_14nm_register(pll_14nm); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); + return ret; } - return pll; + phy->pll = pll; + + return 0; } static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, @@ -1230,6 +1227,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_14nm_get_provider, + .destroy = dsi_pll_14nm_destroy, + .save_state = dsi_pll_14nm_save_state, + .restore_state = dsi_pll_14nm_restore_state, + .set_usecase = dsi_pll_14nm_set_usecase, + .disable_seq = dsi_pll_14nm_disable_seq, + .enable_seq = dsi_pll_14nm_enable_seq, }, .io_start = { 0x994400, 0x996400 }, .num_dsi_phy = 2, @@ -1248,6 +1255,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_14nm_get_provider, + .destroy = dsi_pll_14nm_destroy, + .save_state = dsi_pll_14nm_save_state, + .restore_state = dsi_pll_14nm_restore_state, + .set_usecase = dsi_pll_14nm_set_usecase, + .disable_seq = dsi_pll_14nm_disable_seq, + .enable_seq = dsi_pll_14nm_enable_seq, }, .io_start = { 0xc994400, 0xc996000 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 760cf7956fa2..fb6e19d9495d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -597,19 +597,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) return 0; } -struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) +static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) { + struct platform_device *pdev = phy->pdev; + int id = phy->id; struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; int ret; if (!pdev) - return ERR_PTR(-ENODEV); + return -ENODEV; pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); if (!pll_28nm) - return ERR_PTR(-ENOMEM); + return -ENOMEM; pll_28nm->pdev = pdev; pll_28nm->id = id; @@ -617,40 +618,33 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pll = &pll_28nm->base; pll->min_rate = VCO_MIN_RATE; pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_28nm_get_provider; - pll->destroy = dsi_pll_28nm_destroy; - pll->disable_seq = dsi_pll_28nm_disable_seq; - pll->save_state = dsi_pll_28nm_save_state; - pll->restore_state = dsi_pll_28nm_restore_state; - - if (type == MSM_DSI_PHY_28NM_HPM) { + if (phy->cfg->type == MSM_DSI_PHY_28NM_HPM) { pll_28nm->vco_delay = 1; - - pll->enable_seq = dsi_pll_28nm_enable_seq_hpm; - } else if (type == MSM_DSI_PHY_28NM_LP) { + } else if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) { pll_28nm->vco_delay = 1000; - - pll->enable_seq = dsi_pll_28nm_enable_seq_lp; } else { - DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type); - return ERR_PTR(-EINVAL); + DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", phy->cfg->type); + return -EINVAL; } + pll->cfg = phy->cfg; + ret = pll_28nm_register(pll_28nm); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); + return ret; } - return pll; -} + phy->pll = pll; + return 0; +} static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) @@ -809,6 +803,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_28nm_get_provider, + .destroy = dsi_pll_28nm_destroy, + .save_state = dsi_pll_28nm_save_state, + .restore_state = dsi_pll_28nm_restore_state, + .disable_seq = dsi_pll_28nm_disable_seq, + .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, .io_start = { 0xfd922b00, 0xfd923100 }, .num_dsi_phy = 2, @@ -827,6 +830,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_28nm_get_provider, + .destroy = dsi_pll_28nm_destroy, + .save_state = dsi_pll_28nm_save_state, + .restore_state = dsi_pll_28nm_restore_state, + .disable_seq = dsi_pll_28nm_disable_seq, + .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, .io_start = { 0x1a94400, 0x1a96400 }, .num_dsi_phy = 2, @@ -845,6 +857,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_28nm_get_provider, + .destroy = dsi_pll_28nm_destroy, + .save_state = dsi_pll_28nm_save_state, + .restore_state = dsi_pll_28nm_restore_state, + .disable_seq = dsi_pll_28nm_disable_seq, + .enable_seq = dsi_pll_28nm_enable_seq_lp, }, .io_start = { 0x1a98500 }, .num_dsi_phy = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 2cfb7edf91d8..08f31be3b0dc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -483,19 +483,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) return 0; } -struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, - int id) +static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) { + struct platform_device *pdev = phy->pdev; + int id = phy->id; struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; int ret; if (!pdev) - return ERR_PTR(-ENODEV); + return -ENODEV; pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); if (!pll_28nm) - return ERR_PTR(-ENOMEM); + return -ENOMEM; pll_28nm->pdev = pdev; pll_28nm->id = id + 1; @@ -503,27 +504,24 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pll = &pll_28nm->base; pll->min_rate = VCO_MIN_RATE; pll->max_rate = VCO_MAX_RATE; - pll->get_provider = dsi_pll_28nm_get_provider; - pll->destroy = dsi_pll_28nm_destroy; - pll->disable_seq = dsi_pll_28nm_disable_seq; - pll->save_state = dsi_pll_28nm_save_state; - pll->restore_state = dsi_pll_28nm_restore_state; - pll->enable_seq = dsi_pll_28nm_enable_seq; + pll->cfg = phy->cfg; ret = pll_28nm_register(pll_28nm); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); + return ret; } - return pll; + phy->pll = pll; + + return 0; } static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, @@ -704,6 +702,15 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_8960_init, + }, + .pll_ops = { + .get_provider = dsi_pll_28nm_get_provider, + .destroy = dsi_pll_28nm_destroy, + .save_state = dsi_pll_28nm_save_state, + .restore_state = dsi_pll_28nm_restore_state, + .disable_seq = dsi_pll_28nm_disable_seq, + .enable_seq = dsi_pll_28nm_enable_seq, }, .io_start = { 0x4700300, 0x5800300 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index f9af9d70b56a..68b54e5060e4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -178,7 +178,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) dec = div_u64(dec_multiple, multiplier); - if (pll->base.type != MSM_DSI_PHY_7NM_V4_1) + if (pll->base.cfg->type != MSM_DSI_PHY_7NM_V4_1) regs->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) regs->pll_clock_inverters = 0xa0; @@ -273,7 +273,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->mmio; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { + if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; @@ -307,9 +307,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); + pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); - if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { + if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -853,16 +853,17 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) return ret; } -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) +static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) { + struct platform_device *pdev = phy->pdev; + int id = phy->id; struct dsi_pll_7nm *pll_7nm; struct msm_dsi_pll *pll; int ret; pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); if (!pll_7nm) - return ERR_PTR(-ENOMEM); + return -ENOMEM; DBG("DSI PLL%d", id); @@ -873,13 +874,13 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_7nm->mmio)) { DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } spin_lock_init(&pll_7nm->postdiv_lock); @@ -887,30 +888,28 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, pll = &pll_7nm->base; pll->min_rate = 1000000000UL; pll->max_rate = 3500000000UL; - if (type == MSM_DSI_PHY_7NM_V4_1) { + if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) { pll->min_rate = 600000000UL; pll->max_rate = (unsigned long)5000000000ULL; /* workaround for max rate overflowing on 32-bit builds: */ pll->max_rate = max(pll->max_rate, 0xffffffffUL); } - pll->get_provider = dsi_pll_7nm_get_provider; - pll->destroy = dsi_pll_7nm_destroy; - pll->save_state = dsi_pll_7nm_save_state; - pll->restore_state = dsi_pll_7nm_restore_state; - pll->set_usecase = dsi_pll_7nm_set_usecase; + pll->cfg = phy->cfg; pll_7nm->vco_delay = 1; ret = pll_7nm_register(pll_7nm); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ERR_PTR(ret); + return ret; } + phy->pll = pll; + /* TODO: Remove this when we have proper display handover support */ msm_dsi_pll_save_state(pll); - return pll; + return 0; } static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) @@ -1142,6 +1141,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_7nm_get_provider, + .destroy = dsi_pll_7nm_destroy, + .save_state = dsi_pll_7nm_save_state, + .restore_state = dsi_pll_7nm_restore_state, + .set_usecase = dsi_pll_7nm_set_usecase, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, @@ -1160,6 +1167,14 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + }, + .pll_ops = { + .get_provider = dsi_pll_7nm_get_provider, + .destroy = dsi_pll_7nm_destroy, + .save_state = dsi_pll_7nm_save_state, + .restore_state = dsi_pll_7nm_restore_state, + .set_usecase = dsi_pll_7nm_set_usecase, }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 9e9fa90bf504..c7ff0eba0e8b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -3,6 +3,7 @@ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. */ +#include "dsi_phy.h" #include "dsi_pll.h" /* @@ -33,7 +34,7 @@ int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) if (unlikely(pll->pll_on)) return 0; - ret = pll->enable_seq(pll); + ret = pll->cfg->pll_ops.enable_seq(pll); if (ret) { DRM_ERROR("DSI PLL failed to lock\n"); return ret; @@ -51,7 +52,7 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) if (unlikely(!pll->pll_on)) return; - pll->disable_seq(pll); + pll->cfg->pll_ops.disable_seq(pll); pll->pll_on = false; } @@ -76,8 +77,8 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, struct clk **byte_clk_provider, struct clk **pixel_clk_provider) { - if (pll->get_provider) - return pll->get_provider(pll, + if (pll->cfg->pll_ops.get_provider) + return pll->cfg->pll_ops.get_provider(pll, byte_clk_provider, pixel_clk_provider); @@ -86,14 +87,14 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) { - if (pll->destroy) - pll->destroy(pll); + if (pll->cfg->pll_ops.destroy) + pll->cfg->pll_ops.destroy(pll); } void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) { - if (pll->save_state) { - pll->save_state(pll); + if (pll->cfg->pll_ops.save_state) { + pll->cfg->pll_ops.save_state(pll); pll->state_saved = true; } } @@ -102,8 +103,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) { int ret; - if (pll->restore_state && pll->state_saved) { - ret = pll->restore_state(pll); + if (pll->cfg->pll_ops.restore_state && pll->state_saved) { + ret = pll->cfg->pll_ops.restore_state(pll); if (ret) return ret; @@ -116,50 +117,8 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, enum msm_dsi_phy_usecase uc) { - if (pll->set_usecase) - return pll->set_usecase(pll, uc); + if (pll->cfg->pll_ops.set_usecase) + return pll->cfg->pll_ops.set_usecase(pll, uc); return 0; } - -struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) -{ - struct device *dev = &pdev->dev; - struct msm_dsi_pll *pll; - - switch (type) { - case MSM_DSI_PHY_28NM_HPM: - case MSM_DSI_PHY_28NM_LP: - pll = msm_dsi_pll_28nm_init(pdev, type, id); - break; - case MSM_DSI_PHY_28NM_8960: - pll = msm_dsi_pll_28nm_8960_init(pdev, id); - break; - case MSM_DSI_PHY_14NM: - pll = msm_dsi_pll_14nm_init(pdev, id); - break; - case MSM_DSI_PHY_10NM: - pll = msm_dsi_pll_10nm_init(pdev, id); - break; - case MSM_DSI_PHY_7NM: - case MSM_DSI_PHY_7NM_V4_1: - pll = msm_dsi_pll_7nm_init(pdev, type, id); - break; - default: - pll = ERR_PTR(-ENXIO); - break; - } - - if (IS_ERR(pll)) { - DRM_DEV_ERROR(dev, "%s: failed to init DSI PLL\n", __func__); - return pll; - } - - pll->type = type; - - DBG("DSI:%d PLL registered", id); - - return pll; -} - diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index eebf90671eec..4fa73fbcba52 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -14,8 +14,6 @@ #define NUM_DSI_CLOCKS_MAX 6 struct msm_dsi_pll { - enum msm_dsi_phy_type type; - struct clk_hw clk_hw; bool pll_on; bool state_saved; @@ -23,16 +21,7 @@ struct msm_dsi_pll { unsigned long min_rate; unsigned long max_rate; - int (*enable_seq)(struct msm_dsi_pll *pll); - void (*disable_seq)(struct msm_dsi_pll *pll); - int (*get_provider)(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider); - void (*destroy)(struct msm_dsi_pll *pll); - void (*save_state)(struct msm_dsi_pll *pll); - int (*restore_state)(struct msm_dsi_pll *pll); - int (*set_usecase)(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc); + const struct msm_dsi_phy_cfg *cfg; }; #define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) @@ -72,59 +61,5 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw); void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, struct clk **clks, u32 num_clks); -/* - * Initialization for Each PLL Type - */ -#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY -struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id); -#else -static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init( - struct platform_device *pdev, enum msm_dsi_phy_type type, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif -#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY -struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, - int id); -#else -static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init( - struct platform_device *pdev, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif - -#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY -struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id); -#else -static inline struct msm_dsi_pll * -msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif -#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY -struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id); -#else -static inline struct msm_dsi_pll * -msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif -#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id); -#else -static inline struct msm_dsi_pll * -msm_dsi_pll_7nm_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) -{ - return ERR_PTR(-ENODEV); -} -#endif - #endif /* __DSI_PLL_H__ */ From patchwork Wed Mar 24 15:18:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407868 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502026jai; Wed, 24 Mar 2021 08:19:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2BkULlIpFFFWC1eJ1/HNDjqjGGNBLlouJSM9oDk2UJCpuIoRTvwQPNLskM4FEmzqicvNd X-Received: by 2002:a17:902:fe0d:b029:e5:ffb8:1c28 with SMTP id g13-20020a170902fe0db02900e5ffb81c28mr4089871plj.62.1616599171796; Wed, 24 Mar 2021 08:19:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599171; cv=none; d=google.com; s=arc-20160816; b=R2QeFjEAPK3HbZ6K95UfDkTp0eCZKyqGY9KEn3OLpKaZO4Cyitd2htgf9cxoI3xEIi Aa3nA+5yemJ+OYPzjcu0XDol1c9S6orKi4sCL4NmXNx6vc+3Ju6Z4QYpk5rM3+7kxRdz dylcGafc18gIIa/PPN40ArqBBFUpAdHiqhSarlFvK7gq7Z4BgU+nBbJgc1MPtU5Emdvt 5ySayW2KCmJ68TICsFicUqbRBBCw9U0TNGPtC7s+Jn+K4Dq556dQ/BKusFD7dWFAR2oN wY28MiDSQvFIUYobvJMFL0DdU9EmsZA6CQ7a6TmuNm2o/C5ArRSg+ZzfNTkEI5m0EgZa wOOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=40cdPWnckejQjAzrxIdeofvylSWqqPiqNfrYtvvh1CI=; b=MA0Bp7JtKQCf5mHk8rBJCB2vYdfxmuzYTX/CEI5GbrqPx3krEdNYG18hEvAV7ixErH fdEZCQaSZyRrxY2N07mZDNswq8eSDRqrP5k7JA1vPASif6k02DCt1l1LOLMwNIFG5+zn IYGhsyibv3i55juhxQk1Ww6hflq7ywpEnnmHV4KzTfxUo/kPP1RdhLq6RxFFlpBu49/+ m/eYy+pf05dPxSA1t+tzRXa5N9ckpkYI+8MzaUpOF+I7lOQoz7bQFF6mQATzYCnR6pyg P7JSkSJDpqIdWwO4N3MDH74oG08ZzWv9/OkFhbggoF60j6OJm3UNQ7tt4nd3dOj0FSqs VxFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=oEyPq+l0; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id v129si2533903pgv.266.2021.03.24.08.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=oEyPq+l0; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FC8A6EC76; Wed, 24 Mar 2021 15:19:22 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by gabe.freedesktop.org (Postfix) with ESMTPS id 591C66EC76 for ; Wed, 24 Mar 2021 15:19:20 +0000 (UTC) Received: by mail-lj1-x229.google.com with SMTP id z25so30670657lja.3 for ; Wed, 24 Mar 2021 08:19:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=una7OW7SwqxBKetRjUutsOKpzg9raxB99uDxP68mTsc=; b=oEyPq+l0VttqNWjHuQS3veEc+Pe99sYEZOZnL6LVimVOhyUl9qUii+VZu6LJk/PNCx rG3UH0PVz74iTCTL1AIQu3crTJaGZ14LMznoi4NbeLlSoU9LFAYeKLrg+3n4iJq1r0UT /mY7mndzHLBoJW7mWOp/PURHjn1CQTCi1nLMXshnRcdHBP8Xbp2AHkQNGQKKxW8392vM y0mSCM4p4DVjISdn04hQ7uNbGh4oOVxg5HGtxTMZEeyCorvQQLcCVfOCdW7Okgv8CgOM cIUqzMo0beaOG9Ge0Ke1Fw4uWFo1pPEH0iTIGXQwPbuSMDUHLPLiSGi7d/ApxTtYMpk9 f1Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=una7OW7SwqxBKetRjUutsOKpzg9raxB99uDxP68mTsc=; b=VooSqRWgxeLdJGgdnSFgeesG6/PL6dfdyyNchB2k4GoJP/qR1oDR8QOgppGgK7SEiz AVJM0SAf+mL7vXHSo1TcqTJDYc24SHZlcudqYo+PReFAuBeQ1VSuznjjxF142TdDrHSN BMRJp8hvrfVC2ZBQIQo+0XrlBDduW5O8VsoEzVfqOFoWYVXwXU2CYtjulYervvrBsfsr 7ax2kDDmkYTfzQD9lJ0SsXIxi/22epHinxO85xCRsOFsPZxyCzHeNdq/xGbuRE+jQybe n4eVQzkpTnymVOKxtcPcbjRgrlc12EKNniiuMxbmDmGU0VlFXOvkUqyPxIiOYynLHpPQ E/Zw== X-Gm-Message-State: AOAM533sjSMVp37IlJDYmQyPG1AI3uaFlV0w3F2sDDH00X2EgWij0Ln5 O6UmyqpWnnTMwIM5gmfjc4QbCw== X-Received: by 2002:a2e:9793:: with SMTP id y19mr2355270lji.374.1616599158738; Wed, 24 Mar 2021 08:19:18 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:17 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 08/28] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Date: Wed, 24 Mar 2021 18:18:26 +0300 Message-Id: <20210324151846.2774204-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 12 ----------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 11 +++++----- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 1 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 19 ++++++++---------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 20 ++++++++++--------- 8 files changed, 25 insertions(+), 45 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 21cf883fb6f1..98a4b296fa30 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -23,18 +23,6 @@ struct msm_dsi_phy_shared_timings; struct msm_dsi_phy_clk_request; -enum msm_dsi_phy_type { - MSM_DSI_PHY_28NM_HPM, - MSM_DSI_PHY_28NM_LP, - MSM_DSI_PHY_20NM, - MSM_DSI_PHY_28NM_8960, - MSM_DSI_PHY_14NM, - MSM_DSI_PHY_10NM, - MSM_DSI_PHY_7NM, - MSM_DSI_PHY_7NM_V4_1, - MSM_DSI_PHY_MAX -}; - enum msm_dsi_phy_usecase { MSM_DSI_PHY_STANDALONE, MSM_DSI_PHY_MASTER, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 244d2c900d40..39abb86446f9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -13,9 +13,6 @@ #define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset)) -/* v3.0.0 10nm implementation that requires the old timings settings */ -#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) - struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, @@ -37,7 +34,6 @@ struct msm_dsi_pll_ops { }; struct msm_dsi_phy_cfg { - enum msm_dsi_phy_type type; struct dsi_reg_config reg_cfg; struct msm_dsi_phy_ops ops; const struct msm_dsi_pll_ops pll_ops; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index f697ff9a0d8e..dc8ccc994759 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -59,6 +59,9 @@ struct dsi_pll_regs { u32 ssc_control; }; +/* v3.0.0 10nm implementation that requires the old timings settings */ +#define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0) + struct dsi_pll_config { u32 ref_freq; bool div_override; @@ -915,7 +918,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 }; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) + if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS) tx_dctrl[3] = 0x02; /* Strength ctrl settings */ @@ -950,7 +953,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) tx_dctrl[i]); } - if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) { + if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) { /* Toggle BIT 0 to release freeze I/0 */ dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05); dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04); @@ -1090,7 +1093,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { - .type = MSM_DSI_PHY_10NM, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { @@ -1116,7 +1118,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { - .type = MSM_DSI_PHY_10NM, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { @@ -1139,5 +1140,5 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { }, .io_start = { 0xc994400, 0xc996400 }, .num_dsi_phy = 2, - .quirks = V3_0_0_10NM_OLD_TIMINGS_QUIRK, + .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS, }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 011d285bf2c0..d78f846cf8e4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1215,7 +1215,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { - .type = MSM_DSI_PHY_14NM, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { @@ -1243,7 +1242,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { - .type = MSM_DSI_PHY_14NM, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index b752636f7f21..5e73f811d645 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -125,7 +125,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { - .type = MSM_DSI_PHY_20NM, .src_pll_truthtable = { {false, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index fb6e19d9495d..bb33261d606d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -40,6 +40,9 @@ #define DSI_BYTE_PLL_CLK 0 #define DSI_PIXEL_PLL_CLK 1 +/* v2.0.0 28nm LP implementation */ +#define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) + #define LPFR_LUT_SIZE 10 struct lpfr_cfg { unsigned long vco_rate; @@ -624,14 +627,10 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) pll = &pll_28nm->base; pll->min_rate = VCO_MIN_RATE; pll->max_rate = VCO_MAX_RATE; - if (phy->cfg->type == MSM_DSI_PHY_28NM_HPM) { - pll_28nm->vco_delay = 1; - } else if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) { + if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) pll_28nm->vco_delay = 1000; - } else { - DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", phy->cfg->type); - return -EINVAL; - } + else + pll_28nm->vco_delay = 1; pll->cfg = phy->cfg; @@ -706,7 +705,7 @@ static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy) dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); - if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) + if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05); else dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d); @@ -791,7 +790,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { - .type = MSM_DSI_PHY_28NM_HPM, .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { @@ -818,7 +816,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { - .type = MSM_DSI_PHY_28NM_HPM, .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { @@ -845,7 +842,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { - .type = MSM_DSI_PHY_28NM_LP, .src_pll_truthtable = { {true, true}, {true, true} }, .has_phy_regulator = true, .reg_cfg = { @@ -869,5 +865,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { }, .io_start = { 0x1a98500 }, .num_dsi_phy = 1, + .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 08f31be3b0dc..79b0842a8dc4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -690,7 +690,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { - .type = MSM_DSI_PHY_28NM_8960, .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 68b54e5060e4..44ae495e8fca 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -59,6 +59,9 @@ struct dsi_pll_regs { u32 ssc_control; }; +/* Hardware is V4.1 */ +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) + struct dsi_pll_config { u32 ref_freq; bool div_override; @@ -178,7 +181,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) dec = div_u64(dec_multiple, multiplier); - if (pll->base.cfg->type != MSM_DSI_PHY_7NM_V4_1) + if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) regs->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) regs->pll_clock_inverters = 0xa0; @@ -273,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->mmio; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { + if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; @@ -307,9 +310,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); + pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); - if (pll->base.cfg->type == MSM_DSI_PHY_7NM_V4_1) { + if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -888,7 +891,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->min_rate = 1000000000UL; pll->max_rate = 3500000000UL; - if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) { + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { pll->min_rate = 600000000UL; pll->max_rate = (unsigned long)5000000000ULL; /* workaround for max rate overflowing on 32-bit builds: */ @@ -948,7 +951,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) const u8 *tx_dctrl = tx_dctrl_0; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) tx_dctrl = tx_dctrl_1; /* Strength ctrl settings */ @@ -1012,7 +1015,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); - if (phy->cfg->type == MSM_DSI_PHY_7NM_V4_1) { + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; @@ -1129,7 +1132,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { - .type = MSM_DSI_PHY_7NM_V4_1, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { @@ -1152,10 +1154,10 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { }, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_1, }; const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { - .type = MSM_DSI_PHY_7NM, .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { From patchwork Wed Mar 24 15:18:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407869 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502053jai; Wed, 24 Mar 2021 08:19:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIj9pjPjEtpwK6N7nc6g5Cv2l1PkDlsOjYk9zu2mXMVAi1vVDr1ybmlP223O/N0WQGJpGx X-Received: by 2002:a63:3485:: with SMTP id b127mr2331851pga.168.1616599173632; Wed, 24 Mar 2021 08:19:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599173; cv=none; d=google.com; s=arc-20160816; b=XklGtNjt7vflZ+ti4Uwei7uvD4fdc/PpT9vOZQy3UYbaOZCjTeSxoiE5mfoDkzrFfO K81ummrImUxvsv78hwFjg7JlCEesO4P26o0HRrNG0spLmorJACq82KscH8w6vFrqbpQa n1fxIsMiJQbli2AmeKNucQ3G/9Iyjngp4YZsK74vMxn76l6KZ7cuAzOs8B7KGoX1fUoe IaFaZlAVm40QNG1bVVZAKjW3gQOqt+4etft4KIS6oT+RKVOPDedQxyFVQLHjL3QKfNVp SN5K0bOLq16vggjiFVKH+5XZttPWs3GrZMqdrE+0Eq3OXmHYwZzzmYhIuuWoHg4rH5IR 4dkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=tHhYG4PSvhRoNKCnwEL5NUKepOFSaMQvJkzBQnTdeyw=; b=zDdGAUhHITOk6ieIMc0CIi6c8plgVnECfGdp2rwh/+hHs8xtO/w1fYW0TtOoqrKmq6 YVpntegJWUa0RAmLWfgkjBn90rpU4JeygNwiRXvbc92bDBV22c6RPFHCHb6LcmSQ6QLN tk/+HHi9uEj2laIFv3zOg8qTyU7oqj03JlLyD9UffWCWvz08CzxZjeE2YpWdiO4XK/Rs UuawhhKiIgLHiKOWiT4GJq8yTN7tlaG+Y+iEkkfLRHmDeFcMxp3JsRVEs8+UiEKHduYg yhvZI8BdBR2zqb8K8Lz2bIyBvPPgh1Cbl3bqCZcCmnSWPvDQ3OtDzMpPO0X5qna/k/zE ly4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDGANL1o; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id nv4si2365002pjb.172.2021.03.24.08.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDGANL1o; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC89B6EC84; Wed, 24 Mar 2021 15:19:22 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C0476EC6B for ; Wed, 24 Mar 2021 15:19:21 +0000 (UTC) Received: by mail-lf1-x12e.google.com with SMTP id a198so32535256lfd.7 for ; Wed, 24 Mar 2021 08:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kKmMzx9L+pGHn81TOLWWWuWPME7Tz9WZtHz+YDj8zLw=; b=aDGANL1opzNfRT1/KACZZ0pojd8tblP3uWWXcZvtJU3DCbO7x5g+x0jPbew2p/cK4p d7kZgMxUYpIU883gCoyXIDY83Gxi+5nglewjHgmMlPJyTatvsj8GJ/TJ5//K0CZeuia+ 6ME2VVW28N9fApCE+eBbp916zqqrFYqGVP/ScijRx7mYZQCtT9k0F8LCaexqX/9ZTcIA 2gALPqxsmyiRAVy2C9jgJqPU1WEUdaID5aKpgc99WdnbLod4iPXUHQs/TRTPlLUNBgk5 eUs0MjCON6sFEJ2pfdqxSS5IsOn7RrBOpR3WhqfZFRsO3lknn5+N04adR7cP9YkSCfK/ M+EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kKmMzx9L+pGHn81TOLWWWuWPME7Tz9WZtHz+YDj8zLw=; b=rdWhjPy3xFoU8XKN7izxJNWOzPEleyAKRv6B9SWTmyou+y19pn3KYKkZaEc68Ha8i7 Fg/gxjPXLvPPHdchcIgw7HMBg/3p0gaADlAOo9Y1Je3KvL2eG0g/m3sI3UhndxSjeZkJ paHGK64M+Gq9tpLYG8F5Qutv66J82NNou06dHh7gVIG2rhDYdWiDRTN74eYGidOISs7P D6GRe0jHxOU1zFsL2DePCOGQ47Z0JgwCVcxYNCl75OA5T2Cq08IpdZxWkMQ8UG4y+tsg +GaBSeWtuHuv0GBOq8C/yKlbAQ8+K4OaXU2Ob45x5JZLo5radDmPdUKfvI2N/SR8yfal NC1Q== X-Gm-Message-State: AOAM532lQZ6IML7dn/HeDvbe2NMc6cGrL8HcA6EoldgkZndvfdMo4vrn gMnBJ2jhpFOHpGHG3ANFT4qY3g== X-Received: by 2002:a19:f614:: with SMTP id x20mr2215089lfe.229.1616599160025; Wed, 24 Mar 2021 08:19:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:19 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 09/28] drm/msm/dsi: move min/max PLL rate to phy config Date: Wed, 24 Mar 2021 18:18:27 +0300 Message-Id: <20210324151846.2774204-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 ++++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 ++++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 8 ++++++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 ++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 8 ++++---- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 --- 8 files changed, 27 insertions(+), 23 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 39abb86446f9..000e4207dabc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg { struct msm_dsi_phy_ops ops; const struct msm_dsi_pll_ops pll_ops; + unsigned long min_pll_rate; + unsigned long max_pll_rate; + /* * Each cell {phy_id, pll_id} of the truth table indicates * if the source PLL selection bit should be set for each PHY. diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index dc8ccc994759..5f9d0cfc4e03 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_10nm->postdiv_lock); pll = &pll_10nm->base; - pll->min_rate = 1000000000UL; - pll->max_rate = 3500000000UL; pll->cfg = phy->cfg; pll_10nm->vco_delay = 1; @@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .restore_state = dsi_pll_10nm_restore_state, .set_usecase = dsi_pll_10nm_set_usecase, }, + .min_pll_rate = 1000000000UL, + .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, }; @@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .restore_state = dsi_pll_10nm_restore_state, .set_usecase = dsi_pll_10nm_set_usecase, }, + .min_pll_rate = 1000000000UL, + .max_pll_rate = 3500000000UL, .io_start = { 0xc994400, 0xc996400 }, .num_dsi_phy = 2, .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index d78f846cf8e4..8e4528301e5d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1078,8 +1078,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_14nm->postdiv_lock); pll = &pll_14nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; pll->cfg = phy->cfg; pll_14nm->vco_delay = 1; @@ -1237,6 +1235,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .disable_seq = dsi_pll_14nm_disable_seq, .enable_seq = dsi_pll_14nm_enable_seq, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0x994400, 0x996400 }, .num_dsi_phy = 2, }; @@ -1264,6 +1264,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .disable_seq = dsi_pll_14nm_disable_seq, .enable_seq = dsi_pll_14nm_enable_seq, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0xc994400, 0xc996000 }, .num_dsi_phy = 2, }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index bb33261d606d..d267b25e5da0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -625,8 +625,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) pll_28nm->vco_delay = 1000; else @@ -811,6 +809,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .disable_seq = dsi_pll_28nm_disable_seq, .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0xfd922b00, 0xfd923100 }, .num_dsi_phy = 2, }; @@ -837,6 +837,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .disable_seq = dsi_pll_28nm_disable_seq, .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0x1a94400, 0x1a96400 }, .num_dsi_phy = 2, }; @@ -863,6 +865,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .disable_seq = dsi_pll_28nm_disable_seq, .enable_seq = dsi_pll_28nm_enable_seq_lp, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0x1a98500 }, .num_dsi_phy = 1, .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 79b0842a8dc4..31e7910c6050 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -508,8 +508,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll->min_rate = VCO_MIN_RATE; - pll->max_rate = VCO_MAX_RATE; pll->cfg = phy->cfg; @@ -711,6 +709,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .disable_seq = dsi_pll_28nm_disable_seq, .enable_seq = dsi_pll_28nm_enable_seq, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, .io_start = { 0x4700300, 0x5800300 }, .num_dsi_phy = 2, }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 44ae495e8fca..4831d6769da7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -889,14 +889,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_7nm->postdiv_lock); pll = &pll_7nm->base; - pll->min_rate = 1000000000UL; - pll->max_rate = 3500000000UL; - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - pll->min_rate = 600000000UL; - pll->max_rate = (unsigned long)5000000000ULL; - /* workaround for max rate overflowing on 32-bit builds: */ - pll->max_rate = max(pll->max_rate, 0xffffffffUL); - } pll->cfg = phy->cfg; pll_7nm->vco_delay = 1; @@ -1152,6 +1144,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .restore_state = dsi_pll_7nm_restore_state, .set_usecase = dsi_pll_7nm_set_usecase, }, + .min_pll_rate = 600000000UL, + .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V4_1, @@ -1178,6 +1172,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .restore_state = dsi_pll_7nm_restore_state, .set_usecase = dsi_pll_7nm_set_usecase, }, + .min_pll_rate = 1000000000UL, + .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index c7ff0eba0e8b..e607adffe001 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -14,10 +14,10 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - if (rate < pll->min_rate) - return pll->min_rate; - else if (rate > pll->max_rate) - return pll->max_rate; + if (rate < pll->cfg->min_pll_rate) + return pll->cfg->min_pll_rate; + else if (rate > pll->cfg->max_pll_rate) + return pll->cfg->max_pll_rate; else return rate; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index 4fa73fbcba52..8306911f8318 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -18,9 +18,6 @@ struct msm_dsi_pll { bool pll_on; bool state_saved; - unsigned long min_rate; - unsigned long max_rate; - const struct msm_dsi_phy_cfg *cfg; }; From patchwork Wed Mar 24 15:18:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407871 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502091jai; Wed, 24 Mar 2021 08:19:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxR9FnABKpupg+9T8nb6g3AF7KMWvW9vMoGV/sxufY0ebmmLNDhPUoZEY1bZ1zclrb9hOG5 X-Received: by 2002:a17:90a:c902:: with SMTP id v2mr4073391pjt.144.1616599177332; Wed, 24 Mar 2021 08:19:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599177; cv=none; d=google.com; s=arc-20160816; b=w9sSits6RPdGRUl7kDaB59esj5GYms5el9bZdHr6wyNHnL1RtwOhRVoU767hC9z/bo +h6POD92DfcJ24ccsxPi84bHO4R04Hq+5cRqPAccs15VHb8kpfjAD0yDzy8bXpEDvoqn JUMAdUL8jSNkpaCpu6YRk9jgICmDAec1Y/bY7VztpDbV9uUy0dhyRge6SlgEn7KsFPpz fnOSDiGfe2eTjGdbKRKoAJsbxjr3tbXFvh9UfsFpXogCn6VXUyEi5cvxmKxZ6X0h4a8h mx6ADX+r2rYJiuYEsWaHsGrYLven6hayApqhJAFRf3Eow03//SfySjCEaEVwq7OqmN2o GhEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=5EZlBQCLjuSzUlv3Gq1qzmMcC8GG2H0LN89wPvBiFv0=; b=H43VpImPQJbqRjhTzA/cnQTAaImnpoXzh8+qvKaf2R9dJ3oos3K84NZ41hNIqpZHaH NHp4yxlTdXOX2vfSUUqSc7k0qojlSG0dCCoMLdxRjx+J2kYCUlLtnrflUreVTx4o5CaS Is0SFjraEIVmfx3J9rI99oWZF0hV6ttSL/9dHxP3xWQ3jI6g5UL/2hG43jiJAuuuIXWA /CwnZuStV75bE720ED9FtNkTsrKdY6z5X6sKYQNWnGzO+5M1bP0KiNK+dzthnT12cd60 vAcmkQ40Mvur+oZyf+swdXKCJn91g+pB96PjsqkcSX6m7IlnIu+il8AeTGhy0Ad+5Tos uj3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T8Ms+03l; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id l5si2547195pjh.79.2021.03.24.08.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T8Ms+03l; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA85C6EC82; Wed, 24 Mar 2021 15:19:26 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by gabe.freedesktop.org (Postfix) with ESMTPS id C409D6EC81 for ; Wed, 24 Mar 2021 15:19:22 +0000 (UTC) Received: by mail-lj1-x233.google.com with SMTP id z8so30635248ljm.12 for ; Wed, 24 Mar 2021 08:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zd6cvJ3+XU4QkBwijy37jRcuA9f/DooPKIPSb6ns/58=; b=T8Ms+03lwMnoEbvtcKLdULxswKsmdA9EtBfrVDzaBjZSt2elmj3Uc8pdvwGskq9j6x TERE30MqqUO1cZjVb4ta3kDlTjGHufstcaC4C8iENrbWjqr0AxMrtC2XTpH639rKZAsf K7LqBoRFhAT5FbJCeARusb08mPL+d1mKOE6Tzn6a/HA0yRtXJBFkti5vfqEVVAnLhHeC UKc+JGLbYJFYdjbCUrWKXNR2MKo0KgSKqO12t1KTlhyfxcJem0uXcCfrKdT3ODscVdgb 9D34IkiNEuvTxfJb3lpm1dCbhXgUm5PFLfTP5tO5cFuiJYDs6ElyRRPkULqcxy5pgI9z dl2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zd6cvJ3+XU4QkBwijy37jRcuA9f/DooPKIPSb6ns/58=; b=UD7dwyKi9wAos7KpPWd3/AyAb+VdOEYHjorwGH4pqRwHTlQGbZgyS5WlWo0yE9zNIK gxq4KIRXngJX4wSXmeQUJeKB9kao+ZnpNWdMweBnQjYArgo4HgCOVlQJ6i7kMd8i8ylh K9PdgIqXd44yJ6G9U1HH1JWwdH/mcRQdNjh6GInetuuJrm4ZuSiMwBoCm+aHT5sQTHFI Zp7VYTsqy4kqXCnro68UjELdP+zBtkDUOT+hoQo+ca2mHMExsNx4tf28zpreF2gb/TwJ aNkP7LLTjhwcYEiLeaNOuU3/p74BEoU08nfOvQcPgHEEnn7Z3MuJkgHQTpKNQf2aDrjT /IwQ== X-Gm-Message-State: AOAM532rEUHVw8Wq/rBJge5RJDc5Kf2hSqRXdbsCJVJPkGBN6bvwduO+ IchW5maDDrGnDRpeDUiKgezqaw== X-Received: by 2002:a2e:509:: with SMTP id 9mr2493424ljf.170.1616599161208; Wed, 24 Mar 2021 08:19:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:20 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 10/28] drm/msm/dsi: remove msm_dsi_pll_set_usecase Date: Wed, 24 Mar 2021 18:18:28 +0300 Message-Id: <20210324151846.2774204-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" msm_dsi_pll_set_usecase() function is not used outside of individual DSI PHY drivers, so drop it in favour of calling the the respective set_usecase functions directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 7 ------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 4 +--- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 +--- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 +--- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 9 --------- 6 files changed, 3 insertions(+), 27 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 98a4b296fa30..b310cf344ed4 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -100,8 +100,6 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_pll_save_state(struct msm_dsi_pll *pll); int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); -int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc); #else static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) { @@ -118,11 +116,6 @@ static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) { return 0; } -static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) -{ - return -ENODEV; -} #endif /* dsi host */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 000e4207dabc..f737bef74b91 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -29,8 +29,6 @@ struct msm_dsi_pll_ops { void (*destroy)(struct msm_dsi_pll *pll); void (*save_state)(struct msm_dsi_pll *pll); int (*restore_state)(struct msm_dsi_pll *pll); - int (*set_usecase)(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc); }; struct msm_dsi_phy_cfg { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 5f9d0cfc4e03..7a98e420414f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -1049,7 +1049,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, /* Select full-rate mode */ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40); - ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); + ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); @@ -1109,7 +1109,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, - .set_usecase = dsi_pll_10nm_set_usecase, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, @@ -1136,7 +1135,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, - .set_usecase = dsi_pll_10nm_set_usecase, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 8e4528301e5d..bab86fa6dc4b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1190,7 +1190,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL); - ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); + ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); @@ -1231,7 +1231,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, - .set_usecase = dsi_pll_14nm_set_usecase, .disable_seq = dsi_pll_14nm_disable_seq, .enable_seq = dsi_pll_14nm_enable_seq, }, @@ -1260,7 +1259,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, - .set_usecase = dsi_pll_14nm_set_usecase, .disable_seq = dsi_pll_14nm_disable_seq, .enable_seq = dsi_pll_14nm_enable_seq, }, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 4831d6769da7..5acdfe1f63be 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1064,7 +1064,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, /* Select full-rate mode */ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40); - ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); + ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); @@ -1142,7 +1142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, - .set_usecase = dsi_pll_7nm_set_usecase, }, .min_pll_rate = 600000000UL, .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, @@ -1170,7 +1169,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, - .set_usecase = dsi_pll_7nm_set_usecase, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index e607adffe001..98ee4560581a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -113,12 +113,3 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) return 0; } - -int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) -{ - if (pll->cfg->pll_ops.set_usecase) - return pll->cfg->pll_ops.set_usecase(pll, uc); - - return 0; -} From patchwork Wed Mar 24 15:18:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407873 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502135jai; Wed, 24 Mar 2021 08:19:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+Vbgtd3+fDcrDMFqI2Vc002yO/K88WQShh+UeyWIi1F5ZQddZn5vxGx5nQHLk9wVefg4o X-Received: by 2002:aa7:96f0:0:b029:1f3:97a4:19d2 with SMTP id i16-20020aa796f00000b02901f397a419d2mr3370838pfq.73.1616599180964; Wed, 24 Mar 2021 08:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599180; cv=none; d=google.com; s=arc-20160816; b=IOxcLpbZcXXdaa4oq30xM0aTxMP7FP4eJJHYV16M5gcWRMKv38tMDeBVzeGZWbog2B KjnFK32LsZ9XVgjgfyMKf21qIuYf0upc7Qwfhmb+I6H7GhHG8UPve/3fGM0hjId7Ox2a mh95xLxAm4Bpo1ecvVgR6HynTovKV0aPWY2XCmxnpHH+tmYamuYhcuBZ3mwDMss/pnYl 3jNhhw1PPFoPSE1L6pD4r2DJNwtAaBWfA+4IF8FGAxUU79lsWATAtRGj4VlVmxNQKdlz QDDi3h2MqL12w6EVg4MfkmHc8mniLyqamUKg6ngcrlv/eAwl6BHBpgNotibvpDcRQb1S VjVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=HyBc7BEAN93ld95eLXCw0FaVGlcGhSrQLXUkO3ajtrk=; b=q0eOl3udK9PfZuQt+3lEQeAiJfuqrIuQ8vEahUgL6zuS9VmOWpY1N+R/JXAVlFBxPz gUsnU7By72Tyrc+alNPEbiaCLI76bBBOuM/b6aIJYsfmL/mPVfJ8ZU1AdT/dwoFgJ0+z s7ttWN4qgOAA9JG5BjP9LrFzW34LInk63bswEZ5ZJWNkZCJlovqCp/wtGKoIqr3r5kdm 4QN8TWK/82WIV/QaiTm1DVo5db4mQ8tnwiCgaGBVssDaF67NtwIjGMuiZkh4XbY6fgq4 9Bc0y9igsINQ2Vhy8MTPVBVlsO2Q16xpQwjzMuorn5UeIfmGd1FqvdJoP9xsQu6NpSwd Udcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Ed+XD/CG"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id w11si2261870pll.56.2021.03.24.08.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="Ed+XD/CG"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A6436EC89; Wed, 24 Mar 2021 15:19:27 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 014B16EC81 for ; Wed, 24 Mar 2021 15:19:23 +0000 (UTC) Received: by mail-lj1-x233.google.com with SMTP id a1so30714648ljp.2 for ; Wed, 24 Mar 2021 08:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kW0sFoH+M/ls8iL96z0kdhIhD4PBh75ctweoW1FfopY=; b=Ed+XD/CGKCuGkTtIIWnFaPGB1Ul1O2zXrOQhC4AiIq1L6JTulfbvY1POoz/CuT+gRW YsZYwXOgsKFTms78S1doiiONGUJH4MxbtUdInWeEaYg9l0jwS7xzuyOuaxGoucfM5ABg imWLzb2b4nWfQXOgAfY/1+WIs7bUTKLT+6s+Wza0gm1JaVBN5pF3PQJKHm5LZmReH1ZX OTqB8+daJ/hzrDgIzuj5iUKqywzp8TzYgr/UylE1hF+Rx6RhiFjNa7f9d00RCniICqxB wJhd7mJeHKmAxqaOI5cGr+r6FpgxaGQCb9loPZzEnJnYC/xrxHcECU8pA4ksop6Xmbrz nuVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kW0sFoH+M/ls8iL96z0kdhIhD4PBh75ctweoW1FfopY=; b=dUhlh05rYeNWIxrORN3Q/PtQ3wN5AfG42csYLm9uy/qLvn8ORw4baHoewjNRhUmYHT RDUBPvqdYwqa1nHAqI/NhhdKC+fBlILC8BmSydGIM0r/FeEI2gcjdZMJ5iISMwbwFYK1 KL5HKnHs/RV8FG0kASCC3d6Qov7M76IsRy6pEJE/iW3qRWFAHMCV6U39JwjO9cDSDtZ+ 6HIJuDoUF/cERMgE95nF/5kzw43IfP8mx9DbM8DMIoQlltcxGh3MIZlEocj72jNAaoYr zjIR05O8qxMGieI4ln92666e6bbjf7l4y98x97OqJfDcxRaHLWB1pYhvAlIx8p84WIag xiRw== X-Gm-Message-State: AOAM533c/9c7g++Y10N52GnVQiqCHzYvwAAvgnnYCsJX8I/lLTCRrWO7 lqmF5M7Y7tTg/DlycZJamLCMGA== X-Received: by 2002:a2e:b613:: with SMTP id r19mr2415155ljn.300.1616599162318; Wed, 24 Mar 2021 08:19:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:21 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 11/28] drm/msm/dsi: stop setting clock parents manually Date: Wed, 24 Mar 2021 18:18:29 +0300 Message-Id: <20210324151846.2774204-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There is no reason to set clock parents manually, use device tree to assign DSI/display clock parents to DSI PHY clocks. Dropping this manual setup allows us to drop repeating code and to move registration of hw clock providers to generic place. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 9 ---- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 ------------------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ----- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 19 ------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 ------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 16 ------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 19 ------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 11 ---- 10 files changed, 175 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index b310cf344ed4..3614af64ff52 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -96,19 +96,12 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); struct msm_dsi_pll; #ifdef CONFIG_DRM_MSM_DSI_PLL void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); -int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_pll_save_state(struct msm_dsi_pll *pll); int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); #else static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) { } -static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider) -{ - return -ENODEV; -} static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) { } @@ -143,8 +136,6 @@ unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer); void msm_dsi_host_unregister(struct mipi_dsi_host *host); -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, - struct msm_dsi_pll *src_pll); void msm_dsi_host_reset_phy(struct mipi_dsi_host *host); void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, struct msm_dsi_phy_clk_request *clk_req, diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ab281cba0f08..bf3468ccc965 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2225,57 +2225,6 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, wmb(); } -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, - struct msm_dsi_pll *src_pll) -{ - struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - struct clk *byte_clk_provider, *pixel_clk_provider; - int ret; - - ret = msm_dsi_pll_get_clk_provider(src_pll, - &byte_clk_provider, &pixel_clk_provider); - if (ret) { - pr_info("%s: can't get provider from pll, don't set parent\n", - __func__); - return 0; - } - - ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - if (msm_host->dsi_clk_src) { - ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - - if (msm_host->esc_clk_src) { - ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - -exit: - return ret; -} - void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 1d28dfba2c9b..6b65d86d116a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -70,7 +70,6 @@ static int dsi_mgr_setup_components(int id) struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER); struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); - struct msm_dsi_pll *src_pll; int ret; if (!IS_DUAL_DSI()) { @@ -79,10 +78,6 @@ static int dsi_mgr_setup_components(int id) return ret; msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); - src_pll = msm_dsi_phy_get_pll(msm_dsi->phy); - if (IS_ERR(src_pll)) - return PTR_ERR(src_pll); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); } else if (!other_dsi) { ret = 0; } else { @@ -109,13 +104,6 @@ static int dsi_mgr_setup_components(int id) MSM_DSI_PHY_MASTER); msm_dsi_phy_set_usecase(clk_slave_dsi->phy, MSM_DSI_PHY_SLAVE); - src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy); - if (IS_ERR(src_pll)) - return PTR_ERR(src_pll); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); - if (ret) - return ret; - ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll); } return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index f737bef74b91..3e3ed884c3dc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -23,9 +23,6 @@ struct msm_dsi_phy_ops { struct msm_dsi_pll_ops { int (*enable_seq)(struct msm_dsi_pll *pll); void (*disable_seq)(struct msm_dsi_pll *pll); - int (*get_provider)(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider); void (*destroy)(struct msm_dsi_pll *pll); void (*save_state)(struct msm_dsi_pll *pll); int (*restore_state)(struct msm_dsi_pll *pll); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 7a98e420414f..319d7b26c784 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -621,23 +621,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; - - DBG("DSI PLL%d", pll_10nm->id); - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); @@ -1105,7 +1088,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .pll_init = dsi_pll_10nm_init, }, .pll_ops = { - .get_provider = dsi_pll_10nm_get_provider, .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, @@ -1131,7 +1113,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .pll_init = dsi_pll_10nm_init, }, .pll_ops = { - .get_provider = dsi_pll_10nm_get_provider, .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index bab86fa6dc4b..6f3021f66ecc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -880,21 +880,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data; - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); @@ -1227,7 +1212,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .pll_init = dsi_pll_14nm_init, }, .pll_ops = { - .get_provider = dsi_pll_14nm_get_provider, .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, @@ -1255,7 +1239,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .pll_init = dsi_pll_14nm_init, }, .pll_ops = { - .get_provider = dsi_pll_14nm_get_provider, .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index d267b25e5da0..83c73230266d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -495,21 +495,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) return 0; } -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - if (byte_clk_provider) - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; - if (pixel_clk_provider) - *pixel_clk_provider = - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; - - return 0; -} - static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); @@ -802,7 +787,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, @@ -830,7 +814,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, @@ -858,7 +841,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 31e7910c6050..0e26780e3eb4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -377,21 +377,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) return 0; } -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - if (byte_clk_provider) - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; - if (pixel_clk_provider) - *pixel_clk_provider = - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; - - return 0; -} - static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); @@ -702,7 +687,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .pll_init = dsi_pll_28nm_8960_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 5acdfe1f63be..7618f40ad45d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -646,23 +646,6 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data; - - DBG("DSI PLL%d", pll_7nm->id); - - if (byte_clk_provider) - *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); @@ -1138,7 +1121,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .pll_init = dsi_pll_7nm_init, }, .pll_ops = { - .get_provider = dsi_pll_7nm_get_provider, .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, @@ -1165,7 +1147,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .pll_init = dsi_pll_7nm_init, }, .pll_ops = { - .get_provider = dsi_pll_7nm_get_provider, .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 98ee4560581a..5768e8d225fc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -74,17 +74,6 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, /* * DSI PLL API */ -int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider) -{ - if (pll->cfg->pll_ops.get_provider) - return pll->cfg->pll_ops.get_provider(pll, - byte_clk_provider, - pixel_clk_provider); - - return -EINVAL; -} - void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) { if (pll->cfg->pll_ops.destroy) From patchwork Wed Mar 24 15:18:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407870 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502073jai; Wed, 24 Mar 2021 08:19:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx12zc7KrXEGd+lvnap8lp4+OOuHTMN2HNwm4irlN88aiXfP/3o0QdEBs/gL5anUel4d8z4 X-Received: by 2002:a17:90a:ba8b:: with SMTP id t11mr4097945pjr.177.1616599175781; Wed, 24 Mar 2021 08:19:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599175; cv=none; d=google.com; s=arc-20160816; b=xCNUr9acWMFxebW32rzzw8sMLkwISHPJcNY0GJ3fWbG866BY9k2QXcYs0Ki/vgiDwN +yzXPFnVhsd6IBJs6u3Apxo1b7bzKKPEOBhpn1vq0iOcSjcj6iILifWxo/D5ZbcTeiE5 l6XD3Il/INB7O9X//3Bo1cIUPSWVoVtAReoRPYMmP9KOsCPceCb864a6YRuxEOIZCN4l HkjLHDSLCjkac755XQgqSVG7vbMDkx2bKyY+0eSRS3BMvantlcS0gDEKxqEFlrS5Hhgs jPhSz9uicdOoEeSSTNao8oBTOwpCnInDgeugF5yWSL5/Hb/s4SOuHm2bUH0JVnxPw2eo agQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=UQpVKa0SenXAb027o+YtPB6B0j+DTPzd2XpRQUrO/VQ=; b=KDEqvsWnxmMBDZvk9yagoadLoH5ZXyEeMUyIC+Ihs52eQMOnvvhbMuCpYI5Bu24CXl 2oMdpVNj7Pgw2c72WufME2wSYO7vlFp15gOY5FWKjKvSFjNfxKLX69TsEqaj4DB0QYY1 +FS9ilVm4e1cfUI0Ngboc0bVg23gJWaOnOB+f+AEWEYlDQMChvcT2VSG/JHWHWZPxSvI T+we3tK5cPAmvTvXmzz58yt4XM0rrV6uuRu67Or2tawBHg8+lA2uhaLf6DxW89hMr+u1 dGGi22l+UD8BwyFLUcWXnvfqSXRS6WnSJrnnrEFDLw/WuBJNFtxSQdUp0Kudo6FzUkOm 4fOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HSrTD8Xd; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id v3si2416921pfu.333.2021.03.24.08.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HSrTD8Xd; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AA076EC81; Wed, 24 Mar 2021 15:19:26 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEFCD6EC87 for ; Wed, 24 Mar 2021 15:19:24 +0000 (UTC) Received: by mail-lj1-x22e.google.com with SMTP id z25so30671052lja.3 for ; Wed, 24 Mar 2021 08:19:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uOwO8iANW7saI2yo/rKV3plq3B/8JH8KOWGKGoDTU2M=; b=HSrTD8Xdjt+QEKCvw5WgkS71Vcl/EUopfIf3Af5r8fWOFz5Cym7/FQ+BFQIbmz8GFm cx296qZIIxdNR+2dlViqrjUNR3z6Ny7uz1sRisaFEpwEZL36NaNh6HQVdamNVdDzYEXF Ou2rzif4QfT4B4Dw22StjRHcQzPJCR0NSZ/TGTarLcPlvTEBDDQMnVdHqagDh51mfDBR KK3H86b9Dp5r4fZnexUoHrDBp9KArCKfj+sDZhBejAl5NfoNc/VLLZOQgKWcwV+xE/58 Y0bOgbHVSax9IPD4RGuNie0gL1y/QMv60SLXAj9nKUyvgapz5z+gUlaJKH9llFBMXT2h Pvyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOwO8iANW7saI2yo/rKV3plq3B/8JH8KOWGKGoDTU2M=; b=XwKp89Bw2RB5HzCXa5a7trcbVp+eB9dYHw72b7L4n1TDt3KGk41etZi17+4l+6DkGH lX8vZrN5KYU/e1mdEUWQCVvU2H2ZHVB8mNEMIopz5E+c9NXWX/fU/dEUXA6YbMw1RaMW +2SwlhZNHxc+McBGZZjtobfo1nZXcf+jSAdOXzRvXXRI0jFPVG2VyXSPSUYsFiVK5zgu EsaODNoAJLwMv1n5hn0rN0Jax9FzC7GetnIIvRjixr3CYyd4xXDh4S0QkR7TIOVVDmEw a/qussdQRLCBjBlagle6puY5QO5hA12jL6uNa5zfUZKbahUqUQ30MHOWU7v8v0oMcvMW 1Kaw== X-Gm-Message-State: AOAM533ys7yDTEOt4FECdzpvBYK7CIlxFaSV3T/cfKO0Ub6ETRCj7+kL iZ3FUEcDUJjR8vDRNNWQNpGFvA== X-Received: by 2002:a2e:b6c7:: with SMTP id m7mr2386715ljo.241.1616599163322; Wed, 24 Mar 2021 08:19:23 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:22 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 12/28] arm64: dts: qcom: sdm845: assign DSI clock source parents Date: Wed, 24 Mar 2021 18:18:30 +0300 Message-Id: <20210324151846.2774204-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bcf888381f14..8e0c5dfbd639 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4115,6 +4115,9 @@ dsi0: dsi@ae94000 { "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4181,6 +4184,9 @@ dsi1: dsi@ae96000 { "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; From patchwork Wed Mar 24 15:18:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407883 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502444jai; Wed, 24 Mar 2021 08:20:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz8o7PsBbf5lYDUBm1fat+w1hjeNMuMBROlet+6ovBzMpLz+Vyh8V4x02F2qEKBL0hbagEE X-Received: by 2002:a17:903:1cb:b029:e5:f712:c13c with SMTP id e11-20020a17090301cbb02900e5f712c13cmr4157293plh.22.1616599202988; Wed, 24 Mar 2021 08:20:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599202; cv=none; d=google.com; s=arc-20160816; b=m6PUo3X+bolGitn/ZfzLeikq6QqrCeFo7t32G4rvfri3p9hfrEsq54cQy3MuBSvNB8 7YZzLHxWpr5YBlVNLjVlHQaVrp1/6BOTyewfvT0jrvBBkgCAwDjVhF9gS6Hdx/wvHMPZ 7j5O9yuC+TjlZfKrhXa/6K6BthnybHPnTCpA3BKqfEgYSb6ztLJLNe/djmq5qnDBJ/Jt w2nirAeexeJzGvNf6bA9CGHxIVoS0K178ie/yIX9deLhSgt9a5HbWdI3MjmZ1mSaqH4L vjleFIqY32ioy4+rRS8vJ2N39KBohUum33CegNG1qaOxmQ0X404lhWrcTRFG4miTzMVd ekUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=/xIqQ0BIPHkkF0+5tozUBZzoWT/hOR2Fzza/tEvHm1k=; b=n3s77n73ayxoUOjvtpmCdiEWAjA+6+Pos+pEI2Sa5kKfNgo5bbpspQiqWpqiBsb4Ac MMG2Iwl59amKJsVe0/24ZxVRonHfhReTLoKSugt7VoLUaVVoQycT1UM5RMw6QDD8aYxg GXriq++NJ8VDRkrFjekKaSnJFvqFsQbkKSD9vcmftqLqAHV4qZgfx/lO5IuR0WYTaz8m LxouifNP7fUNpman5vqpvgkaPDN5XoWGQcu0CfOMLW5g5kzePIpHCFKhGqkzDt6bG2/F pqGhQr8zszgEn/795NUD0d4ysk2zwh5opWNiSFJz+Bn3v0E9jsZKKBVziGALRY9xRYUM 4uGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ahp+fVKP; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id ay9si2384866pjb.55.2021.03.24.08.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ahp+fVKP; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34C046EC78; Wed, 24 Mar 2021 15:19:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0B796EC81 for ; Wed, 24 Mar 2021 15:19:25 +0000 (UTC) Received: by mail-lf1-x12d.google.com with SMTP id b14so19284679lfv.8 for ; Wed, 24 Mar 2021 08:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d5gXnaS6/FhBtkbwF8y1QR9zxelWPPlPpq/TCaYVKkQ=; b=ahp+fVKPZwAYJOW7LBbtb9n9bOtkcZ8QEH92zF0ab5N9I6JC/bQAFlWBWCXj/7GxMY KXs1r/ByTAchuEe9IEHPZU0h+05/u29eJIiggZRbHuSnVAulRDX62LU5xFRFyLkUHNnL +oqsGuNEul9eDR/gWiAR/YPHklWTlVq1iwa2CIvvxNokMlgb3nskHwPfabCcQL1Fa1zL sd1p1G94PgZkt5kszyIIj2+jyLcg83O039DV/ojycQFbwB5EqIt01IgL78QLQHdVhxSf 2Lf490CyWN4LD+V8qFbEMm+gB16bQgXbpaWuEWEJF3BPBq/7zpKxrFtkkUuUjrcOOnHD 4MhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d5gXnaS6/FhBtkbwF8y1QR9zxelWPPlPpq/TCaYVKkQ=; b=QauDb9T1Bg4jgHsDnyWqy5Y9K1jeAdbgTc4Sk+aYqGsNrfYRrccyfAzKMhP1kGpsUo e45l6MFYO6+sjP6ZYbV924jwCy4eaIiywgXUz7z/z/FZihBiK/PuegtlQi3KF+PTwjVg AvCKIpc4x3NIDaKzLZhOdgti4gwPWf9tx5fpjjJ8r2lFwdITjtZUEm9ZCA7W+Dy1uRVl laagMK7Bg4MnsZHduP3bFmO3ya6RxM9REr3PH0l4pvtyHw0IiiroxTNvpgnrfyaOy/xv HBfmZIgr0Y10q29J+3j3WWINKuj2DCKzCZ3ZYfasKe+T0G9QRfPCYPpR2OA29lY6oYXh HTVg== X-Gm-Message-State: AOAM530q2Zc/4n2QvkhcNh1AQ+pE49o9E3o6yH/udCAirU1+MyoDevcn gOFQHDW+HBHOIecc+1r1xz6R/Q== X-Received: by 2002:ac2:4ac4:: with SMTP id m4mr2215124lfp.404.1616599164364; Wed, 24 Mar 2021 08:19:24 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:23 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 13/28] arm64: dts: qcom: sc7180: assign DSI clock source parents Date: Wed, 24 Mar 2021 18:18:31 +0300 Message-Id: <20210324151846.2774204-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 22b832fc62e3..c16ddabb3a92 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3076,6 +3076,9 @@ dsi0: dsi@ae94000 { "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; From patchwork Wed Mar 24 15:18:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407879 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502321jai; Wed, 24 Mar 2021 08:19:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFdC+N5zC6qY0jtoBeH3HJnvBarxy5pAVEPY6Bt2n/LOScXzZHUPKzzQVI/ngMJrGOa8M8 X-Received: by 2002:a62:a108:0:b029:1c1:119b:8713 with SMTP id b8-20020a62a1080000b02901c1119b8713mr3681753pff.74.1616599194796; Wed, 24 Mar 2021 08:19:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599194; cv=none; d=google.com; s=arc-20160816; b=PSv2To2nTQ9L03RHq8mQdotAdqnmf9+C2oSaCNGP6kjI8KA0S+IZTW6VMyiUaOGKZU 7My5jOjAIajRtPewAaksn2B1+QXGEg5SVlARdYG0xfz2lDTrqG9/yoDnObl8jnTHJT3d xdnIqqSI86XQkTSaHtz8UAiqD0AcePSlT98OYzpXoRAsUKDxus22sYpmPVFzqskMyucN z0RCX1nJkPw5oVR5ur7BWyHSpIReL75sXC16CGvXWQETj7S1s0mudkB8WmcjZH3+3JsW HjNGAtE5DXCbDbK5d2HZd8kkcQiDR8oUbL5gxVCiQn4paxw0hTCOHNLaKz2nQluWU7kI xzAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=3ELWw2kOr39+0FZiVywtKd40pa7f+wg2ga1EFtqopFg=; b=0usm0YUVGGhuh4OxRHG2SDozRoQcui95voOb+QerZ5A0EIHirGuqyZpqEEAEl0bFL0 MWOGFMO1DrkBZDUeuW/yiMD8bQVm/CFxOFX9qJ0nYrPnIOsHxbo1EhN8rYtKOhtPlRqw I4bP4kC4NcE/4lNK5PKtoGVWyNg/yUySwWRnfUmqxvZ9G5stf7ntnTU0MiqYLaEQj3Ru oi3GaZ+QVLpTCjV9+Ly8EtqgxuredL42bHgLuY2UOl4MpqUu3m4YFuzwuSzv6tdJDOrV qWR8a6vgU8Q15iGolxhkDP8G8z4RYxOB0/Wlgr9neK2N1MAPNbWA9ntA3op3JJoNVSfL YCpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="CMkUwp8/"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id y6si2433271plp.27.2021.03.24.08.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="CMkUwp8/"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7ABB26EC9A; Wed, 24 Mar 2021 15:19:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F02C6EC88 for ; Wed, 24 Mar 2021 15:19:27 +0000 (UTC) Received: by mail-lf1-x12f.google.com with SMTP id o126so23038907lfa.0 for ; Wed, 24 Mar 2021 08:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r+pZ6+V4PRaBdy5TK9d1InLteDXNH323N1ivMmzXSQo=; b=CMkUwp8/LG7XLXvFV5WrrtGK9vwOn5H7o1Dp8QY/61GA/H2c8oxXlH0V/kzNS5auvu FKzpK0FUQkX5xA9/JJ+paaxEK8QBpYtxENSsohSfu/xuXWbzhYXozEdY4eKhSK+kYz4p K+iQQAY0Df8fVxoRZW06OiDsjnPhn/gcG8FR6gW3F3ioHCO2NfD6I+s7tJ9lIX7UDiSm 4nJmTMpMblReJJQkAte7pQqIq7J6WRp18kBu/CP0aOaGG28tjlmkC5+0skjBtT5vI5YX Nc3qOmq0esswoPo+VGvG8arNHpifjx3IwhTLXVSKC0TnH7Kob76WZwjnT9Qz9hfLrYb+ 7e4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r+pZ6+V4PRaBdy5TK9d1InLteDXNH323N1ivMmzXSQo=; b=Ou9FYzS72ePeYabTb19ay21rAzEyPbsmbX8hFFg+isTkCg4wHFmiPjXNy8BUmTsxa1 RMP8MCgQsaE5IVrdtTSzW/jAOhj3XWIP8mxZyytEdCyoXFssKS5EJQbWVo2HCnMe51yf dgi1sDR7XHyByCIL8I+rt8MX6kK2QCj/5H3GQIFvIj/Isjgw5ZfaRAaK6/lEmKy3I4E+ GfOf4LZ4k/CDPaBWz2MjxjKBUlUSOUFskdM/sQkvwG1Osvcuc7Twj/y+iQ6iaE6JlPCK y967wyNJnw89KzRLOhPkXLDwqHFhZUQLY+sH+3vIi1l6B9JMT65Mi0p6cGQEdUwwjWaX TFMQ== X-Gm-Message-State: AOAM533gDIjj9g1Axv7cUmEnpXM98Z7DpTuLyJdAkyacSsuiRWYxLIK4 mycPQR/nelG7tTHoqWqmINgO0g== X-Received: by 2002:ac2:5e36:: with SMTP id o22mr2370414lfg.525.1616599165725; Wed, 24 Mar 2021 08:19:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 14/28] drm/msm/dsi: push provided clocks handling into a generic code Date: Wed, 24 Mar 2021 18:18:32 +0300 Message-Id: <20210324151846.2774204-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 23 ++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 6 +++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 36 ++------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 36 ++------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 45 ++++--------------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 41 ++++------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 36 ++------------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 5 +-- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 3 +- 9 files changed, 59 insertions(+), 172 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 5f153b683521..b01ba76adb9f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include "dsi_phy.h" @@ -652,6 +653,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) if (!match) return -ENODEV; + phy->provided_clocks = devm_kzalloc(dev, + struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS), + GFP_KERNEL); + if (!phy->provided_clocks) + return -ENOMEM; + + phy->provided_clocks->num = NUM_PROVIDED_CLKS; + phy->cfg = match->data; phy->pdev = pdev; @@ -719,6 +728,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } } + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + phy->provided_clocks); + if (ret) { + DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret); + goto fail; + } + dsi_phy_disable_resource(phy); platform_set_drvdata(pdev, phy); @@ -726,6 +742,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) return 0; fail: + if (phy->pll) { + of_clk_del_provider(dev->of_node); + msm_dsi_pll_destroy(phy->pll); + phy->pll = NULL; + } + return ret; } @@ -734,6 +756,7 @@ static int dsi_phy_driver_remove(struct platform_device *pdev) struct msm_dsi_phy *phy = platform_get_drvdata(pdev); if (phy && phy->pll) { + of_clk_del_provider(pdev->dev.of_node); msm_dsi_pll_destroy(phy->pll); phy->pll = NULL; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 3e3ed884c3dc..c3099629fa3b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -84,6 +84,10 @@ struct msm_dsi_dphy_timing { u8 hs_halfbyte_en_ckln; }; +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 +#define NUM_PROVIDED_CLKS 2 + struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; @@ -101,6 +105,8 @@ struct msm_dsi_phy { bool regulator_ldo_mode; struct msm_dsi_pll *pll; + + struct clk_hw_onecell_data *provided_clocks; }; /* diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 319d7b26c784..8666da1c29e5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -36,10 +36,6 @@ * dsi0_pll_post_out_div_clk */ -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 19200000 struct dsi_pll_regs { @@ -116,9 +112,6 @@ struct dsi_pll_10nm { struct clk_hw *pclk_mux_hw; struct clk_hw *out_dsiclk_hw; - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - struct pll_10nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -624,10 +617,8 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - struct device *dev = &pll_10nm->pdev->dev; DBG("DSI PLL%d", pll_10nm->id); - of_clk_del_provider(dev->of_node); clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); @@ -645,7 +636,7 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) * state to follow the master PLL's divider/mux state. Therefore, we don't * require special clock ops that also configure the slave PLL registers */ -static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) +static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks) { char clk_name[32], parent[32], vco_name[32]; char parent2[32], parent3[32], parent4[32]; @@ -657,18 +648,11 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) .ops = &clk_ops_dsi_pll_10nm_vco, }; struct device *dev = &pll_10nm->pdev->dev; - struct clk_hw_onecell_data *hw_data; struct clk_hw *hw; int ret; DBG("DSI%d", pll_10nm->id); - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); pll_10nm->base.clk_hw.init = &vco_init; @@ -720,7 +704,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) } pll_10nm->byte_clk_hw = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); @@ -780,22 +764,10 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) } pll_10nm->out_dsiclk_hw = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_10nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_10nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - goto err_dsiclk_hw; - } + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; -err_dsiclk_hw: - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); err_pclk_mux_hw: clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); err_post_out_div_clk_hw: @@ -851,7 +823,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm); + ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 6f3021f66ecc..07ecdf34f614 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -34,15 +34,10 @@ #define POLL_MAX_READS 15 #define POLL_TIMEOUT_US 1000 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 1300000000UL #define VCO_MAX_RATE 2600000000UL -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - #define DSI_PLL_DEFAULT_VCO_POSTDIV 1 struct dsi_pll_input { @@ -142,9 +137,6 @@ struct dsi_pll_14nm { struct clk_hw *hws[NUM_DSI_CLOCKS_MAX]; u32 num_hws; - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - struct pll_14nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -883,11 +875,8 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - struct platform_device *pdev = pll_14nm->pdev; int num_hws = pll_14nm->num_hws; - of_clk_del_provider(pdev->dev.of_node); - while (num_hws--) clk_hw_unregister(pll_14nm->hws[num_hws]); } @@ -928,7 +917,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, return &pll_postdiv->hw; } -static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) +static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks) { char clk_name[32], parent[32], vco_name[32]; struct clk_init_data vco_init = { @@ -940,19 +929,12 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) }; struct device *dev = &pll_14nm->pdev->dev; struct clk_hw **hws = pll_14nm->hws; - struct clk_hw_onecell_data *hw_data; struct clk_hw *hw; int num = 0; int ret; DBG("DSI%d", pll_14nm->id); - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); pll_14nm->base.clk_hw.init = &vco_init; @@ -983,7 +965,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) return PTR_ERR(hw); hws[num++] = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); @@ -1010,20 +992,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) return PTR_ERR(hw); hws[num++] = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; pll_14nm->num_hws = num; - hw_data->num = NUM_PROVIDED_CLKS; - pll_14nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_14nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - return 0; } @@ -1067,7 +1039,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm); + ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 83c73230266d..3446be318648 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -31,15 +31,10 @@ #define POLL_MAX_READS 10 #define POLL_TIMEOUT_US 50 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000 -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) @@ -83,10 +78,6 @@ struct dsi_pll_28nm { struct clk *clks[NUM_DSI_CLOCKS_MAX]; u32 num_clks; - /* clock-provider: */ - struct clk *provided_clks[NUM_PROVIDED_CLKS]; - struct clk_onecell_data clk_data; - struct pll_28nm_cached_state cached_state; }; @@ -498,20 +489,13 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - int i; - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, - pll_28nm->clks, pll_28nm->num_clks); - - for (i = 0; i < NUM_PROVIDED_CLKS; i++) - pll_28nm->provided_clks[i] = NULL; + msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks); pll_28nm->num_clks = 0; - pll_28nm->clk_data.clks = NULL; - pll_28nm->clk_data.clk_num = 0; } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { @@ -523,9 +507,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) }; struct device *dev = &pll_28nm->pdev->dev; struct clk **clks = pll_28nm->clks; - struct clk **provided_clks = pll_28nm->provided_clks; int num = 0; - int ret; DBG("%d", pll_28nm->id); @@ -549,11 +531,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = - clk_register_divider(dev, clk_name, + clks[num++] = clk_register_divider(dev, clk_name, parent1, 0, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, 0, 8, 0, NULL); + provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]); snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); @@ -566,22 +548,12 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = - clk_register_fixed_factor(dev, clk_name, + clks[num++] = clk_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 4); + provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]); pll_28nm->num_clks = num; - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; - pll_28nm->clk_data.clks = provided_clks; - - ret = of_clk_add_provider(dev->of_node, - of_clk_src_onecell_get, &pll_28nm->clk_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - return 0; } @@ -610,14 +582,13 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; + pll->cfg = phy->cfg; if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) pll_28nm->vco_delay = 1000; else pll_28nm->vco_delay = 1; - pll->cfg = phy->cfg; - - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 0e26780e3eb4..c4b433790cfb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -39,15 +39,10 @@ #define POLL_MAX_READS 8000 #define POLL_TIMEOUT_US 1 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 27000000 #define VCO_MIN_RATE 600000000 #define VCO_MAX_RATE 1200000000 -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - #define VCO_PREF_DIV_RATIO 27 struct pll_28nm_cached_state { @@ -76,10 +71,6 @@ struct dsi_pll_28nm { struct clk *clks[NUM_DSI_CLOCKS_MAX]; u32 num_clks; - /* clock-provider: */ - struct clk *provided_clks[NUM_PROVIDED_CLKS]; - struct clk_onecell_data clk_data; - struct pll_28nm_cached_state cached_state; }; @@ -381,11 +372,10 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, - pll_28nm->clks, pll_28nm->num_clks); + msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks); } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { char *clk_name, *parent_name, *vco_name; struct clk_init_data vco_init = { @@ -396,10 +386,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) }; struct device *dev = &pll_28nm->pdev->dev; struct clk **clks = pll_28nm->clks; - struct clk **provided_clks = pll_28nm->provided_clks; struct clk_bytediv *bytediv; struct clk_init_data bytediv_init = { }; - int ret, num = 0; + int num = 0; DBG("%d", pll_28nm->id); @@ -411,10 +400,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) if (!vco_name) return -ENOMEM; - parent_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!parent_name) - return -ENOMEM; - clk_name = devm_kzalloc(dev, 32, GFP_KERNEL); if (!clk_name) return -ENOMEM; @@ -442,29 +427,19 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) bytediv_init.num_parents = 1; /* DIV2 */ - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = - clk_register(dev, &bytediv->hw); + clks[num++] = clk_register(dev, &bytediv->hw); + provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]); snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); /* DIV3 */ - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = - clk_register_divider(dev, clk_name, + clks[num++] = clk_register_divider(dev, clk_name, parent_name, 0, pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, 0, 8, 0, NULL); + provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]); pll_28nm->num_clks = num; - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; - pll_28nm->clk_data.clks = provided_clks; - - ret = of_clk_add_provider(dev->of_node, - of_clk_src_onecell_get, &pll_28nm->clk_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - return 0; } @@ -496,7 +471,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) pll->cfg = phy->cfg; - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 7618f40ad45d..0b601afa9e49 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -36,10 +36,6 @@ * dsi0_pll_post_out_div_clk */ -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 19200000 struct dsi_pll_regs { @@ -116,9 +112,6 @@ struct dsi_pll_7nm { struct clk_hw *pclk_mux_hw; struct clk_hw *out_dsiclk_hw; - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - struct pll_7nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -649,10 +642,8 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - struct device *dev = &pll_7nm->pdev->dev; DBG("DSI PLL%d", pll_7nm->id); - of_clk_del_provider(dev->of_node); clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); @@ -670,7 +661,7 @@ static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) * state to follow the master PLL's divider/mux state. Therefore, we don't * require special clock ops that also configure the slave PLL registers */ -static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) +static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) { char clk_name[32], parent[32], vco_name[32]; char parent2[32], parent3[32], parent4[32]; @@ -682,18 +673,11 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) .ops = &clk_ops_dsi_pll_7nm_vco, }; struct device *dev = &pll_7nm->pdev->dev; - struct clk_hw_onecell_data *hw_data; struct clk_hw *hw; int ret; DBG("DSI%d", pll_7nm->id); - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); pll_7nm->base.clk_hw.init = &vco_init; @@ -745,7 +729,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) } pll_7nm->byte_clk_hw = hw; - hw_data->hws[DSI_BYTE_PLL_CLK] = hw; + provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); @@ -805,22 +789,10 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) } pll_7nm->out_dsiclk_hw = hw; - hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; - - hw_data->num = NUM_PROVIDED_CLKS; - pll_7nm->hw_data = hw_data; - - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - pll_7nm->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - goto err_dsiclk_hw; - } + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; -err_dsiclk_hw: - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); err_pclk_mux_hw: clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); err_post_out_div_clk_hw: @@ -876,7 +848,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm); + ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 5768e8d225fc..914e95435dcb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -57,11 +57,8 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) pll->pll_on = false; } -void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, - struct clk **clks, u32 num_clks) +void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks) { - of_clk_del_provider(pdev->dev.of_node); - if (!num_clks || !clks) return; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index 8306911f8318..d819a886beb8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -55,8 +55,7 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw); void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw); /* misc */ -void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, - struct clk **clks, u32 num_clks); +void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks); #endif /* __DSI_PLL_H__ */ From patchwork Wed Mar 24 15:18:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407875 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502188jai; Wed, 24 Mar 2021 08:19:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwvlG22EQlZKBTutN8tsmbCXdy/CtiXLjw7ChKiKoCggfq3kE4VdcoYdGpaXp6/aO53jYxv X-Received: by 2002:a17:902:7c88:b029:e6:f006:f8e5 with SMTP id y8-20020a1709027c88b02900e6f006f8e5mr4120406pll.1.1616599185009; Wed, 24 Mar 2021 08:19:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599185; cv=none; d=google.com; s=arc-20160816; b=L56UnW+8QYuTWx/wxhkpHtje6XcLNV3rGgYZoN9KV+K7JTWrB/hibCNGxmgNHWHo5a N1mkc4/hanLvgwxB1sEocYQEiwG/y/1OxxcpeCpEa43zk0WJH2v+DT1079j/A22KQqKp mWonuZBuMPdnN0i72t0le+0tpClsM7Q2xDFbdwKsyAJMPZA2LYxKzXyF8K/G9yQWWnKc ElJGLIqMWjIlXjjj6Kj8UFXU/PuiI78cdPpmRvkiH/ZKL2OImA3aTOiAXh1uoerWjru0 pRJw89TCdSpOh8+4sLsJz2/Lmy4wAfYupBAeH0n7uE7egQpQ2/krPWZ+xN1U1YmCEZHG NXsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=lEsx9KIJJn7TGVUuIV0PnvG5n1MkD0wdiKoNHeAtjcY=; b=mhQRuY7ZBBKngKxcgK8eb5KE8mmqbxmHxairXZWkpC2Q5qP664daazt901QDqiZLXk POQ8VCx3fpGPNrKEZJuTMakmpsoHb8qYX4260YNrvTVM2WAYpUEXc+JiBJvZPoZBuAMs 6oWkm/KyWZLmH0WF4gquwRmxKr6XASb98QV78i2OYYrBsiegVYcSEL5xJ0rnYGr3bi3U 4ZiA5gse/BaGQ76aeXUtk/S+4L3L6YVBCOEYI5OywMtmAre0ku1Z4TxBzVIkHDwQmvsc TDu48FBEG8Ihl5cL+3mCy1utDzbu9SIdXioeIdFQ+Wndgky4E/pJCR8jx9FnrQMr5zCu nzfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="TwVi/ZO1"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id d10si2606175pga.380.2021.03.24.08.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="TwVi/ZO1"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 751BF6EC8C; Wed, 24 Mar 2021 15:19:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by gabe.freedesktop.org (Postfix) with ESMTPS id D3E6C6EC8C for ; Wed, 24 Mar 2021 15:19:28 +0000 (UTC) Received: by mail-lf1-x136.google.com with SMTP id o10so32555872lfb.9 for ; Wed, 24 Mar 2021 08:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PYjsvJFTBcosviMkI0tWTDFDnjdVcUAI2MKwdSX6P8c=; b=TwVi/ZO16P8obM6foGAtEvRQu3nti0YPPfc5rDKiPZEvHMnRHwU007JpOpgOR5V2sC g60l1OS3TMUEk10OnOQrLXScTXL3H2kuMRRpPjZ7Zrdh8lKv77u5Yd7qKvT0GbBPCTNX HB5OrLx6GoLdR6OeZ7CnmmvO3TUgXH7n1Tu3wW0SDxG83PSAllwF92j6/VXzUXW83PCB zv57BH7Um8PIHCeo9zgZ4xjBI/mVETHazpv8ADYiU68UtKO9egqpdtAv8sYJFEmblPcL rTA5Z3q4BrPZuATQbcFh3Kkk4rqXbUcRndU2cFMgpGUlAQMHh3K3AzaXvih/ztbDNHz5 lZHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PYjsvJFTBcosviMkI0tWTDFDnjdVcUAI2MKwdSX6P8c=; b=jo6V14H54Chee1fOx1ELsIdcjPkffzgugw1G19H861gU91ErHIfuSuzErULMfRue8O rFG63EKigsMNgd2eEJef4ZS2u+iM8QJbsaYXJlyRtUX8LPb850gD+Gll3cPgJnByvuEF GiVYGceSr1DJJUj/JZwgJq9ISZ+a3oUaUOAwQg8/kB5h+6j8s+2rFGLYqdStx5Dsvs3Q wAMvV4uRRo7elV+eTJFVbAJzVCyHXy82HjwcqF47tNsteCJADqKKwd1rFsZLN4I6edkV OW6s1hHvm3drGhXcyJ5WS4a/4lDuPZ3jL05Wf+4gFtCAzLaO1OsCOo4idhyfSE5Zvp+z 084w== X-Gm-Message-State: AOAM531xGylvAjVxElEHr1uhaHXVVW5wf34PmI0jlJMZTirPgBkDCof4 vyVd9oR+u9uKE4wCgexaeWriSg== X-Received: by 2002:ac2:58fc:: with SMTP id v28mr2181410lfo.201.1616599167126; Wed, 24 Mar 2021 08:19:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:26 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 15/28] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Date: Wed, 24 Mar 2021 18:18:33 +0300 Message-Id: <20210324151846.2774204-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use devres-enabled version of clock registration functions. This lets us remove dsi_pll destroy callbacks completely. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 4 - drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 - drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 84 ++++--------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 35 +------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 50 +++++------ .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 39 +++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84 ++++--------------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 17 ---- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 4 - 10 files changed, 71 insertions(+), 249 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 3614af64ff52..1357fa15f320 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -95,13 +95,9 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); /* dsi pll */ struct msm_dsi_pll; #ifdef CONFIG_DRM_MSM_DSI_PLL -void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); void msm_dsi_pll_save_state(struct msm_dsi_pll *pll); int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); #else -static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) -{ -} static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) { } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index b01ba76adb9f..4a8577a08f57 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -744,7 +744,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) fail: if (phy->pll) { of_clk_del_provider(dev->of_node); - msm_dsi_pll_destroy(phy->pll); phy->pll = NULL; } @@ -757,7 +756,6 @@ static int dsi_phy_driver_remove(struct platform_device *pdev) if (phy && phy->pll) { of_clk_del_provider(pdev->dev.of_node); - msm_dsi_pll_destroy(phy->pll); phy->pll = NULL; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index c3099629fa3b..2c5196844ba9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -23,7 +23,6 @@ struct msm_dsi_phy_ops { struct msm_dsi_pll_ops { int (*enable_seq)(struct msm_dsi_pll *pll); void (*disable_seq)(struct msm_dsi_pll *pll); - void (*destroy)(struct msm_dsi_pll *pll); void (*save_state)(struct msm_dsi_pll *pll); int (*restore_state)(struct msm_dsi_pll *pll); }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 8666da1c29e5..6300b92c65eb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -103,15 +103,6 @@ struct dsi_pll_10nm { struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; - /* private clocks: */ - struct clk_hw *out_div_clk_hw; - struct clk_hw *bit_clk_hw; - struct clk_hw *byte_clk_hw; - struct clk_hw *by_2_bit_clk_hw; - struct clk_hw *post_out_div_clk_hw; - struct clk_hw *pclk_mux_hw; - struct clk_hw *out_dsiclk_hw; - struct pll_10nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -614,22 +605,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); - - DBG("DSI PLL%d", pll_10nm->id); - - clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); - clk_hw_unregister_divider(pll_10nm->bit_clk_hw); - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); - clk_hw_unregister(&pll_10nm->base.clk_hw); -} - /* * The post dividers and mux clocks are created using the standard divider and * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux @@ -656,30 +631,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); pll_10nm->base.clk_hw.init = &vco_init; - ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw); if (ret) return ret; snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id); - hw = clk_hw_register_divider(dev, clk_name, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_base_clk_hw; + goto fail; } - pll_10nm->out_div_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); /* BIT CLK: DIV_CTRL_3_0 */ - hw = clk_hw_register_divider(dev, clk_name, parent, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG0, @@ -687,56 +660,49 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov &pll_10nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_out_div_clk_hw; + goto fail; } - pll_10nm->bit_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, CLK_SET_RATE_PARENT, 1, 8); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_bit_clk_hw; + goto fail; } - pll_10nm->byte_clk_hw = hw; provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_byte_clk_hw; + goto fail; } - pll_10nm->by_2_bit_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_by_2_bit_clk_hw; + goto fail; } - pll_10nm->post_out_div_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); - hw = clk_hw_register_mux(dev, clk_name, + hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent, parent2, parent3, parent4 }), 4, 0, pll_10nm->phy_cmn_mmio + @@ -744,44 +710,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 0, 2, 0, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_post_out_div_clk_hw; + goto fail; } - pll_10nm->pclk_mux_hw = hw; - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = clk_hw_register_divider(dev, clk_name, parent, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, 0, pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG0, 4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_pclk_mux_hw; + goto fail; } - pll_10nm->out_dsiclk_hw = hw; provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; -err_pclk_mux_hw: - clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); -err_post_out_div_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); -err_by_2_bit_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); -err_byte_clk_hw: - clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); -err_bit_clk_hw: - clk_hw_unregister_divider(pll_10nm->bit_clk_hw); -err_out_div_clk_hw: - clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); -err_base_clk_hw: - clk_hw_unregister(&pll_10nm->base.clk_hw); +fail: return ret; } @@ -1060,7 +1010,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .pll_init = dsi_pll_10nm_init, }, .pll_ops = { - .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, }, @@ -1085,7 +1034,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .pll_init = dsi_pll_10nm_init, }, .pll_ops = { - .destroy = dsi_pll_10nm_destroy, .save_state = dsi_pll_10nm_save_state, .restore_state = dsi_pll_10nm_restore_state, }, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 07ecdf34f614..7fe7c8348b42 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -133,10 +133,6 @@ struct dsi_pll_14nm { u64 vco_current_rate; u64 vco_ref_clk_rate; - /* private clocks: */ - struct clk_hw *hws[NUM_DSI_CLOCKS_MAX]; - u32 num_hws; - struct pll_14nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -872,15 +868,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - int num_hws = pll_14nm->num_hws; - - while (num_hws--) - clk_hw_unregister(pll_14nm->hws[num_hws]); -} - static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, const char *name, const char *parent_name, @@ -910,7 +897,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; pll_postdiv->hw.init = &postdiv_init; - ret = clk_hw_register(dev, &pll_postdiv->hw); + ret = devm_clk_hw_register(dev, &pll_postdiv->hw); if (ret) return ERR_PTR(ret); @@ -928,9 +915,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov .ops = &clk_ops_dsi_pll_14nm_vco, }; struct device *dev = &pll_14nm->pdev->dev; - struct clk_hw **hws = pll_14nm->hws; struct clk_hw *hw; - int num = 0; int ret; DBG("DSI%d", pll_14nm->id); @@ -938,12 +923,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); pll_14nm->base.clk_hw.init = &vco_init; - ret = clk_hw_register(dev, &pll_14nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw); if (ret) return ret; - hws[num++] = &pll_14nm->base.clk_hw; - snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id); @@ -953,18 +936,15 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - hws[num++] = hw; - snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id); snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); /* DSI Byte clock = VCO_CLK / N1 / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, CLK_SET_RATE_PARENT, 1, 8); if (IS_ERR(hw)) return PTR_ERR(hw); - hws[num++] = hw; provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); @@ -974,12 +954,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider * on the way. Don't let it set parent. */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); if (IS_ERR(hw)) return PTR_ERR(hw); - hws[num++] = hw; - snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id); snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); @@ -991,11 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - hws[num++] = hw; provided_clocks[DSI_PIXEL_PLL_CLK] = hw; - pll_14nm->num_hws = num; - return 0; } @@ -1184,7 +1159,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .pll_init = dsi_pll_14nm_init, }, .pll_ops = { - .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, .disable_seq = dsi_pll_14nm_disable_seq, @@ -1211,7 +1185,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .pll_init = dsi_pll_14nm_init, }, .pll_ops = { - .destroy = dsi_pll_14nm_destroy, .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, .disable_seq = dsi_pll_14nm_disable_seq, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 3446be318648..3e9b7949b038 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -74,10 +74,6 @@ struct dsi_pll_28nm { int vco_delay; - /* private clocks: */ - struct clk *clks[NUM_DSI_CLOCKS_MAX]; - u32 num_clks; - struct pll_28nm_cached_state cached_state; }; @@ -486,15 +482,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) return 0; } -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks); - - pll_28nm->num_clks = 0; -} - static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; @@ -506,53 +493,63 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov .ops = &clk_ops_dsi_pll_28nm_vco, }; struct device *dev = &pll_28nm->pdev->dev; - struct clk **clks = pll_28nm->clks; - int num = 0; + struct clk_hw *hw; + int ret; DBG("%d", pll_28nm->id); snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm->base.clk_hw.init = &vco_init; - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw); + if (ret) + return ret; snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = clk_register_divider(dev, clk_name, + hw = devm_clk_hw_register_divider(dev, clk_name, parent1, CLK_SET_RATE_PARENT, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, 0, 4, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); - clks[num++] = clk_register_fixed_factor(dev, clk_name, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 2); + if (IS_ERR(hw)) + return PTR_ERR(hw); snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = clk_register_divider(dev, clk_name, + hw = devm_clk_hw_register_divider(dev, clk_name, parent1, 0, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, 0, 8, 0, NULL); - provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]); + if (IS_ERR(hw)) + return PTR_ERR(hw); + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); - clks[num++] = clk_register_mux(dev, clk_name, + hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent1, parent2 }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); - clks[num++] = clk_register_fixed_factor(dev, clk_name, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 4); - provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]); - - pll_28nm->num_clks = num; + if (IS_ERR(hw)) + return PTR_ERR(hw); + provided_clocks[DSI_BYTE_PLL_CLK] = hw; return 0; } @@ -758,7 +755,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, .disable_seq = dsi_pll_28nm_disable_seq, @@ -785,7 +781,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, .disable_seq = dsi_pll_28nm_disable_seq, @@ -812,7 +807,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, .disable_seq = dsi_pll_28nm_disable_seq, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index c4b433790cfb..45b2bf482392 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -64,13 +64,6 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; - /* custom byte clock divider */ - struct clk_bytediv *bytediv; - - /* private clocks: */ - struct clk *clks[NUM_DSI_CLOCKS_MAX]; - u32 num_clks; - struct pll_28nm_cached_state cached_state; }; @@ -368,13 +361,6 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) return 0; } -static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks); -} - static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { char *clk_name, *parent_name, *vco_name; @@ -385,10 +371,10 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov .ops = &clk_ops_dsi_pll_28nm_vco, }; struct device *dev = &pll_28nm->pdev->dev; - struct clk **clks = pll_28nm->clks; + struct clk_hw *hw; struct clk_bytediv *bytediv; struct clk_init_data bytediv_init = { }; - int num = 0; + int ret; DBG("%d", pll_28nm->id); @@ -404,14 +390,14 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (!clk_name) return -ENOMEM; - pll_28nm->bytediv = bytediv; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); vco_init.name = vco_name; pll_28nm->base.clk_hw.init = &vco_init; - clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw); + if (ret) + return ret; /* prepare and register bytediv */ bytediv->hw.init = &bytediv_init; @@ -427,18 +413,20 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov bytediv_init.num_parents = 1; /* DIV2 */ - clks[num++] = clk_register(dev, &bytediv->hw); - provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]); + ret = devm_clk_hw_register(dev, &bytediv->hw); + if (ret) + return ret; + provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw; snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); /* DIV3 */ - clks[num++] = clk_register_divider(dev, clk_name, + hw = devm_clk_hw_register_divider(dev, clk_name, parent_name, 0, pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, 0, 8, 0, NULL); - provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]); - - pll_28nm->num_clks = num; + if (IS_ERR(hw)) + return PTR_ERR(hw); + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; } @@ -662,7 +650,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .pll_init = dsi_pll_28nm_8960_init, }, .pll_ops = { - .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, .disable_seq = dsi_pll_28nm_disable_seq, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 0b601afa9e49..c482e51d1bee 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -103,15 +103,6 @@ struct dsi_pll_7nm { struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; - /* private clocks: */ - struct clk_hw *out_div_clk_hw; - struct clk_hw *bit_clk_hw; - struct clk_hw *byte_clk_hw; - struct clk_hw *by_2_bit_clk_hw; - struct clk_hw *post_out_div_clk_hw; - struct clk_hw *pclk_mux_hw; - struct clk_hw *out_dsiclk_hw; - struct pll_7nm_cached_state cached_state; enum msm_dsi_phy_usecase uc; @@ -639,22 +630,6 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, return 0; } -static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) -{ - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); - - DBG("DSI PLL%d", pll_7nm->id); - - clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw); - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); - clk_hw_unregister_divider(pll_7nm->bit_clk_hw); - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); - clk_hw_unregister(&pll_7nm->base.clk_hw); -} - /* * The post dividers and mux clocks are created using the standard divider and * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux @@ -681,30 +656,28 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); pll_7nm->base.clk_hw.init = &vco_init; - ret = clk_hw_register(dev, &pll_7nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw); if (ret) return ret; snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id); - hw = clk_hw_register_divider(dev, clk_name, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_base_clk_hw; + goto fail; } - pll_7nm->out_div_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); /* BIT CLK: DIV_CTRL_3_0 */ - hw = clk_hw_register_divider(dev, clk_name, parent, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG0, @@ -712,56 +685,49 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide &pll_7nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_out_div_clk_hw; + goto fail; } - pll_7nm->bit_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, CLK_SET_RATE_PARENT, 1, 8); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_bit_clk_hw; + goto fail; } - pll_7nm->byte_clk_hw = hw; provided_clocks[DSI_BYTE_PLL_CLK] = hw; snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_byte_clk_hw; + goto fail; } - pll_7nm->by_2_bit_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - hw = clk_hw_register_fixed_factor(dev, clk_name, parent, + hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_by_2_bit_clk_hw; + goto fail; } - pll_7nm->post_out_div_clk_hw = hw; - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); - hw = clk_hw_register_mux(dev, clk_name, + hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent, parent2, parent3, parent4 }), 4, 0, pll_7nm->phy_cmn_mmio + @@ -769,44 +735,28 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 0, 2, 0, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_post_out_div_clk_hw; + goto fail; } - pll_7nm->pclk_mux_hw = hw; - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id); snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = clk_hw_register_divider(dev, clk_name, parent, + hw = devm_clk_hw_register_divider(dev, clk_name, parent, 0, pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); - goto err_pclk_mux_hw; + goto fail; } - pll_7nm->out_dsiclk_hw = hw; provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; -err_pclk_mux_hw: - clk_hw_unregister_mux(pll_7nm->pclk_mux_hw); -err_post_out_div_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->post_out_div_clk_hw); -err_by_2_bit_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->by_2_bit_clk_hw); -err_byte_clk_hw: - clk_hw_unregister_fixed_factor(pll_7nm->byte_clk_hw); -err_bit_clk_hw: - clk_hw_unregister_divider(pll_7nm->bit_clk_hw); -err_out_div_clk_hw: - clk_hw_unregister_divider(pll_7nm->out_div_clk_hw); -err_base_clk_hw: - clk_hw_unregister(&pll_7nm->base.clk_hw); +fail: return ret; } @@ -1093,7 +1043,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .pll_init = dsi_pll_7nm_init, }, .pll_ops = { - .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, }, @@ -1119,7 +1068,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .pll_init = dsi_pll_7nm_init, }, .pll_ops = { - .destroy = dsi_pll_7nm_destroy, .save_state = dsi_pll_7nm_save_state, .restore_state = dsi_pll_7nm_restore_state, }, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 914e95435dcb..96de79b94f1b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -57,26 +57,9 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) pll->pll_on = false; } -void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks) -{ - if (!num_clks || !clks) - return; - - do { - clk_unregister(clks[--num_clks]); - clks[num_clks] = NULL; - } while (num_clks); -} - /* * DSI PLL API */ -void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) -{ - if (pll->cfg->pll_ops.destroy) - pll->cfg->pll_ops.destroy(pll); -} - void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) { if (pll->cfg->pll_ops.save_state) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index d819a886beb8..c94f079b8275 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -11,8 +11,6 @@ #include "dsi.h" -#define NUM_DSI_CLOCKS_MAX 6 - struct msm_dsi_pll { struct clk_hw clk_hw; bool pll_on; @@ -54,8 +52,6 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw); void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw); -/* misc */ -void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks); #endif /* __DSI_PLL_H__ */ From patchwork Wed Mar 24 15:18:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407874 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502164jai; Wed, 24 Mar 2021 08:19:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyVxm7B/1v0FOQE5FMhusfOOxl5CtVeMjKnGA3MsU30+sBLToevWlfP0AAB0Dd/CLnoYa/ X-Received: by 2002:a17:90a:ff05:: with SMTP id ce5mr3928521pjb.156.1616599182841; Wed, 24 Mar 2021 08:19:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599182; cv=none; d=google.com; s=arc-20160816; b=n0tNdR1eCfa5Wgi56T+QNzlEFgqmHunnaXm3Imj19qpET7ybQ7HOdH/Pap/3V2L3U3 5O57wZOceXZim5vw0RzVzrbfGvc1Z2o6lCl+2rbVXboR/OkRTSHVyLcmlCDBGf1L9kiM Bz4yzQF+f+PoFbmN4KUm+oJZPubVZT1Q9ZuT82OnWUVKCfOWNbasDCj24NRaZWnYt5a6 HWqt26syxHIpyY/VyNm4JnDi/xPT0ahARrpQcppzG7urEKCuaQXVmR19P6mO2RZqq6pM ex2xzu19J7wpeh+kH+mFnx6GrcjTRwDGt5MDITfd9lIVn2QvrbY0POqVtTZRYKKEddb5 XRyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=ljQgJF7yAqYvfuz3+8qFZjFvbp2Z4BSJcRR02ie0YGw=; b=GF8Ym2g4HYo/ytbvR9UwQ5cixxXsFNFylZ0Wz+dgpNCv44VJYupL1H/SwUBIFxHYxI jAENKyCM0EzGe0WcJdQRZ6TU+o0maR0TU1qHHqxAaPP5lJXHy4yqKgHsGpKKGO01WfgK V0E/iOXEEEth/rnr3YqhVPq+kIh70u8Q6NR4FiAMMTMONWvisjIrOpr3lA5xqUIeaKTi LcwNw/hIRfz9aYBBY+wkE5Nk+PTGzgk16iAefPkT9aBXpJdobNpFW8vWWNMxDqO0L2Em 1JoqCI94iTR27VQ8WMUkk3P7uofnTI220YXW4Hf2vW17/l0kmEm2JUwD18cvXdig9V8p 4Fng== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tc25TD5+; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id l1si2390082plt.82.2021.03.24.08.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tc25TD5+; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 155FE6EC5D; Wed, 24 Mar 2021 15:19:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31E046EA1F for ; Wed, 24 Mar 2021 15:19:30 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id w37so32506798lfu.13 for ; Wed, 24 Mar 2021 08:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cjAMUv7MIhb1KdQ27o54N1t7Ve1qx874G712Y764Vm0=; b=Tc25TD5+7Gwo1HO4vQj/3EiBeyJcsnhH7fA3aeCN5TNcqbP/oVU4HMDFXqOtqwP+P2 Zdq93VMu2vCBVadNX3nvEKyzRcDkbHi5u2/7Avu8aDQtVOtDidA95usU5UlmTP+MJ/R6 sVguu0bJ75WatTP8XaB3NJPDsLzgw/cpxzjobzcFr8p3kaQeKo57bqtNmE82PfYjpSy1 ALGNzNRoBz1hiCw566AJcCM/S2N5vCB83Fk0QWPJT3VWfBIoZiTqvExohdsc93hFEM+I m2YFbOjtRW6ndpLOdLmt8Zb49bk/7dz3sjQR81yB/rfa3Un0WCyMj02Fn14szlge6Tfv vP1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cjAMUv7MIhb1KdQ27o54N1t7Ve1qx874G712Y764Vm0=; b=s4Xq99b8wpXZMFSO97zWG7/M80/hYpJcfMFbQpMWrqeyUHkZAb7Xp7p8BuA5CgXxWt hE5dLyHOfVhjlsH07g8KEL0tTjXc3HJw0AphLc0a99pKnzGXdeeE47ZYD2a3neFGJnmT 90x2dJMXpVbUmsm+6Ad89pHKKzrYJ9ZFldT3kwjbF6WaWtMOE5ApWtceUh8UMfqLMDTx ecN/sIulI3lREFJUqzfn/g7Zjm7Geg1Fj95sT45PPo+T6p6ApldTVOKL7pjvAhvDkfk7 c4rGP2+Pqm8e3Ekk3BStVGiTAnZnB3XaFsDIUtBMleTA9Np993sDrwZEeWUV/Go7z2gB TMWg== X-Gm-Message-State: AOAM5339/VW8NKpuVhKDOSWWxLCOdd+tpI2oGxq2cdBEIPy8zYNDwF48 aS1X/oaw9YhWi99/wIhjNZKKQQ== X-Received: by 2002:ac2:5fa2:: with SMTP id s2mr2232448lfe.486.1616599168652; Wed, 24 Mar 2021 08:19:28 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:27 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 16/28] drm/msm/dsi: use devm_of_clk_add_hw_provider Date: Wed, 24 Mar 2021 18:18:34 +0300 Message-Id: <20210324151846.2774204-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use devm_of_clk_add_hw_provider() to register provided clocks. This allows dropping the remove function alltogether. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 4a8577a08f57..74a4e2daade8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -728,7 +728,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } } - ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret); @@ -742,31 +742,11 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) return 0; fail: - if (phy->pll) { - of_clk_del_provider(dev->of_node); - phy->pll = NULL; - } - return ret; } -static int dsi_phy_driver_remove(struct platform_device *pdev) -{ - struct msm_dsi_phy *phy = platform_get_drvdata(pdev); - - if (phy && phy->pll) { - of_clk_del_provider(pdev->dev.of_node); - phy->pll = NULL; - } - - platform_set_drvdata(pdev, NULL); - - return 0; -} - static struct platform_driver dsi_phy_platform_driver = { .probe = dsi_phy_driver_probe, - .remove = dsi_phy_driver_remove, .driver = { .name = "msm_dsi_phy", .of_match_table = dsi_phy_dt_match, From patchwork Wed Mar 24 15:18:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407880 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502356jai; Wed, 24 Mar 2021 08:19:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsiah49qF5yzJ8GfmkjHcSPBQpwUHbSht+NnILwxovGCEztkI8tVfWRAmH6BB3Gn8Dmo61 X-Received: by 2002:aa7:8dda:0:b029:1fa:19b3:7ed9 with SMTP id j26-20020aa78dda0000b02901fa19b37ed9mr3729367pfr.32.1616599197256; Wed, 24 Mar 2021 08:19:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599197; cv=none; d=google.com; s=arc-20160816; b=fhcsPcis+6hPHE9FILwcgNeF6gVR9FQT46i0hb4bNd+AffYzjGBD+bGxjw3f0x1WuI RW2tCQgn+3IveIZ8Ifln8+t0w6zv6CHbjTw/Adgtw1dUHOW8DmiA9f/thI/GNn8IccAa n+TDDruBX9zvJVaesQeo9g07DJJtBTQaBw7UMoMauNyhSt0aPTWmahImO0rBecMmPd97 GTpDN9YPd4IiT4GbRyfh6EYc+J8xAMy/BUEKcpdtLUXglYsMnKbKIW7VssR3h4wepH+R pODzRMOZ6Pes4niIpWOLj3W6aSr7nEp/Lv0tpMd6UWFKJEGJrdYVIFnhr4EH9EvIbj3g GlSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=ywZ7RgGe4NN5e5jRNE1CacIwTkHB9kZ8JjC5WfYvD8w=; b=rOLEZrgl0HnnE7G15oIurplyuZr/WBth8wLuOK+N2ZunESYbuDJce9fHagJNk7LFdp mDhZwQtXGS4bxKDVXB2DT+uPS5RZdL8cIChdtzpAqTbMpua5QDE2Nur7hPzz5QHU5HAt 620CjuODH6vDiwFZGDgHaASD98B6r2FXEgfWQwGJgsTosh+SmF9t9HLmjnKd6zY0p3d9 Ra3H6x7AO5s090yv7B67jV4qeijWYHpdjOdfNxcc0u5MYUr2Ivoz5v6n6ZQYzZjPdbk2 57FjTjYStlgwS5H+j08mj/jExgBgYh/cU4z49smBzfenCrjlWAYdlECFYfPnK22bQXM+ 981A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UZiUs5DZ; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id n2si2499951pgi.18.2021.03.24.08.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UZiUs5DZ; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8873A6ECA2; Wed, 24 Mar 2021 15:19:44 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76A3F6EC5D for ; Wed, 24 Mar 2021 15:19:31 +0000 (UTC) Received: by mail-lf1-x12c.google.com with SMTP id a198so32535980lfd.7 for ; Wed, 24 Mar 2021 08:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gPEBJGZHxZvASfnJl5UyU4ySRa9bo19Qh8IfkJJg4KI=; b=UZiUs5DZYUtSqmR8x4nciwVqKTI7wqKlG5uIqihsEQkKVrl+RJhibIz8sTdSUNq1a/ 17xQ+Q/zIvW5VFtdgsMcnaDrTirg9PA8esZY0pMCZCIoSITk96o1qm29XmoWeRVLlihY SwHemcl5T0lffLIrzdx6oUO+zz3kBk5VdpANwNiUMqffNirofVva3TTXQSWPq22mD9NZ 05JvxC0eW5rf+bKqj0cFZnWXQon13biDLpwN7IEH9j8cnFBkp90rvVjPFGPUI8ePNwyZ O9HbvjB915uJToHaVZfAV69XS1qyEHRKkijnYQVdwYVbizN+egvysckbKm3CLHOJ7KT+ Ougg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gPEBJGZHxZvASfnJl5UyU4ySRa9bo19Qh8IfkJJg4KI=; b=YiIJlEMOX7HPmNIsjAZIgwdrnMFu7E9z6/G4fFzZ/BDrRD2QW5zoLE1d7SUYzf4Qly ZepvJyx6kR44K1lOzoT1ZGX+tfI2jQGiZMYNkV6P/WGK/Wh098B5fGW5PcJHlwqxhL+y OxJ8Q66MbPiRKfvU3tgbJmu5C+E2rnRCY+esSmflzryBGuqX7B1vTj8uGmdY2Iec/d0A 8qE7FN0w4mEio7rUVHA2P47U/T7kQuzNcwFVGFG5UGdS9DlPIVuj/LEcQt0ZlYgm3brx 2EauiTE00XzpoQkZ9QFAajuvVdFD5YygQyKTgl57Nj+sx3fhs83XoGPXQ/I5aM/yPTyX snLg== X-Gm-Message-State: AOAM5322bqnp0k4hRjLhZDeWQKpsHqpoBtptM9tQUgxQyAgeaPW1O1d7 Q0x0eilWV2UZZIJnwhzwagD57A== X-Received: by 2002:a05:6512:20d9:: with SMTP id u25mr2157061lfr.452.1616599169890; Wed, 24 Mar 2021 08:19:29 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:29 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 17/28] drm/msm/dsi: make save/restore_state phy-level functions Date: Wed, 24 Mar 2021 18:18:35 +0300 Message-Id: <20210324151846.2774204-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(), thus removing last bits of knowledge about msm_dsi_pll from dsi_manager. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 18 ++--------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 35 +++++++++++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 26 ---------------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 11 ------- 8 files changed, 42 insertions(+), 69 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 1357fa15f320..5c32ee2b3605 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -92,21 +92,6 @@ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); -/* dsi pll */ -struct msm_dsi_pll; -#ifdef CONFIG_DRM_MSM_DSI_PLL -void msm_dsi_pll_save_state(struct msm_dsi_pll *pll); -int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); -#else -static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) -{ -} -static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) -{ - return 0; -} -#endif - /* dsi host */ struct msm_dsi_host; int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, @@ -180,9 +165,10 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, void msm_dsi_phy_disable(struct msm_dsi_phy *phy); void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, struct msm_dsi_phy_shared_timings *shared_timing); -struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); +void msm_dsi_phy_save_state(struct msm_dsi_phy *phy); +int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy); #endif /* __DSI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 6b65d86d116a..2976b09a881d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -493,7 +493,6 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; struct drm_panel *panel = msm_dsi->panel; - struct msm_dsi_pll *src_pll; bool is_dual_dsi = IS_DUAL_DSI(); int ret; @@ -527,9 +526,8 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) id, ret); } - /* Save PLL status if it is a clock source */ - src_pll = msm_dsi_phy_get_pll(msm_dsi->phy); - msm_dsi_pll_save_state(src_pll); + /* Save PHY status if it is a clock source */ + msm_dsi_phy_save_state(msm_dsi->phy); ret = msm_dsi_host_power_off(host); if (ret) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 74a4e2daade8..7d23371a83f6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -799,9 +799,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, * source. */ if (phy->usecase != MSM_DSI_PHY_SLAVE) { - ret = msm_dsi_pll_restore_state(phy->pll); + ret = msm_dsi_phy_restore_state(phy); if (ret) { - DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n", + DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n", __func__, ret); goto pll_restor_fail; } @@ -838,17 +838,32 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, sizeof(*shared_timings)); } -struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy) -{ - if (!phy) - return NULL; - - return phy->pll; -} - void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc) { if (phy) phy->usecase = uc; } + +void msm_dsi_phy_save_state(struct msm_dsi_phy *phy) +{ + if (phy->cfg->pll_ops.save_state) { + phy->cfg->pll_ops.save_state(phy->pll); + phy->pll->state_saved = true; + } +} + +int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy) +{ + int ret; + + if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) { + ret = phy->cfg->pll_ops.restore_state(phy->pll); + if (ret) + return ret; + + phy->pll->state_saved = false; + } + + return 0; +} diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 2c5196844ba9..8133732e0c7f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -6,6 +6,7 @@ #ifndef __DSI_PHY_H__ #define __DSI_PHY_H__ +#include #include #include "dsi.h" @@ -13,6 +14,16 @@ #define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset)) +struct msm_dsi_pll { + struct clk_hw clk_hw; + bool pll_on; + bool state_saved; + + const struct msm_dsi_phy_cfg *cfg; +}; + +#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) + struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 6300b92c65eb..e0df12a841b2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -782,7 +782,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) phy->pll = pll; /* TODO: Remove this when we have proper display handover support */ - msm_dsi_pll_save_state(pll); + msm_dsi_phy_save_state(phy); return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c482e51d1bee..e6c8040e1bd3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -807,7 +807,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) phy->pll = pll; /* TODO: Remove this when we have proper display handover support */ - msm_dsi_pll_save_state(pll); + msm_dsi_phy_save_state(phy); return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 96de79b94f1b..652c2d6bfeec 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -56,29 +56,3 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) pll->pll_on = false; } - -/* - * DSI PLL API - */ -void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) -{ - if (pll->cfg->pll_ops.save_state) { - pll->cfg->pll_ops.save_state(pll); - pll->state_saved = true; - } -} - -int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) -{ - int ret; - - if (pll->cfg->pll_ops.restore_state && pll->state_saved) { - ret = pll->cfg->pll_ops.restore_state(pll); - if (ret) - return ret; - - pll->state_saved = false; - } - - return 0; -} diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index c94f079b8275..eca13cf67c21 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -6,21 +6,10 @@ #ifndef __DSI_PLL_H__ #define __DSI_PLL_H__ -#include #include #include "dsi.h" -struct msm_dsi_pll { - struct clk_hw clk_hw; - bool pll_on; - bool state_saved; - - const struct msm_dsi_phy_cfg *cfg; -}; - -#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) - static inline void pll_write(void __iomem *reg, u32 data) { msm_writel(data, reg); From patchwork Wed Mar 24 15:18:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407884 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502485jai; Wed, 24 Mar 2021 08:20:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJ/jmNhzJno7yDpmTSLyVLO0zWJit+012X2ImcHmVRPlenaJ7xZkCnwhdTYi5OSMPYmsQ7 X-Received: by 2002:a17:902:265:b029:e6:cc0f:ce79 with SMTP id 92-20020a1709020265b02900e6cc0fce79mr4120143plc.11.1616599205912; Wed, 24 Mar 2021 08:20:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599205; cv=none; d=google.com; s=arc-20160816; b=DinrHeiwb3otAtu4PGdmXBn7Xou4gS+k/r7OlLu4h3r82jqiWgqoiRlv1HFzbHJZmQ Ix/eaanIp43m+6IAxLzSHEkbQiWhu8b4e68KocbO90lOaXz0SiyIwEB40tN5aokAFURI /xoWeFUjoSRn34jktZcR/Wl21CN+2yyIhmCuRJwtWGZfJ9NDon09lEy6uCD4ywZnpmnE 1KZzyFrSg813c3gxM0/l3yIE4T0zrj2pXDS3pMTIL7DTIrIxty1HuT6KpZ1Bfz63S6WM hkDe4g7vL1QIGevRlQB3YCTjU7+57h5tJMt9n+4wgNZPuM/PWqKm/CGF8NMwWCzdboae 1/OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=wE9MnP0syqPTk9mbtWq+fnYm+Kjvl0hxsjPSwBNwSPA=; b=ZOBn7WgIs0AgABY+CPmX7sN0datatA8iBFatXBXc0bL9qsHZL3upV9SdZ+jZhPAYS/ 069JqTmNED6aZHFOFCi0tCKtzASr74Pn8RVL0aofpPNt3H4rEvbzz4EKZCpq8WuRjfPU o2TAUgW/n1iFWQxtz7ljU51wkPdL4dnYHaGfsh9DDyj6QWCL+MGlCCxn7Flk16xxu6Ed JFMLYHATbgcxMxTSEN9GtO4V1ooSMseSFvkPuRy4Qi1EBfylCaxjbtzXQUMyQ/64iThz oi12Ssm3YPRZiQkQnJkBJ/2OuyelLysFl8T8xqVfjegk4kHFNjsqCQKfOGgDQzrNbiim 3oeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kVQxFEwR; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id v197si2560830pfc.135.2021.03.24.08.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kVQxFEwR; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF1806EC9C; Wed, 24 Mar 2021 15:19:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by gabe.freedesktop.org (Postfix) with ESMTPS id B37FF6EC8D for ; Wed, 24 Mar 2021 15:19:32 +0000 (UTC) Received: by mail-lf1-x12c.google.com with SMTP id n138so32539212lfa.3 for ; Wed, 24 Mar 2021 08:19:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F6SPcQ3rOU1M+d5rn+hxpcarF5MAsSjTj9sicv1mJgY=; b=kVQxFEwRg/dLwRA58uX0wgY9+ikO6I2UA9DHxCfFo2gRFYG0owX0OUSrEMtOo8pOlO YZc9oYXf+9Nlu2uogQA+wpGjtEHv1e4QD+C+YgoAXURFYCKEBf7EXBEowNXfZyppIAiZ FZiJpDLqukFDohpKCosas6TSGGK2jyaEGcLNKTWqTYPIeLWvNMirdOnZboEcjqBsuLyY ilGeOL8pP9LS+Blb7ClnjzEJ8OULdBtN7tQTiCcttd4iSX2FnOCqh5K8aj7jxKmU3pkT UUacUqhM/Mk4kDOfHU03yp8Ee0aUadPfW1w5rdq0b9xFcbE7lcV08JK+Vz0C/7eIXFed zcqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F6SPcQ3rOU1M+d5rn+hxpcarF5MAsSjTj9sicv1mJgY=; b=TF5roAxkZhMymdx7ZTBPgudNTsZjWt3Z8wYSvAiTsoD8ePsuK1KPzIv++10xHG9ztc XVXUnBkdxmA4zhx0tllpWsIojgOmKJY/aJAqnLbHe3Vfza2H39Bn6SB0+SdLI8T7T8MN ueSlVQ5vxNA7f+3W16//YB0kz8H54va31L3kEdRZYWlBOhqR08yOhxWvg8DgfvrAaH9P CcXD6OLHG3KAWcJZ+nCg59FWCKj/Zcd1Z6gP4X1CvdHpOzCfjG2lurB1cuz47xjUZi1V BriBQKFAUgsGf3JdsaxPqUju9TkLQVu1j3FZLOCp6kDktq2dtpoCxo+cPRy1f2454Vbb 1VoA== X-Gm-Message-State: AOAM5303wYzxKGoK8Me0DxF+BfV0HR9lmmZzOrM+p7r6CcQxOOpkTDnJ nJadaki1WVtkd+3rJINBk752Sg== X-Received: by 2002:a19:ef02:: with SMTP id n2mr2206276lfh.141.1616599171146; Wed, 24 Mar 2021 08:19:31 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:30 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 18/28] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers Date: Wed, 24 Mar 2021 18:18:36 +0300 Message-Id: <20210324151846.2774204-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" These drivers do not use vco_delay variable, so drop it from all of them. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- 3 files changed, 10 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index e0df12a841b2..bfb96d87d1d7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -99,7 +99,6 @@ struct dsi_pll_10nm { /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll = &pll_10nm->base; pll->cfg = phy->cfg; - pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 7fe7c8348b42..434d02ffa7fe 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -122,8 +122,6 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; - int vco_delay; - struct dsi_pll_input in; struct dsi_pll_output out; @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll = &pll_14nm->base; pll->cfg = phy->cfg; - pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index e6c8040e1bd3..f760904efac9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -99,7 +99,6 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->cfg = phy->cfg; - pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); From patchwork Wed Mar 24 15:18:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407878 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502274jai; Wed, 24 Mar 2021 08:19:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxnzn3SPhKk2A5u4h8wc6Ve/Tw+NX7oH13ivUzyG1iAfvSUZnuD9bqrURsDm6DX1KihAHqz X-Received: by 2002:a17:90b:1213:: with SMTP id gl19mr3951662pjb.55.1616599192515; Wed, 24 Mar 2021 08:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599192; cv=none; d=google.com; s=arc-20160816; b=jHAX+PPmWufRrDtldD4zTHjSQyz0XeLJ0fBO+x7rGZ1T36q4fbqKo5TIc0/mOliknz SXrJObX/e73gj6mY7sIoB6P1g+YU++tAzNTxPYzrr3znzIiTpNGvHFyFQGxskVXFyM9W 3nKhcaHgP/bmZWyLp5H8O4XvCHVeD4ObX/xLNcLbKW5L2xnAhm+D0fZRg66MbJbAXB9z oQVvH1XwuN4B+opiZjydgT0srBKQUoyd1e4wrjnArhzSBbCTcV+GZVYqX7sK8yM27eB+ Z896czqV2jzrFtYFzuqVZPCfhutWbJhNmi3lHe4BPefEJmh0QHcLQ62UxOL0a3HiLikf CUwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=9ZMHBfFyf4QR2ydfjlI74TSe1K+0+7WzI2lfAk3Qd+A=; b=d1wceS72BNnbGI1pEQoCcCFcGG4DDe3UzTABmdpAj+W+Swf0bTHdVRdLnXMuF9Fe9B c2+jvi9y9zJSVvYfiasKJk/C/Ug31PKLSOCbZcHS5pJFPLbs9iEcZz0ozryRCd8ovLJz M3os63Ngp1PdI1gdp2vsxQWN4KE0UcsN5irUIyYYtlsd2l0xcHJMC6PX8lLPqRuJS7kQ KqCvMVbRw+iU3bjUctDqgDAI8ILc4f+aI1z7828sThuB/lgktFTd890HmYzribl+/lcU sNTn5klSKKKhB2x1reCLWOWDElaZsyeCfnU9NnRHwaEtgqXRc7ed6WU1KL3w8U9Pd4X7 fKNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=znoqwLJm; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id z18si2452266plb.188.2021.03.24.08.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=znoqwLJm; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C7BB6EC93; Wed, 24 Mar 2021 15:19:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by gabe.freedesktop.org (Postfix) with ESMTPS id B723A6EC91 for ; Wed, 24 Mar 2021 15:19:33 +0000 (UTC) Received: by mail-lf1-x12d.google.com with SMTP id b14so19285302lfv.8 for ; Wed, 24 Mar 2021 08:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RFHW0LdlrmaF7YDk0vokBt8XF/nut54+Ls9k+Au93LE=; b=znoqwLJm7izb5lBmvfQwSvrc7kAZkwlBIOkIwe1r2FpSKUwHYcNd2RvOtQBv6rjHes idvTjUKowrFuKSzrhG6PTGe55Ftzt/KlSBbbsAYEhSNYfYL7DuGeV3Co1ak+2rlZtuGq u/53FicoWS8BniYtKaiPTNj1qvuO2hjzj5iNJVqxelDgGT7KwWMZWAP9biyyWEkjPYl1 XsCOz0nQfNaBe3oN0/wI5tYgkyu/k0RO+07V4WOT3Dpa79QLxUG2cNuPIMpBSSfljBdQ 7/doPKIxu+z//vNI/5vVkaYIi5RmBhggCZzSscdDEJ6pv3SXyHuxko/n4wuKffA2fePS t/iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RFHW0LdlrmaF7YDk0vokBt8XF/nut54+Ls9k+Au93LE=; b=FebGKTdixqpRhScBCYKvIU6mwHJ2Qcy7H/hGYe54fPKEtdQBxXwf81VnJL7i0tdGOV ZWRBRolhnmlk1242r2Ho+j5do0G/S0cyoO+spJTWku8D+1v54CHkWmqDN/Bt3kMp3v5C ZXyWC5sDf16q7PeKI5XmKreOlYtDw9pLFfrv21ekEh4I92azoej/col5DNjXXtRPDASm ZKlGWYiVenCBOr1st9P8RNU3QdX1PSeRU6DJGxVK8mBaXUw1FLwFbNYHKzm8ufaDK0Fd g8+8o1N5O1+k1x9Xcrs0MchEAtsLO9G8Kb0fGSMZ0kDljSRtY4pN14C9QdbcRuu5qOlS xspg== X-Gm-Message-State: AOAM533cfjaPRMkzguWkCpDAm6cm4DybFTAmJqGC+vMgzds6IpxBg7NK i9aAlAB8EgvFs8nhJ99syUJeqvQfvGho3w== X-Received: by 2002:ac2:5146:: with SMTP id q6mr2347257lfd.441.1616599172213; Wed, 24 Mar 2021 08:19:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:31 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 19/28] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver Date: Wed, 24 Mar 2021 18:18:37 +0300 Message-Id: <20210324151846.2774204-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Instead of setting the variable and then using it just in the one place, determine vco_delay directly at the PLL configuration time. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 3e9b7949b038..87d1aa4114e4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -72,8 +72,6 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; - int vco_delay; - struct pll_28nm_cached_state cached_state; }; @@ -212,8 +210,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); /* Add hardware recommended delay for correct PLL configuration */ - if (pll_28nm->vco_delay) - udelay(pll_28nm->vco_delay); + if (pll->cfg->type == MSM_DSI_PHY_28NM_HPM) + udelay(1); + else /* LP */ + udelay(1000); pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); @@ -580,10 +580,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) pll = &pll_28nm->base; pll->cfg = phy->cfg; - if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) - pll_28nm->vco_delay = 1000; - else - pll_28nm->vco_delay = 1; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { From patchwork Wed Mar 24 15:18:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407876 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502229jai; Wed, 24 Mar 2021 08:19:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyen1jicPYpLApG+VTjvxDumr8/0x4+8qDLhXVRxJMWMHsGvKuNB1NbxxXOnwhVjcbhL+pl X-Received: by 2002:a17:90a:4290:: with SMTP id p16mr4028690pjg.120.1616599188453; Wed, 24 Mar 2021 08:19:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599188; cv=none; d=google.com; s=arc-20160816; b=vC0QBDBFS9p6m1fDAgQ2MB9hOV+ov0kq7Xyu6ksvDvH2/nDa7w6FtgVz36hiN6dxbZ PXPM5Z55O25ecHFWZ029LfhtAZI68oIeobPN+H46oWKss53j6S9ALIQFfAUVR11iYNzA odeWhrOZTSzbCs3qEhuFnP0/tXDskKdEMKZVpRkJ9maMSyUBn+EE/2Gg1J+C4vuJ3pdJ qxvoXAkE09WaVYyGYDmiPrxW3s0Hi8fohQJY0ZLHPeNHAf1b2bXXVlalLBJKrlWCKuOu l5Bwd7WVUG/njEVrLRGb6jUW4+Sho5ThlqcnJY5qjTngY1e/GbVz39arqo82+S0jHCpA tXnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=GHwWUu721/UNUSPAeZl/57RdH6FRIbr4t5jnDdmSgns=; b=hwy2+ATgLDUT2AUYYXq2U0JOtmDuSyOv9QP86Ctu/YW+iTXs4LJ7Jcr87mTNhNhrHR LMBf/zt+HeuRIHjJ+UeYXj/RYoobRewg1Nhd3ITXhrhbX615DxcrMZLxqv5K+Rb76UuA Oe5Wv9UpdorKvWTYRJjQ2kkb/F9m8H651tcD32OzDHXOZ0NZB8lav5Jv98NJU3zYYhT0 sK6kTHQ+/lBqF68qlSSZklCTRY827bjwVNmQOpa1ImwWTdrpK7Q8xxGsnJXpbAOgWWHH QCNusHx+F0RGL8vjRhzf0WmG0QrxdDXqhysmP6Z3gK6DQaEjtFyaBpTZXGW3yEpw8TEj /oeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d8sJpXgw; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id s4si2416109plr.175.2021.03.24.08.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d8sJpXgw; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 09B4E6EC94; Wed, 24 Mar 2021 15:19:38 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by gabe.freedesktop.org (Postfix) with ESMTPS id D74756EC87 for ; Wed, 24 Mar 2021 15:19:34 +0000 (UTC) Received: by mail-lf1-x130.google.com with SMTP id b4so8596562lfi.6 for ; Wed, 24 Mar 2021 08:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2p4oL96Pew8x1y5rAyDAueBp+j2sBp7UMdeXoZ4vvl4=; b=d8sJpXgwe9DJ1tCXbTxqlGFJRNc/qZ8qcDgD38y5+D2CHrlV8nYcAzHhTkMXRPLWnI sN+XyUgluLaV0X0FUMjy2CU8nPwS8Z2SMDp7KpnDo5NrSCTg5RLec4O3NUMlKakOv6bR +KJdmNUSfu9BepDgLzfipBVz+2kif1B4doJiaIhfY/+CGVoJNW2WqdS2Kd59NqrCbWNC 51AopBb/vHgz4A5jJ1lBXYfUP+YsQ04d/0roOwQciclyIvM0NLyn/IYA3gnvSkVoAlxj PeS+fpeC3/NbuYmXwkpU1hOuebg8SfY9mva3mXXNQ7rmHzwBWAAixfxtn3TS4rXfWiZs s5TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2p4oL96Pew8x1y5rAyDAueBp+j2sBp7UMdeXoZ4vvl4=; b=Q32NUrz2nGvW6TqIbyHeMSf5vLG4zYUOp5+JnWlHFM2j5miKmek0D5H/FSzN8ibX1J UYfETO842OzUU1vFrJspZLHjuEC7y/LJUjizCUT1Cxm9Irl9lZ2cDWpVN3hpmNA9Dcl1 /xf21c4YKt1kCR6zO4S0mJMH2R6Jfi+5fSRZH4s3gWsv6Jj+1X6NvvBv+Tx3x0yAr1mn NHza9e1N+ffOKUCZ6FlEcXAcSYhmp8I6WT+XZQiCyn2ndW+lM8jMXsR3rL+2pxNqATck Z0iY2SuS++LOzdk4hdbuUaB0pGSAU2n9i5aMeGGMeeDQdtHiNjSPHYc8jRjPVt6RNm14 592A== X-Gm-Message-State: AOAM53249L2O5xt9+dsQpYbHqwwCjgGGnbGJRERF5wdr/MrvbIvkoxJv w6d0NTH/DT7hE6eknzHlQoORpA== X-Received: by 2002:ac2:4857:: with SMTP id 23mr2286025lfy.136.1616599173229; Wed, 24 Mar 2021 08:19:33 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:32 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 20/28] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Date: Wed, 24 Mar 2021 18:18:38 +0300 Message-Id: <20210324151846.2774204-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 10nm and 7nm already do not use these helpers, as they handle setting slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to remove unnecessary indirection and drop enable_seq/disable_seq PLL callbacks. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 87 +++++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 86 ++++++++----- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 120 ++++++++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 35 ----- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 2 - 6 files changed, 171 insertions(+), 161 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8133732e0c7f..b477d21804c8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -32,8 +32,6 @@ struct msm_dsi_phy_ops { }; struct msm_dsi_pll_ops { - int (*enable_seq)(struct msm_dsi_pll *pll); - void (*disable_seq)(struct msm_dsi_pll *pll); void (*save_state)(struct msm_dsi_pll *pll); int (*restore_state)(struct msm_dsi_pll *pll); }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 434d02ffa7fe..91c5bb2fd169 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -652,12 +652,58 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, return (unsigned long)vco_rate; } +static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *base = pll_14nm->mmio; + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + bool locked; + + DBG(""); + + if (unlikely(pll->pll_on)) + return 0; + + pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); + + locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, + POLL_TIMEOUT_US); + + if (unlikely(!locked)) { + DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); + return -EINVAL; + } + + DBG("DSI PLL lock success"); + pll->pll_on = true; + + return 0; +} + +static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + + DBG(""); + + if (unlikely(!pll->pll_on)) + return; + + pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + + pll->pll_on = false; +} + static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { .round_rate = msm_dsi_pll_helper_clk_round_rate, .set_rate = dsi_pll_14nm_vco_set_rate, .recalc_rate = dsi_pll_14nm_vco_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, + .prepare = dsi_pll_14nm_vco_prepare, + .unprepare = dsi_pll_14nm_vco_unprepare, }; /* @@ -749,39 +795,6 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { * PLL Callbacks */ -static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *base = pll_14nm->mmio; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - bool locked; - - DBG(""); - - pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); - - locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, - POLL_TIMEOUT_US); - - if (unlikely(!locked)) - DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); - - return locked ? 0 : -EINVAL; -} - -static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; - - DBG(""); - - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); -} - static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); @@ -1157,8 +1170,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .pll_ops = { .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, - .disable_seq = dsi_pll_14nm_disable_seq, - .enable_seq = dsi_pll_14nm_enable_seq, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -1183,8 +1194,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .pll_ops = { .save_state = dsi_pll_14nm_save_state, .restore_state = dsi_pll_14nm_restore_state, - .disable_seq = dsi_pll_14nm_disable_seq, - .enable_seq = dsi_pll_14nm_enable_seq, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 87d1aa4114e4..53e225934f9e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -289,19 +289,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, return vco_rate; } -static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, - .set_rate = dsi_pll_28nm_clk_set_rate, - .recalc_rate = dsi_pll_28nm_clk_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, - .is_enabled = dsi_pll_28nm_clk_is_enabled, -}; - -/* - * PLL Callbacks - */ -static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; @@ -376,21 +364,28 @@ static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) return locked ? 0 : -EINVAL; } -static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) { + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); int i, ret; + if (unlikely(pll->pll_on)) + return 0; + for (i = 0; i < 3; i++) { - ret = _dsi_pll_28nm_enable_seq_hpm(pll); - if (!ret) + ret = _dsi_pll_28nm_vco_prepare_hpm(pll); + if (!ret) { + pll->pll_on = true; return 0; + } } return ret; } -static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) +static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; @@ -400,6 +395,9 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) DBG("id=%d", pll_28nm->id); + if (unlikely(pll->pll_on)) + return 0; + pll_28nm_software_reset(pll_28nm); /* @@ -424,22 +422,54 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); - if (unlikely(!locked)) + if (unlikely(!locked)) { DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); + return -EINVAL; + } - return locked ? 0 : -EINVAL; + DBG("DSI PLL lock success"); + pll->pll_on = true; + + return 0; } -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) +static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); DBG("id=%d", pll_28nm->id); + + if (unlikely(!pll->pll_on)) + return; + pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); + + pll->pll_on = false; } +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_hpm, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_lp, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + +/* + * PLL Callbacks + */ + static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); @@ -490,7 +520,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, - .ops = &clk_ops_dsi_pll_28nm_vco, }; struct device *dev = &pll_28nm->pdev->dev; struct clk_hw *hw; @@ -498,6 +527,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov DBG("%d", pll_28nm->id); + if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP) + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; + else + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm->base.clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw); @@ -753,8 +787,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .pll_ops = { .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, - .disable_seq = dsi_pll_28nm_disable_seq, - .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -779,8 +811,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .pll_ops = { .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, - .disable_seq = dsi_pll_28nm_disable_seq, - .enable_seq = dsi_pll_28nm_enable_seq_hpm, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -805,8 +835,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .pll_ops = { .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, - .disable_seq = dsi_pll_28nm_disable_seq, - .enable_seq = dsi_pll_28nm_enable_seq_lp, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 45b2bf482392..952444e3e8f0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -178,12 +178,76 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, return vco_rate; } +static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + bool locked; + unsigned int bit_div, byte_div; + int max_reads = 1000, timeout_us = 100; + u32 val; + + DBG("id=%d", pll_28nm->id); + + if (unlikely(pll->pll_on)) + return 0; + + /* + * before enabling the PLL, configure the bit clock divider since we + * don't expose it as a clock to the outside world + * 1: read back the byte clock divider that should already be set + * 2: divide by 8 to get bit clock divider + * 3: write it to POSTDIV1 + */ + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + byte_div = val + 1; + bit_div = byte_div / 8; + + val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val &= ~0xf; + val |= (bit_div - 1); + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); + + /* enable the PLL */ + pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, + DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); + + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); + + if (unlikely(!locked)) { + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + return -EINVAL; + } + + DBG("DSI PLL lock success"); + pll->pll_on = true; + + return 0; +} + +static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + DBG("id=%d", pll_28nm->id); + + if (unlikely(!pll->pll_on)) + return; + + pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); + + pll->pll_on = false; +} + static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { .round_rate = msm_dsi_pll_helper_clk_round_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, - .prepare = msm_dsi_pll_helper_clk_prepare, - .unprepare = msm_dsi_pll_helper_clk_unprepare, + .prepare = dsi_pll_28nm_vco_prepare, + .unprepare = dsi_pll_28nm_vco_unprepare, .is_enabled = dsi_pll_28nm_clk_is_enabled, }; @@ -270,56 +334,6 @@ static const struct clk_ops clk_bytediv_ops = { /* * PLL Callbacks */ -static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; - bool locked; - unsigned int bit_div, byte_div; - int max_reads = 1000, timeout_us = 100; - u32 val; - - DBG("id=%d", pll_28nm->id); - - /* - * before enabling the PLL, configure the bit clock divider since we - * don't expose it as a clock to the outside world - * 1: read back the byte clock divider that should already be set - * 2: divide by 8 to get bit clock divider - * 3: write it to POSTDIV1 - */ - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); - byte_div = val + 1; - bit_div = byte_div / 8; - - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - val &= ~0xf; - val |= (bit_div - 1); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); - - /* enable the PLL */ - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, - DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); - - locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); - - if (unlikely(!locked)) - DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); - else - DBG("DSI PLL lock success"); - - return locked ? 0 : -EINVAL; -} - -static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - DBG("id=%d", pll_28nm->id); - pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); -} - static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); @@ -652,8 +666,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .pll_ops = { .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, - .disable_seq = dsi_pll_28nm_disable_seq, - .enable_seq = dsi_pll_28nm_enable_seq, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c index 652c2d6bfeec..cae668b669a4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c @@ -21,38 +21,3 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, else return rate; } - -int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - int ret = 0; - - /* - * Certain PLLs do not allow VCO rate update when it is on. - * Keep track of their status to turn on/off after set rate success. - */ - if (unlikely(pll->pll_on)) - return 0; - - ret = pll->cfg->pll_ops.enable_seq(pll); - if (ret) { - DRM_ERROR("DSI PLL failed to lock\n"); - return ret; - } - - pll->pll_on = true; - - return 0; -} - -void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - - if (unlikely(!pll->pll_on)) - return; - - pll->cfg->pll_ops.disable_seq(pll); - - pll->pll_on = false; -} diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h index eca13cf67c21..da83e4c11f4f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h @@ -39,8 +39,6 @@ static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) /* clock callbacks */ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); -int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw); -void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw); #endif /* __DSI_PLL_H__ */ From patchwork Wed Mar 24 15:18:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407881 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502380jai; Wed, 24 Mar 2021 08:19:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyeVNSJybGg0si/Q5FlFOl9YAZb4RQzuJ2Y/sAsodU3SyeRxK9eObYU5xZxq9aZN0R8R7Bq X-Received: by 2002:a65:4c01:: with SMTP id u1mr3553242pgq.182.1616599199010; Wed, 24 Mar 2021 08:19:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599199; cv=none; d=google.com; s=arc-20160816; b=E5WtNeFmxIsxUXdTWv+lobDrGl5uM46guYg5YTq73QtY9Te5rzSKwmdEOlXWa0jXYQ MT2yDj0LeWR6xHFzzZS9j1VvYsYg8uzgSoZXY6f5Rcb79Fri51ealzltjGPu46vAKQEb uW5yGLFip65gu2mK6nDX+zNYU8VOm41dy/yOTs5B/vmcJnLbyoKK91iiQKolsF1joJeO fuA/D2xGdS/Q9yzCuscF13er4sxcg7CIMQtT43Gf+hfaEpzNyakPgbs/twizwYTgXqCQ pP+3cn7guSdCtGAvyqlJy3jC5+6HwAT2+E90n8GXVeqBFn3Pt7DiKNFK1YbuNkylR6qL 4Uzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=OYxzUf+aYirn4vIKC3v0BNHSqs7HwzZtzgzCq41B8Lg=; b=hi9uOSenTWRHVvLIak8fQ/btILs+6MeTTgrq/iDiuApuyYS/nWJkeAiTXSBWP0DPgY WAPHYamXvPKvgQT4Zv1zuPNuJA5DFn65gyoVZ+s76WtcbGCabTohqgttxtVx61QnxiBM Tc/Kz4GHp2AJfVX38oZy/P2nwpEw0hhzU1mzxC7UhWw+ZlwnuraImZjI8YBTm8orRpa0 aNimYC6xGVxzTXdgQCICjItIQIAG/7z+O2XFVPcjKZwdPep4hiFTNZHWcz3shJkLJrnt qMOhdcY63LgWatu0poRCspzYgy4Fv+gmgvmQRAOIztP7VCxuPAh61uREqhho2ygiU2Rd 4Qyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EJ8OEbNm; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id x1si3226739pgj.577.2021.03.24.08.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EJ8OEbNm; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 096606EC9B; Wed, 24 Mar 2021 15:19:44 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by gabe.freedesktop.org (Postfix) with ESMTPS id E9DB86EC87 for ; Wed, 24 Mar 2021 15:19:35 +0000 (UTC) Received: by mail-lf1-x131.google.com with SMTP id b83so32538717lfd.11 for ; Wed, 24 Mar 2021 08:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TnOxSzkdxiuIpKQMEb6cCKF5K0F2bZFPRE7TYCJUc74=; b=EJ8OEbNmWq3MGjyS1aJnimXvYmKNWg26ETAnMe21aJ3SIGzN4+ovH2E6xN9fpUXvfa US32uD+IJn/Run2U9s1wW2r4AR7geT20ujhrUNFF0dll6e0dEotSOIS9tNJAfw3MPYyR 3bOW2CEoXctsK1xsPF7UrTqwfSQgpa6IEwsyHZmbtwANIUIzzhAzdT4tsSfaAYK5io3h ujOwtsU91Ty2R+4HaHR9TBlvndNzytafHlYn9t9GXVVYL6qR6a9s+MokdudJPyYHd3gp uRxdQe3JYDJKou6H90ojFmil6x27H5sMEBYvnVB1os9ZA2Gw14glowEwbgiZvzyTZ2o7 ec7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TnOxSzkdxiuIpKQMEb6cCKF5K0F2bZFPRE7TYCJUc74=; b=Wd6CoRybLcYOomTtZm81vlRAvgs+v8EufdwsKTBS7OAMtzpRpue/cjIsH01f7N1y5U HJc2qiE9koR6GSduX8mR1Ac5Ap6uyBAkackTpkE85PRGDIcghVjeQwtNzR/ktmmyh8BW uyRjwugcZpGtHVAIoVDsULVWILJtbl4GLsRq2QyaNF5vm5nRLvJWFnqaS3HaCJk2O3Co iO3XE+5NiCpsbg7lUiB9KGZKSIKGGO0SPq4pwp9Zx1pp6BqJfva8ir4wkmTwZ0GxFTMT i0rjsOqZuny94Wm0LVDsF+r311HBpgUa6otnicYkP26kvHVpJ6wYqwgJBoztw7IFCtLy mGfw== X-Gm-Message-State: AOAM530ibFjFgKfRaXkzzZhi6d7N/LTa24/u+E0OZ5bXNsFjO+ergCV4 2UgjyBu2wo2jBnNb6k7xWy+HAw== X-Received: by 2002:a05:6512:ac9:: with SMTP id n9mr2267502lfu.186.1616599174291; Wed, 24 Mar 2021 08:19:34 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:33 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 21/28] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Date: Wed, 24 Mar 2021 18:18:39 +0300 Message-Id: <20210324151846.2774204-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Make save_state/restore callbacks accept struct msm_dsi_phy rather than struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing us to drop struct msm_dsi_pll_ops. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 12 +++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 11 +++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 22 ++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 24 ++++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 32 ++++++++----------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 18 +++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 22 ++++++------- 7 files changed, 59 insertions(+), 82 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 7d23371a83f6..1a49cb2d1184 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -847,9 +847,9 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, void msm_dsi_phy_save_state(struct msm_dsi_phy *phy) { - if (phy->cfg->pll_ops.save_state) { - phy->cfg->pll_ops.save_state(phy->pll); - phy->pll->state_saved = true; + if (phy->cfg->ops.save_state) { + phy->cfg->ops.save_state(phy); + phy->state_saved = true; } } @@ -857,12 +857,12 @@ int msm_dsi_phy_restore_state(struct msm_dsi_phy *phy) { int ret; - if (phy->cfg->pll_ops.restore_state && phy->pll->state_saved) { - ret = phy->cfg->pll_ops.restore_state(phy->pll); + if (phy->cfg->ops.restore_state && phy->state_saved) { + ret = phy->cfg->ops.restore_state(phy); if (ret) return ret; - phy->pll->state_saved = false; + phy->state_saved = false; } return 0; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index b477d21804c8..fa09f4c2c071 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -17,7 +17,6 @@ struct msm_dsi_pll { struct clk_hw clk_hw; bool pll_on; - bool state_saved; const struct msm_dsi_phy_cfg *cfg; }; @@ -29,17 +28,13 @@ struct msm_dsi_phy_ops { int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, struct msm_dsi_phy_clk_request *clk_req); void (*disable)(struct msm_dsi_phy *phy); -}; - -struct msm_dsi_pll_ops { - void (*save_state)(struct msm_dsi_pll *pll); - int (*restore_state)(struct msm_dsi_pll *pll); + void (*save_state)(struct msm_dsi_phy *phy); + int (*restore_state)(struct msm_dsi_phy *phy); }; struct msm_dsi_phy_cfg { struct dsi_reg_config reg_cfg; struct msm_dsi_phy_ops ops; - const struct msm_dsi_pll_ops pll_ops; unsigned long min_pll_rate; unsigned long max_pll_rate; @@ -115,6 +110,8 @@ struct msm_dsi_phy { struct msm_dsi_pll *pll; struct clk_hw_onecell_data *provided_clocks; + + bool state_saved; }; /* diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index bfb96d87d1d7..25fd4d860c4d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -518,9 +518,9 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { * PLL Callbacks */ -static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) +static void dsi_10nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; void __iomem *phy_base = pll_10nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; @@ -541,9 +541,9 @@ static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) cached->pix_clk_div, cached->pll_mux); } -static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) +static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; void __iomem *phy_base = pll_10nm->phy_cmn_mmio; u32 val; @@ -562,7 +562,7 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) val |= cached->pll_mux; pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); + ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); if (ret) { DRM_DEV_ERROR(&pll_10nm->pdev->dev, "restore vco rate failed. ret=%d\n", ret); @@ -1005,10 +1005,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_10nm_save_state, - .restore_state = dsi_pll_10nm_restore_state, + .save_state = dsi_10nm_save_state, + .restore_state = dsi_10nm_restore_state, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, @@ -1029,10 +1027,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_10nm_save_state, - .restore_state = dsi_pll_10nm_restore_state, + .save_state = dsi_10nm_save_state, + .restore_state = dsi_10nm_restore_state, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 91c5bb2fd169..c7c462bfe96d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -795,9 +795,9 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { * PLL Callbacks */ -static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) +static void dsi_14nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; u32 data; @@ -810,18 +810,18 @@ static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) DBG("DSI%d PLL save state %x %x", pll_14nm->id, cached_state->n1postdiv, cached_state->n2postdiv); - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); } -static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) +static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; u32 data; int ret; - ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, + ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_14nm->pdev->dev, @@ -1166,10 +1166,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, .pll_init = dsi_pll_14nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_14nm_save_state, - .restore_state = dsi_pll_14nm_restore_state, + .save_state = dsi_14nm_save_state, + .restore_state = dsi_14nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -1190,10 +1188,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, .pll_init = dsi_pll_14nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_14nm_save_state, - .restore_state = dsi_pll_14nm_restore_state, + .save_state = dsi_14nm_save_state, + .restore_state = dsi_14nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 53e225934f9e..8f10dbb0c136 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -470,9 +470,9 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { * PLL Callbacks */ -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) +static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; @@ -481,20 +481,20 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) cached_state->postdiv1 = pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); - if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw)) - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); + if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw)) + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); else cached_state->vco_rate = 0; } -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) +static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; int ret; - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_28nm->pdev->dev, @@ -783,10 +783,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_28nm_save_state, - .restore_state = dsi_pll_28nm_restore_state, + .save_state = dsi_28nm_save_state, + .restore_state = dsi_28nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -807,10 +805,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_28nm_save_state, - .restore_state = dsi_pll_28nm_restore_state, + .save_state = dsi_28nm_save_state, + .restore_state = dsi_28nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, @@ -831,10 +827,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_28nm_save_state, - .restore_state = dsi_pll_28nm_restore_state, + .save_state = dsi_28nm_save_state, + .restore_state = dsi_28nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 952444e3e8f0..c71c5f07666d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -334,9 +334,9 @@ static const struct clk_ops clk_bytediv_ops = { /* * PLL Callbacks */ -static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) +static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; @@ -347,17 +347,17 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) cached_state->postdiv1 = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); + cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); } -static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) +static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; int ret; - ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, + ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_28nm->pdev->dev, @@ -662,10 +662,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_8960_init, - }, - .pll_ops = { - .save_state = dsi_pll_28nm_save_state, - .restore_state = dsi_pll_28nm_restore_state, + .save_state = dsi_28nm_save_state, + .restore_state = dsi_28nm_restore_state, }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index f760904efac9..015e099d7b7f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -543,9 +543,9 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { * PLL Callbacks */ -static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) +static void dsi_7nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; @@ -566,9 +566,9 @@ static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) cached->pix_clk_div, cached->pll_mux); } -static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) +static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 val; @@ -587,7 +587,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) val |= cached->pll_mux; pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); + ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); if (ret) { DRM_DEV_ERROR(&pll_7nm->pdev->dev, "restore vco rate failed. ret=%d\n", ret); @@ -1038,10 +1038,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_7nm_save_state, - .restore_state = dsi_pll_7nm_restore_state, + .save_state = dsi_7nm_save_state, + .restore_state = dsi_7nm_restore_state, }, .min_pll_rate = 600000000UL, .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, @@ -1063,10 +1061,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init, - }, - .pll_ops = { - .save_state = dsi_pll_7nm_save_state, - .restore_state = dsi_pll_7nm_restore_state, + .save_state = dsi_7nm_save_state, + .restore_state = dsi_7nm_restore_state, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, From patchwork Wed Mar 24 15:18:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407882 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502415jai; Wed, 24 Mar 2021 08:20:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4gaW1SyH/OgxVEGmiEfP7a2uIKUSIoQ4JHC55HOIwU3593523SKtfqOIqDrF/ULJq0AtR X-Received: by 2002:a17:90b:2304:: with SMTP id mt4mr4156026pjb.179.1616599200835; Wed, 24 Mar 2021 08:20:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599200; cv=none; d=google.com; s=arc-20160816; b=sEa8xcVQCI10sYrD6kvWwDHrb8710s9ULeWo0+EzwO9DuaR6qGISQ5O6GdGHHMv7iH dRpsNE+jT9xOrROny/vzjzNuMr56ISyweJCdC9hShr+su/VnlHrewgn/nc2XftC9Vr1Q 0poTus9bybOntHH5loQgsUOiq3XfIh24RFSHxcQItEmBhzAzFz4151TIV4pj5kA+TS8o aus1PHjfIsQh0x/JR9bV0Y3Z3XP4oV+t9whvmBjgnv7ITVWFEGptR/83AWWndNwpTZpD 3oRLFX6VJO6JKuZ/N8qxG3XF6WG2zZwSh0/EkRAIag2qjXPgb9t93KvEhFj0QxqdsUtV g2Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=Zf0/yELinXCsaMZC0o2dUYIYF1mkFmYY73n183QQgek=; b=vby0T0X3WJhppPDD2NaP/j3uMxZd8gkHkUFH3B3bPe/eOb5tbGQ790H9LlIZ52WVVP 3HYINlIYuCIvmbefbX1b2Y/Uan5zlip+yj5CX6Ip44e62JAQ0/gWO4LUsZO6iXLP4TNj pHSjSnnDzhO1aoK56Wc6cSDs8RSk/LdE4WtMQtPHCE6Lt2CCREQnF71/F2w8OmUKyyfU oHHvnDwi3LLFrK4FkAv1cB35sJ5sNQgzjQ6X/kT8h1OAhhQmIKS7irH/36CNk8gVdlKm lVBNS1A0nYFV8YxqiLHREwWhz5vjIwutl8pPch9iTdotbDRvX238Uh/j6/Ts2W6NItp8 nX/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eweLyVhY; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id r22si2358262pjp.103.2021.03.24.08.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eweLyVhY; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0C006EC6F; Wed, 24 Mar 2021 15:19:50 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id 997156EC92 for ; Wed, 24 Mar 2021 15:19:37 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id m12so32536705lfq.10 for ; Wed, 24 Mar 2021 08:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k24C4+aWUoKRx+aU6GfF11558YiatAqqYy1JaAujDmE=; b=eweLyVhYDeI3QowY5MA2oL3bTdWsnubT4/SMLXoziGGOXaGMOTmdt+4moVf0tgAf8V nsuiDK0Ej0L1xkINtSF5gAhWOEWjuq7061QPAoBC1sYapyJLZ+881AcG6UzW6FgSEMdf FctnlR8rY97ehCAgeTIwShVS8wpUvy7ovpNgkeXn6rtJHTeSgu8Kgp7EgSeOz1/N95r0 Kooa5Ej9xsJTXhpCHnxj3MeN7A+PY/+DIExOD//7lAyDzomDWQL0l/rNBOk/K6pFVLTl XY08SGdQVGrEmGtFDo1ZX3b2f38YoV8vNsCTRPXUWkNQmNTuD9n6KoLedbULva+2Dvuq 7DzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k24C4+aWUoKRx+aU6GfF11558YiatAqqYy1JaAujDmE=; b=oUc61Fe8nIdEWhXGNmppBJuW6GLmD71Eln9f9O4jeHr1NKsICSKkr+5XsozvlGw3d6 oHp6wUa1QYe7oTb3EOklBE6RK68z8ZGJqoJ7gSuf7QbdWMm6fxsD1+dn/XjoX3ikG9/f Fq4ChGZtniIHm+yRU/NazDj/3YE9GodmPvVNy9qwl12TyP4vO8+xQpCsXSoT5aMYZdLC 8t5f+dGIaqrj9GooyfDfiK1aIJKHQkJjZWDf78YB0rPUUmGmuD88/hVB0Mczv8F4ktyp 6tRdSyZ3jxuULvu0DomaRQ4pswrYhVbnHKNy9ODBSkRkkpfn6XBAAiFESBJ1aNV9hOiC htnA== X-Gm-Message-State: AOAM531TyAkhFENSDSbDDuUUWnXXCyGqo4pHu52UU9NPsUFZHwvOtHL3 ZTkzUQGSCL4REHhwZKcX3C/Scw== X-Received: by 2002:a05:6512:3e20:: with SMTP id i32mr2295434lfv.257.1616599175629; Wed, 24 Mar 2021 08:19:35 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:34 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 22/28] drm/msm/dsi: drop msm_dsi_pll abstracton Date: Wed, 24 Mar 2021 18:18:40 +0300 Message-Id: <20210324151846.2774204-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw directly into struct msm_dsi_phy. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 8 -- drivers/gpu/drm/msm/Makefile | 2 - drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 36 +++++--- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 66 ++++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 78 ++++++++--------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 83 ++++++++++--------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 65 ++++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 74 +++++++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 23 ----- drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 44 ---------- 10 files changed, 221 insertions(+), 258 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.c delete mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_pll.h -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index dabb4a1ccdcf..1f0b3f0e7149 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -76,14 +76,6 @@ config DRM_MSM_DSI Choose this option if you have a need for MIPI DSI connector support. -config DRM_MSM_DSI_PLL - bool "Enable DSI PLL driver in MSM DRM" - depends on DRM_MSM_DSI && COMMON_CLK - default y - help - Choose this option to enable DSI PLL driver which provides DSI - source clocks under common clock framework. - config DRM_MSM_DSI_28NM_PHY bool "Enable DSI 28nm PHY driver in MSM DRM" depends on DRM_MSM_DSI diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 1be6996b80b7..610d630326bb 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -136,6 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o -msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o - obj-$(CONFIG_DRM_MSM) += msm.o diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index fa09f4c2c071..4fe410c97d3a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -7,6 +7,7 @@ #define __DSI_PHY_H__ #include +#include #include #include "dsi.h" @@ -14,15 +15,6 @@ #define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset)) -struct msm_dsi_pll { - struct clk_hw clk_hw; - bool pll_on; - - const struct msm_dsi_phy_cfg *cfg; -}; - -#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) - struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, @@ -107,7 +99,8 @@ struct msm_dsi_phy { enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; - struct msm_dsi_pll *pll; + struct clk_hw *vco_hw; + bool pll_on; struct clk_hw_onecell_data *provided_clocks; @@ -127,6 +120,27 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, u32 bit_mask); +/* PLL accessors */ +static inline void pll_write(void __iomem *reg, u32 data) +{ + msm_writel(data, reg); +} + +static inline u32 pll_read(const void __iomem *reg) +{ + return msm_readl(reg); +} + +static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) +{ + pll_write(reg, data); + udelay(delay_us); +} + +static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) +{ + pll_write((reg), data); + ndelay(delay_ns); +} #endif /* __DSI_PHY_H__ */ - diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 25fd4d860c4d..dec9beadddaa 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -7,7 +7,6 @@ #include #include -#include "dsi_pll.h" #include "dsi_phy.h" #include "dsi.xml.h" @@ -85,11 +84,13 @@ struct pll_10nm_cached_state { }; struct dsi_pll_10nm { - struct msm_dsi_pll base; + struct clk_hw clk_hw; int id; struct platform_device *pdev; + struct msm_dsi_phy *phy; + void __iomem *phy_cmn_mmio; void __iomem *mmio; @@ -104,11 +105,10 @@ struct dsi_pll_10nm { struct pll_10nm_cached_state cached_state; - enum msm_dsi_phy_usecase uc; struct dsi_pll_10nm *slave; }; -#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base) +#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw) /* * Global list of private DSI PLL struct pointers. We need this for Dual DSI @@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll) static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate, parent_rate); @@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); struct device *dev = &pll_10nm->pdev->dev; int rc; @@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) goto error; } - pll->pll_on = true; + pll_10nm->phy->pll_on = true; dsi_pll_enable_global_clk(pll_10nm); if (pll_10nm->slave) @@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); /* * To avoid any stray glitches while abruptly powering down the PLL @@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) } /* flush, ensure all register writes are done */ wmb(); - pll->pll_on = false; + pll_10nm->phy->pll_on = false; } static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); struct dsi_pll_config *config = &pll_10nm->pll_configuration; void __iomem *base = pll_10nm->mmio; u64 ref_clk = pll_10nm->vco_ref_clk_rate; @@ -506,8 +502,21 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, return (unsigned long)vco_rate; } +static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); + + if (rate < pll_10nm->phy->cfg->min_pll_rate) + return pll_10nm->phy->cfg->min_pll_rate; + else if (rate > pll_10nm->phy->cfg->max_pll_rate) + return pll_10nm->phy->cfg->max_pll_rate; + else + return rate; +} + static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_10nm_clk_round_rate, .set_rate = dsi_pll_10nm_vco_set_rate, .recalc_rate = dsi_pll_10nm_vco_recalc_rate, .prepare = dsi_pll_10nm_vco_prepare, @@ -520,7 +529,7 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { static void dsi_10nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; void __iomem *phy_base = pll_10nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; @@ -543,7 +552,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy) static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; void __iomem *phy_base = pll_10nm->phy_cmn_mmio; u32 val; @@ -562,7 +571,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) val |= cached->pll_mux; pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); if (ret) { DRM_DEV_ERROR(&pll_10nm->pdev->dev, "restore vco rate failed. ret=%d\n", ret); @@ -574,16 +583,15 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) return 0; } -static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) +static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) { - struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); void __iomem *base = pll_10nm->phy_cmn_mmio; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_10nm->id); - switch (uc) { + switch (phy->usecase) { case MSM_DSI_PHY_STANDALONE: break; case MSM_DSI_PHY_MASTER: @@ -599,8 +607,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, /* set PLL src */ pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); - pll_10nm->uc = uc; - return 0; } @@ -628,9 +634,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov DBG("DSI%d", pll_10nm->id); snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); - pll_10nm->base.clk_hw.init = &vco_init; + pll_10nm->clk_hw.init = &vco_init; - ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw); if (ret) return ret; @@ -740,7 +746,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) struct platform_device *pdev = phy->pdev; int id = phy->id; struct dsi_pll_10nm *pll_10nm; - struct msm_dsi_pll *pll; int ret; pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); @@ -767,8 +772,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_10nm->postdiv_lock); - pll = &pll_10nm->base; - pll->cfg = phy->cfg; + pll_10nm->phy = phy; ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); if (ret) { @@ -776,7 +780,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) return ret; } - phy->pll = pll; + phy->vco_hw = &pll_10nm->clk_hw; /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_save_state(phy); @@ -951,7 +955,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, /* Select full-rate mode */ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40); - ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase); + ret = dsi_10nm_set_usecase(phy); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index c7c462bfe96d..86f9aedd790f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -8,7 +8,6 @@ #include #include "dsi_phy.h" -#include "dsi_pll.h" #include "dsi.xml.h" #define PHY_14NM_CKLN_IDX 4 @@ -114,7 +113,7 @@ struct pll_14nm_cached_state { }; struct dsi_pll_14nm { - struct msm_dsi_pll base; + struct clk_hw clk_hw; int id; struct platform_device *pdev; @@ -122,6 +121,8 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; + struct msm_dsi_phy *phy; + struct dsi_pll_input in; struct dsi_pll_output out; @@ -133,11 +134,10 @@ struct dsi_pll_14nm { struct pll_14nm_cached_state cached_state; - enum msm_dsi_phy_usecase uc; struct dsi_pll_14nm *slave; }; -#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base) +#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw) /* * Private struct for N1/N2 post-divider clocks. These clocks are similar to @@ -564,8 +564,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); struct dsi_pll_input *pin = &pll_14nm->in; struct dsi_pll_output *pout = &pll_14nm->out; @@ -600,7 +599,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, * don't lock the slave PLL. We just ensure that the PLL/PHY registers * of the master and slave are identical */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; pll_db_commit_14nm(pll_14nm_slave, pin, pout); @@ -614,8 +613,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); void __iomem *base = pll_14nm->mmio; u64 vco_rate, multiplier = BIT(20); u32 div_frac_start; @@ -654,15 +652,14 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); void __iomem *base = pll_14nm->mmio; void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; bool locked; DBG(""); - if (unlikely(pll->pll_on)) + if (unlikely(pll_14nm->phy->pll_on)) return 0; pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); @@ -677,29 +674,41 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) } DBG("DSI PLL lock success"); - pll->pll_on = true; + pll_14nm->phy->pll_on = true; return 0; } static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; DBG(""); - if (unlikely(!pll->pll_on)) + if (unlikely(!pll_14nm->phy->pll_on)) return; pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); - pll->pll_on = false; + pll_14nm->phy->pll_on = false; +} + +static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); + + if (rate < pll_14nm->phy->cfg->min_pll_rate) + return pll_14nm->phy->cfg->min_pll_rate; + else if (rate > pll_14nm->phy->cfg->max_pll_rate) + return pll_14nm->phy->cfg->max_pll_rate; + else + return rate; } static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_14nm_clk_round_rate, .set_rate = dsi_pll_14nm_vco_set_rate, .recalc_rate = dsi_pll_14nm_vco_recalc_rate, .prepare = dsi_pll_14nm_vco_prepare, @@ -773,7 +782,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, /* If we're master in dual DSI mode, then the slave PLL's post-dividers * follow the master's post dividers */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; @@ -797,7 +806,7 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { static void dsi_14nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; u32 data; @@ -810,18 +819,18 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy) DBG("DSI%d PLL save state %x %x", pll_14nm->id, cached_state->n1postdiv, cached_state->n2postdiv); - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); } static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; u32 data; int ret; - ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw, + ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_14nm->pdev->dev, @@ -837,7 +846,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); /* also restore post-dividers for slave DSI PLL */ - if (pll_14nm->uc == MSM_DSI_PHY_MASTER) { + if (phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; @@ -847,14 +856,13 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) return 0; } -static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) +static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) { - struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); + struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); void __iomem *base = pll_14nm->mmio; u32 clkbuflr_en, bandgap = 0; - switch (uc) { + switch (phy->usecase) { case MSM_DSI_PHY_STANDALONE: clkbuflr_en = 0x1; break; @@ -874,8 +882,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, if (bandgap) pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); - pll_14nm->uc = uc; - return 0; } @@ -932,9 +938,9 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov DBG("DSI%d", pll_14nm->id); snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); - pll_14nm->base.clk_hw.init = &vco_init; + pll_14nm->clk_hw.init = &vco_init; - ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); if (ret) return ret; @@ -990,7 +996,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) struct platform_device *pdev = phy->pdev; int id = phy->id; struct dsi_pll_14nm *pll_14nm; - struct msm_dsi_pll *pll; int ret; if (!pdev) @@ -1020,8 +1025,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_14nm->postdiv_lock); - pll = &pll_14nm->base; - pll->cfg = phy->cfg; + pll_14nm->phy = phy; ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); if (ret) { @@ -1029,7 +1033,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) return ret; } - phy->pll = pll; + phy->vco_hw = &pll_14nm->clk_hw; return 0; } @@ -1131,7 +1135,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL); - ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase); + ret = dsi_14nm_set_usecase(phy); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 8f10dbb0c136..8ac6061246fd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -7,7 +7,6 @@ #include #include "dsi_phy.h" -#include "dsi_pll.h" #include "dsi.xml.h" /* @@ -66,16 +65,19 @@ struct pll_28nm_cached_state { }; struct dsi_pll_28nm { - struct msm_dsi_pll base; + struct clk_hw clk_hw; int id; struct platform_device *pdev; + + struct msm_dsi_phy *phy; + void __iomem *mmio; struct pll_28nm_cached_state cached_state; }; -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw) static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 nb_tries, u32 timeout_us) @@ -116,8 +118,7 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; unsigned long div_fbx1000, gen_vco_clk; @@ -210,7 +211,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); /* Add hardware recommended delay for correct PLL configuration */ - if (pll->cfg->type == MSM_DSI_PHY_28NM_HPM) + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) udelay(1); else /* LP */ udelay(1000); @@ -233,8 +234,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, POLL_TIMEOUT_US); @@ -243,8 +243,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; @@ -289,9 +288,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, return vco_rate; } -static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll) +static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; u32 max_reads = 5, timeout_us = 100; @@ -366,16 +364,16 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll) static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); int i, ret; - if (unlikely(pll->pll_on)) + if (unlikely(pll_28nm->phy->pll_on)) return 0; for (i = 0; i < 3; i++) { - ret = _dsi_pll_28nm_vco_prepare_hpm(pll); + ret = _dsi_pll_28nm_vco_prepare_hpm(pll_28nm); if (!ret) { - pll->pll_on = true; + pll_28nm->phy->pll_on = true; return 0; } } @@ -385,8 +383,7 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; bool locked; @@ -395,7 +392,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) DBG("id=%d", pll_28nm->id); - if (unlikely(pll->pll_on)) + if (unlikely(pll_28nm->phy->pll_on)) return 0; pll_28nm_software_reset(pll_28nm); @@ -428,28 +425,40 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) } DBG("DSI PLL lock success"); - pll->pll_on = true; + pll_28nm->phy->pll_on = true; return 0; } static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); DBG("id=%d", pll_28nm->id); - if (unlikely(!pll->pll_on)) + if (unlikely(!pll_28nm->phy->pll_on)) return; pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); - pll->pll_on = false; + pll_28nm->phy->pll_on = false; +} + +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + + if (rate < pll_28nm->phy->cfg->min_pll_rate) + return pll_28nm->phy->cfg->min_pll_rate; + else if (rate > pll_28nm->phy->cfg->max_pll_rate) + return pll_28nm->phy->cfg->max_pll_rate; + else + return rate; } static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_28nm_clk_round_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare_hpm, @@ -458,7 +467,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { }; static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_28nm_clk_round_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare_lp, @@ -472,7 +481,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; @@ -481,20 +490,20 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) cached_state->postdiv1 = pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); - if (dsi_pll_28nm_clk_is_enabled(&phy->pll->clk_hw)) - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); + if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw)) + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); else cached_state->vco_rate = 0; } static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; int ret; - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_28nm->pdev->dev, @@ -527,14 +536,14 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov DBG("%d", pll_28nm->id); - if (pll_28nm->base.cfg->type == MSM_DSI_PHY_28NM_LP) + if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); - pll_28nm->base.clk_hw.init = &vco_init; - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw); + pll_28nm->clk_hw.init = &vco_init; + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw); if (ret) return ret; @@ -593,7 +602,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) struct platform_device *pdev = phy->pdev; int id = phy->id; struct dsi_pll_28nm *pll_28nm; - struct msm_dsi_pll *pll; int ret; if (!pdev) @@ -612,8 +620,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) return -ENOMEM; } - pll = &pll_28nm->base; - pll->cfg = phy->cfg; + pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { @@ -621,7 +628,7 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) return ret; } - phy->pll = pll; + phy->vco_hw = &pll_28nm->clk_hw; return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index c71c5f07666d..3e63a3b70818 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -7,7 +7,6 @@ #include #include "dsi_phy.h" -#include "dsi_pll.h" #include "dsi.xml.h" /* @@ -58,16 +57,19 @@ struct clk_bytediv { }; struct dsi_pll_28nm { - struct msm_dsi_pll base; + struct clk_hw clk_hw; int id; struct platform_device *pdev; + + struct msm_dsi_phy *phy; + void __iomem *mmio; struct pll_28nm_cached_state cached_state; }; -#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, clk_hw) static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, int nb_tries, int timeout_us) @@ -95,8 +97,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); void __iomem *base = pll_28nm->mmio; u32 val, temp, fb_divider; @@ -136,8 +137,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, POLL_TIMEOUT_US); @@ -146,8 +146,7 @@ static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); void __iomem *base = pll_28nm->mmio; unsigned long vco_rate; u32 status, fb_divider, temp, ref_divider; @@ -180,8 +179,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; bool locked; @@ -191,7 +189,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) DBG("id=%d", pll_28nm->id); - if (unlikely(pll->pll_on)) + if (unlikely(pll_28nm->phy->pll_on)) return 0; /* @@ -222,28 +220,40 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) } DBG("DSI PLL lock success"); - pll->pll_on = true; + pll_28nm->phy->pll_on = true; return 0; } static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); DBG("id=%d", pll_28nm->id); - if (unlikely(!pll->pll_on)) + if (unlikely(!pll_28nm->phy->pll_on)) return; pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); - pll->pll_on = false; + pll_28nm->phy->pll_on = false; +} + +static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + + if (rate < pll_28nm->phy->cfg->min_pll_rate) + return pll_28nm->phy->cfg->min_pll_rate; + else if (rate > pll_28nm->phy->cfg->max_pll_rate) + return pll_28nm->phy->cfg->max_pll_rate; + else + return rate; } static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_28nm_clk_round_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare, @@ -336,7 +346,7 @@ static const struct clk_ops clk_bytediv_ops = { */ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; @@ -347,17 +357,17 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) cached_state->postdiv1 = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); - cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw); + cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); } static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->pll); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; void __iomem *base = pll_28nm->mmio; int ret; - ret = dsi_pll_28nm_clk_set_rate(&phy->pll->clk_hw, + ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_28nm->pdev->dev, @@ -407,9 +417,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); vco_init.name = vco_name; - pll_28nm->base.clk_hw.init = &vco_init; + pll_28nm->clk_hw.init = &vco_init; - ret = devm_clk_hw_register(dev, &pll_28nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw); if (ret) return ret; @@ -450,7 +460,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) struct platform_device *pdev = phy->pdev; int id = phy->id; struct dsi_pll_28nm *pll_28nm; - struct msm_dsi_pll *pll; int ret; if (!pdev) @@ -469,9 +478,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) return -ENOMEM; } - pll = &pll_28nm->base; - - pll->cfg = phy->cfg; + pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { @@ -479,7 +486,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) return ret; } - phy->pll = pll; + phy->vco_hw = &pll_28nm->clk_hw; return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 015e099d7b7f..c922e46f5241 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -7,7 +7,6 @@ #include #include -#include "dsi_pll.h" #include "dsi_phy.h" #include "dsi.xml.h" @@ -85,11 +84,13 @@ struct pll_7nm_cached_state { }; struct dsi_pll_7nm { - struct msm_dsi_pll base; + struct clk_hw clk_hw; int id; struct platform_device *pdev; + struct msm_dsi_phy *phy; + void __iomem *phy_cmn_mmio; void __iomem *mmio; @@ -104,11 +105,10 @@ struct dsi_pll_7nm { struct pll_7nm_cached_state cached_state; - enum msm_dsi_phy_usecase uc; struct dsi_pll_7nm *slave; }; -#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, base) +#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw) /* * Global list of private DSI PLL struct pointers. We need this for Dual DSI @@ -164,7 +164,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) dec = div_u64(dec_multiple, multiplier); - if (!(pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) regs->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) regs->pll_clock_inverters = 0xa0; @@ -259,7 +259,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->mmio; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; @@ -293,9 +293,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); + pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); - if (pll->base.cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -321,8 +321,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll) static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate, parent_rate); @@ -420,8 +419,7 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); int rc; dsi_pll_enable_pll_bias(pll_7nm); @@ -444,7 +442,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) goto error; } - pll->pll_on = true; + pll_7nm->phy->pll_on = true; /* * assert power on reset for PHY digital in case the PLL is @@ -471,8 +469,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); /* * To avoid any stray glitches while abruptly powering down the PLL @@ -488,14 +485,13 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) } /* flush, ensure all register writes are done */ wmb(); - pll->pll_on = false; + pll_7nm->phy->pll_on = false; } static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); struct dsi_pll_config *config = &pll_7nm->pll_configuration; void __iomem *base = pll_7nm->mmio; u64 ref_clk = pll_7nm->vco_ref_clk_rate; @@ -531,8 +527,21 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, return (unsigned long)vco_rate; } +static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); + + if (rate < pll_7nm->phy->cfg->min_pll_rate) + return pll_7nm->phy->cfg->min_pll_rate; + else if (rate > pll_7nm->phy->cfg->max_pll_rate) + return pll_7nm->phy->cfg->max_pll_rate; + else + return rate; +} + static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { - .round_rate = msm_dsi_pll_helper_clk_round_rate, + .round_rate = dsi_pll_7nm_clk_round_rate, .set_rate = dsi_pll_7nm_vco_set_rate, .recalc_rate = dsi_pll_7nm_vco_recalc_rate, .prepare = dsi_pll_7nm_vco_prepare, @@ -545,7 +554,7 @@ static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { static void dsi_7nm_save_state(struct msm_dsi_phy *phy) { - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; @@ -568,7 +577,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy) static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) { - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 val; @@ -587,7 +596,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) val |= cached->pll_mux; pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_7nm_vco_set_rate(&phy->pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); if (ret) { DRM_DEV_ERROR(&pll_7nm->pdev->dev, "restore vco rate failed. ret=%d\n", ret); @@ -599,16 +608,15 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) return 0; } -static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, - enum msm_dsi_phy_usecase uc) +static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { - struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); void __iomem *base = pll_7nm->phy_cmn_mmio; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->id); - switch (uc) { + switch (phy->usecase) { case MSM_DSI_PHY_STANDALONE: break; case MSM_DSI_PHY_MASTER: @@ -624,8 +632,6 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, /* set PLL src */ pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); - pll_7nm->uc = uc; - return 0; } @@ -653,9 +659,9 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide DBG("DSI%d", pll_7nm->id); snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); - pll_7nm->base.clk_hw.init = &vco_init; + pll_7nm->clk_hw.init = &vco_init; - ret = devm_clk_hw_register(dev, &pll_7nm->base.clk_hw); + ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw); if (ret) return ret; @@ -765,7 +771,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) struct platform_device *pdev = phy->pdev; int id = phy->id; struct dsi_pll_7nm *pll_7nm; - struct msm_dsi_pll *pll; int ret; pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); @@ -792,8 +797,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) spin_lock_init(&pll_7nm->postdiv_lock); - pll = &pll_7nm->base; - pll->cfg = phy->cfg; + pll_7nm->phy = phy; ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); if (ret) { @@ -801,7 +805,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) return ret; } - phy->pll = pll; + phy->vco_hw = &pll_7nm->clk_hw; /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_save_state(phy); @@ -966,7 +970,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, /* Select full-rate mode */ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40); - ret = dsi_pll_7nm_set_usecase(phy->pll, phy->usecase); + ret = dsi_7nm_set_usecase(phy); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", __func__, ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c deleted file mode 100644 index cae668b669a4..000000000000 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. - */ - -#include "dsi_phy.h" -#include "dsi_pll.h" - -/* - * DSI PLL Helper functions - */ -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - - if (rate < pll->cfg->min_pll_rate) - return pll->cfg->min_pll_rate; - else if (rate > pll->cfg->max_pll_rate) - return pll->cfg->max_pll_rate; - else - return rate; -} diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h deleted file mode 100644 index da83e4c11f4f..000000000000 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. - */ - -#ifndef __DSI_PLL_H__ -#define __DSI_PLL_H__ - -#include - -#include "dsi.h" - -static inline void pll_write(void __iomem *reg, u32 data) -{ - msm_writel(data, reg); -} - -static inline u32 pll_read(const void __iomem *reg) -{ - return msm_readl(reg); -} - -static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) -{ - pll_write(reg, data); - udelay(delay_us); -} - -static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) -{ - pll_write((reg), data); - ndelay(delay_ns); -} - -/* - * DSI PLL Helper functions - */ - -/* clock callbacks */ -long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate); - -#endif /* __DSI_PLL_H__ */ - From patchwork Wed Mar 24 15:18:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407877 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502243jai; Wed, 24 Mar 2021 08:19:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8t/vdOy2BHtuUSuhda/0TSAedX/kI2JCj/85z9riQjkRVWjjxNL/tOUQ/DrXmObPskICN X-Received: by 2002:a17:90a:c201:: with SMTP id e1mr3990168pjt.30.1616599190488; Wed, 24 Mar 2021 08:19:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599190; cv=none; d=google.com; s=arc-20160816; b=cwFt7hvmOHdr5t0FA5JUhEHmuNgVelCmIjQlsAYWse7GXrcXT+UvTo/enK6NWS8l4m PQ2IUDvX9oPhO9xS4czPiZ/NSsK40pVhRNhUhiCf5fw1p2vRqdnM/DjgOuCnnzowN0Hx yW0WsSINYULG2Xf94cNd/UmkE2uSh15h9ypd5PKRKrgAwcdjCtOgMi0gcJsIBfdwHBNB IRwOuALjJvB8UIzeBuTAqPAVS2+hq/gQ5xFKzVJepAamyHlVbHQjvTVjgU1Os6tkvFzO Ovuzeyg6t68wsIP+VYkWy7UBQaTG9wMvwuxaSXUSrhy6mcGeFl7xlmNxsbrWoXNKoIOF nfeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=VKf6szquSao38lPj0FP2sGyYVuHTWPakiivWIRSwcZ8=; b=MYsTcT848xYqiOeI4OeKQPiO1mwyDmucyP1HT3dJMEgEbIWcuFp+wfasvpc09bPnYz K9X2CiEKjJnLl8ujN1YS/O11PyBTMaaY8gIGCHVYua58MKzVyEtoPKx4YqOkmoyD1MzK he9LFW8RJ0HEhL2nYu94rpCO4/D8cSmVkXKxTuVmpTBvjMdOOUxYHQNx/nKV7ckyrxKY 4IiY8ScKeToDJr3jNQUzuN7QapVYyOSlU0yTdYCsRcIIy4K+57VDiP3+OIolv1mrnK53 L7TiWqcqoPnrF5w3+IOfYWt9XnxPRwEOU7vFgR+ffS0wNDjvHSDyVDM+jqmEYzYWoIPw tyrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Jq5HJl+d; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id b136si2645588pga.86.2021.03.24.08.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Jq5HJl+d; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D78686EC91; Wed, 24 Mar 2021 15:19:40 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B1E846EC93 for ; Wed, 24 Mar 2021 15:19:38 +0000 (UTC) Received: by mail-lf1-x136.google.com with SMTP id w37so32507483lfu.13 for ; Wed, 24 Mar 2021 08:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ariaPipc4YhK3nsG6JRM+VjU2UE4m9KzlBowjgHgToA=; b=Jq5HJl+dy0z5vAR1GaoJeDp1pO+yVd5SXM7dwT74k5ln+9NxwvwONulCrKDk5S3qgI mCS48CyInW0xSLRJoWT9YUbfHUEN75GUwPQn7LHb+kUTSJD6lYXlEU3UJAmUH+FDvc8d SzFFPqh/Vm3T5CBV9KKmxqg1QxqmWYiBKtEsfMsk0Ua4rW2eTOGShn0MQYZ3NEaN/kJQ PQnSQqF7gbmT/ZxrLHnTuRlu5coSHE1SP4gCMJEnWYFs7lQXDt2Gmi6Lsg8qjm4xIUBd RGWGl+s9m4/SWdWuwOElWtJf6nWZwLWrs9mZdUdBHOi7J+TYIQJwm1Dl7L8bdD9QOQFG z4qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ariaPipc4YhK3nsG6JRM+VjU2UE4m9KzlBowjgHgToA=; b=cBCLUdAD7jMn3pVdvaBGfkqJU0wTB/s3Br7Zmz/075Ceq7BlJ8Jgp45FamDt3R9rDA rWJk8IvyzM5mIh4C6zhB/QD5kHMFd24/sgkY4QiAWjGdZr6Xavx7rfXuMQX56koSxY+J +OhOmyW9v3S4xviw/onBX4asxnvNAXKRdXhoLdVtGkO+JoYMOkKtRy+E3usaG/JkqLqU /BT0dHuYfMRHcZ0uclmTUXUD5yM9eDx2kxfd5pCA75YxI6wecXqYO837k8xYpWjAlbMo 7tyWM8wfFfd4UaCL60Vb+ntHRnx08FZeqMYsWIBKq8gU5soCJ067/kd+jXvVkCCxgDe+ wWcA== X-Gm-Message-State: AOAM530UCEbd1Bavin0rKetu3nbSp5PysAA3PQTsnM8pJ/8Ak+B59eMX AsTwlBip5QSZ64RnpSbF3kXKYXSQ2kD0oA== X-Received: by 2002:ac2:5e9d:: with SMTP id b29mr2289454lfq.31.1616599176837; Wed, 24 Mar 2021 08:19:36 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 23/28] drm/msm/dsi: drop PLL accessor functions Date: Wed, 24 Mar 2021 18:18:41 +0300 Message-Id: <20210324151846.2774204-24-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY accessors, reducing duplication. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 124 ++++++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 126 ++++++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 118 +++++++-------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 54 +++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 140 +++++++++--------- 6 files changed, 283 insertions(+), 303 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 4fe410c97d3a..d7031a35e2da 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -14,6 +14,8 @@ #define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset)) +#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); } +#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); } struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); @@ -120,27 +122,5 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, u32 bit_mask); -/* PLL accessors */ -static inline void pll_write(void __iomem *reg, u32 data) -{ - msm_writel(data, reg); -} - -static inline u32 pll_read(const void __iomem *reg) -{ - return msm_readl(reg); -} - -static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) -{ - pll_write(reg, data); - udelay(delay_us); -} - -static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) -{ - pll_write((reg), data); - ndelay(delay_ns); -} #endif /* __DSI_PHY_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index dec9beadddaa..73afbb597a9f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -234,19 +234,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) if (pll->pll_configuration.enable_ssc) { pr_debug("SSC is enabled\n"); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, regs->ssc_stepsize_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, regs->ssc_stepsize_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, regs->ssc_div_per_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, regs->ssc_div_per_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, regs->ssc_adjper_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, regs->ssc_adjper_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, SSC_EN | regs->ssc_control); } } @@ -255,26 +255,26 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) { void __iomem *base = pll->mmio; - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); - pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); - pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); } static void dsi_pll_commit(struct dsi_pll_10nm *pll) @@ -282,20 +282,20 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll) void __iomem *base = pll->mmio; struct dsi_pll_regs *reg = &pll->reg_setup; - pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); - pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); - pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); } @@ -351,21 +351,21 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, data & ~BIT(5)); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, data | BIT(5)); - pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); ndelay(250); } @@ -373,8 +373,8 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); } @@ -382,8 +382,8 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, data | BIT(5)); } @@ -404,7 +404,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) } /* Start PLL */ - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, + dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x01); /* @@ -426,10 +426,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) if (pll_10nm->slave) dsi_pll_enable_global_clk(pll_10nm->slave); - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, + dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); if (pll_10nm->slave) - pll_write(pll_10nm->slave->phy_cmn_mmio + + dsi_phy_write(pll_10nm->slave->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); error: @@ -438,7 +438,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) { - pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); dsi_pll_disable_pll_bias(pll); } @@ -452,7 +452,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_10nm); - pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); dsi_pll_disable_sub(pll_10nm); if (pll_10nm->slave) { dsi_pll_disable_global_clk(pll_10nm->slave); @@ -476,13 +476,13 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, u32 dec; u64 pll_freq, tmp64; - dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); + dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); dec &= 0xff; - frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & + frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & 0xff) << 8); - frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 0x3) << 16); /* @@ -534,15 +534,15 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy) void __iomem *phy_base = pll_10nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = pll_read(pll_10nm->mmio + + cached->pll_out_div = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); + cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); cached->bit_clk_div = cmn_clk_cfg0 & 0xf; cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); cached->pll_mux = cmn_clk_cfg1 & 0x3; DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", @@ -558,18 +558,18 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) u32 val; int ret; - val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + val = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); + dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, cached->bit_clk_div | (cached->pix_clk_div << 4)); - val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); val &= ~0x3; val |= cached->pll_mux; - pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); + dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); if (ret) { @@ -605,7 +605,7 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); + dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 86f9aedd790f..408192ae1456 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -172,7 +172,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, tries = nb_tries; while (tries--) { - val = pll_read(base + + val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); pll_locked = !!(val & BIT(5)); @@ -185,7 +185,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, if (!pll_locked) { tries = nb_tries; while (tries--) { - val = pll_read(base + + val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); pll_locked = !!(val & BIT(0)); @@ -387,29 +387,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) data = pin->ssc_adj_period; data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); data = (pin->ssc_adj_period >> 8); data &= 0x03; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); data = pout->ssc_period; data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); data = (pout->ssc_period >> 8); data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); data = pout->ssc_step_size; data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); data = (pout->ssc_step_size >> 8); data &= 0x0ff; - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); data = (pin->ssc_center & 0x01); data <<= 1; data |= 0x01; /* enable */ - pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); wmb(); /* make sure register committed */ } @@ -423,57 +423,57 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, /* confgiure the non frequency dependent pll registers */ data = 0; - pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); data = pout->pll_txclk_en; - pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); data = pout->pll_resetsm_cntrl; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); data = pout->pll_resetsm_cntrl2; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); data = pout->pll_resetsm_cntrl5; - pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); data = pout->pll_vco_div_ref & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); data = (pout->pll_vco_div_ref >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); data = pout->pll_kvco_div_ref & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); data = (pout->pll_kvco_div_ref >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); data = pout->pll_misc1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); data = pin->pll_ie_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); data = pin->pll_ip_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur; - pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); data = pin->pll_icpmset << 3 | pin->pll_icpcset; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); data = pin->pll_iptat_trim; - pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); } static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) @@ -483,13 +483,13 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) /* de assert pll start and apply pll sw reset */ /* stop pll */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); /* pll sw reset */ - pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); + dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); wmb(); /* make sure register committed */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); wmb(); /* make sure register committed */ } @@ -504,53 +504,53 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, DBG("DSI%d PLL", pll->id); data = pout->cmn_ldo_cntrl; - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); pll_db_commit_common(pll, pin, pout); pll_14nm_software_reset(pll); data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); data = 0xff; /* data, clk, pll normal operation */ - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); /* configure the frequency dependent pll registers */ data = pout->dec_start; - pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); data = pout->div_frac_start & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); data = (pout->div_frac_start >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); data = (pout->div_frac_start >> 16) & 0xf; - pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); data = pout->plllock_cmp & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); data = (pout->plllock_cmp >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); data = (pout->plllock_cmp >> 16) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); data = pin->plllock_cnt << 1 | pin->plllock_rng << 3; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); data = pout->pll_vco_count & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); data = (pout->pll_vco_count >> 8) & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); data = pout->pll_kvco_count & 0xff; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); data = (pout->pll_kvco_count >> 8) & 0x3; - pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1; - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); if (pin->ssc_en) pll_db_commit_ssc(pll); @@ -620,16 +620,16 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, u32 dec_start; u64 ref_clk = parent_rate; - dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); + dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); dec_start &= 0x0ff; DBG("dec_start = %x", dec_start); - div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) + div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) & 0xf) << 16; - div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) + div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) & 0xff) << 8; - div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) + div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) & 0xff; DBG("div_frac_start = %x", div_frac_start); @@ -662,8 +662,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) if (unlikely(pll_14nm->phy->pll_on)) return 0; - pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, POLL_TIMEOUT_US); @@ -689,7 +689,7 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_14nm->phy->pll_on)) return; - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); pll_14nm->phy->pll_on = false; } @@ -731,7 +731,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate); - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; + val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; val &= div_mask(width); return divider_recalc_rate(hw, parent_rate, val, NULL, @@ -773,11 +773,11 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(lock, flags); - val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); val &= ~(div_mask(width) << shift); val |= value << shift; - pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); /* If we're master in dual DSI mode, then the slave PLL's post-dividers * follow the master's post dividers @@ -786,7 +786,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); } spin_unlock_irqrestore(lock, flags); @@ -811,7 +811,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy) void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; u32 data; - data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); cached_state->n1postdiv = data & 0xf; cached_state->n2postdiv = (data >> 4) & 0xf; @@ -843,14 +843,14 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) DBG("DSI%d PLL restore state %x %x", pll_14nm->id, cached_state->n1postdiv, cached_state->n2postdiv); - pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); /* also restore post-dividers for slave DSI PLL */ if (phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; - pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); } return 0; @@ -878,9 +878,9 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) return -EINVAL; } - pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); if (bandgap) - pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 8ac6061246fd..5705c764c13e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -86,7 +86,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); + val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); if (pll_locked) @@ -107,9 +107,9 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) * Add HW recommended delays after toggling the software * reset bit off and back on. */ - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1); - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); } /* @@ -131,7 +131,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, VERB("rate=%lu, parent's=%lu", rate, parent_rate); /* Force postdiv2 to be div-4 */ - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); /* Configure the Loop filter resistance */ for (i = 0; i < LPFR_LUT_SIZE; i++) @@ -142,11 +142,11 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, rate); return -EINVAL; } - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); /* Loop filter capacitance values : c1 and c2 */ - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); - pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); rem = rate % VCO_REF_CLK_RATE; if (rem) { @@ -171,7 +171,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("Generated VCO Clock: %lu", gen_vco_clk); rem = 0; - sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); + sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; if (frac_n_mode) { sdm_cfg0 = 0x0; @@ -198,17 +198,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000); DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); - pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2)); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3)); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); /* Add hardware recommended delay for correct PLL configuration */ if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) @@ -216,18 +216,18 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, else /* LP */ udelay(1000); - pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); - pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); - pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); - pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); - pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); return 0; } @@ -253,27 +253,27 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, VERB("parent_rate=%lu", parent_rate); /* Check to see if the ref clk doubler is enabled */ - doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & + doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; ref_clk += (doubler * VCO_REF_CLK_RATE); /* see if it is integer mode or sdm mode */ - sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); + sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { /* integer mode */ sdm_byp_div = FIELD( - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; vco_rate = ref_clk * sdm_byp_div; } else { /* sdm mode */ sdm_dc_off = FIELD( - pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET); DBG("sdm_dc_off = %d", sdm_dc_off); - sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), + sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0); - sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), + sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8); sdm_freq_seed = (sdm3 << 8) | sdm2; DBG("sdm_freq_seed = %d", sdm_freq_seed); @@ -306,22 +306,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) * Add necessary delays recommended by hardware. */ val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); for (i = 0; i < 2; i++) { /* DSI Uniphy lock detect setting */ - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0c, 100); - pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); /* poll for PLL ready status */ locked = pll_28nm_poll_for_ready(pll_28nm, @@ -336,22 +336,22 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) * Add necessary delays recommended by hardware. */ val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); } if (unlikely(!locked)) @@ -401,21 +401,21 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) * PLL power up sequence. * Add necessary delays recommended by hardware. */ - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); /* DSI PLL toggle lock detect setting */ - pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); - pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); + dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); @@ -439,7 +439,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); + dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); pll_28nm->phy->pll_on = false; } @@ -486,10 +486,10 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) void __iomem *base = pll_28nm->mmio; cached_state->postdiv3 = - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); cached_state->postdiv1 = - pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); - cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); + dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); + cached_state->byte_mux = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw)) cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); else @@ -511,11 +511,11 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) return ret; } - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, cached_state->postdiv3); - pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, cached_state->postdiv1); - pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, cached_state->byte_mux); return 0; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 3e63a3b70818..faefae5ec23c 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -78,7 +78,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); + val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); if (pll_locked) @@ -107,29 +107,29 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, val = VCO_REF_CLK_RATE / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, fb_divider & 0xff); - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); val |= (fb_divider >> 8) & 0x07; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, val); - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, val); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, 0xf); - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val |= 0x7 << 4; - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); return 0; @@ -153,16 +153,16 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, VERB("parent_rate=%lu", parent_rate); - status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); + status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) { - fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); + fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); fb_divider &= 0xff; - temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; + temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; fb_divider = (temp << 8) | fb_divider; fb_divider += 1; - ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); ref_divider &= 0x3f; ref_divider += 1; @@ -199,17 +199,17 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) * 2: divide by 8 to get bit clock divider * 3: write it to POSTDIV1 */ - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); byte_div = val + 1; bit_div = byte_div / 8; - val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val &= ~0xf; val |= (bit_div - 1); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); /* enable the PLL */ - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); @@ -234,7 +234,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); + dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); pll_28nm->phy->pll_on = false; } @@ -281,7 +281,7 @@ static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw, struct clk_bytediv *bytediv = to_clk_bytediv(hw); unsigned int div; - div = pll_read(bytediv->reg) & 0xff; + div = dsi_phy_read(bytediv->reg) & 0xff; return parent_rate / (div + 1); } @@ -327,9 +327,9 @@ static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, factor = get_vco_mul_factor(rate); - val = pll_read(bytediv->reg); + val = dsi_phy_read(bytediv->reg); val |= (factor - 1) & 0xff; - pll_write(bytediv->reg, val); + dsi_phy_write(bytediv->reg, val); return 0; } @@ -351,11 +351,11 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) void __iomem *base = pll_28nm->mmio; cached_state->postdiv3 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); cached_state->postdiv2 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); cached_state->postdiv1 = - pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); } @@ -375,11 +375,11 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) return ret; } - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, cached_state->postdiv3); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, cached_state->postdiv2); - pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, + dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, cached_state->postdiv1); return 0; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c922e46f5241..b873b2f67e3a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -237,19 +237,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) if (pll->pll_configuration.enable_ssc) { pr_debug("SSC is enabled\n"); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, regs->ssc_stepsize_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, regs->ssc_stepsize_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, regs->ssc_div_per_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, regs->ssc_div_per_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, regs->ssc_adjper_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, regs->ssc_adjper_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, SSC_EN | regs->ssc_control); } } @@ -269,36 +269,36 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) vco_config_1 = 0x01; } - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, analog_controls_five_1); - pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - pll_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - pll_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); - pll_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - pll_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); - pll_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); - pll_write(base + REG_DSI_7nm_PHY_PLL_IFILT, + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - pll_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) - pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); } } @@ -307,15 +307,15 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll) void __iomem *base = pll->mmio; struct dsi_pll_regs *reg = &pll->reg_setup; - pll_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); - pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ - pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); } static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, @@ -369,19 +369,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); + dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); - pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); + dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); ndelay(250); } @@ -389,18 +389,18 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) { u32 data; - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); + data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); } static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) { u32 data; - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); - data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | BIT(5) | BIT(4)); } @@ -411,9 +411,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) * coming out of a CX or analog rail power collapse while * ensuring that the pads maintain LP00 or LP11 state */ - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); wmb(); /* Ensure that the reset is deasserted */ - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); wmb(); /* Ensure that the reset is deasserted */ } @@ -427,7 +427,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) dsi_pll_enable_pll_bias(pll_7nm->slave); /* Start PLL */ - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); + dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); /* * ensure all PLL configurations are written prior to checking @@ -463,7 +463,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) { - pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); + dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); dsi_pll_disable_pll_bias(pll); } @@ -477,7 +477,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_7nm); - pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); dsi_pll_disable_sub(pll_7nm); if (pll_7nm->slave) { dsi_pll_disable_global_clk(pll_7nm->slave); @@ -501,13 +501,13 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, u32 dec; u64 pll_freq, tmp64; - dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); + dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); dec &= 0xff; - frac = pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & + frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & 0xff) << 8); - frac |= ((pll_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 0x3) << 16); /* @@ -559,15 +559,15 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy) void __iomem *phy_base = pll_7nm->phy_cmn_mmio; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = pll_read(pll_7nm->mmio + + cached->pll_out_div = dsi_phy_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; - cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); + cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); cached->bit_clk_div = cmn_clk_cfg0 & 0xf; cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; - cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); cached->pll_mux = cmn_clk_cfg1 & 0x3; DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", @@ -583,18 +583,18 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) u32 val; int ret; - val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + val = dsi_phy_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - pll_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); + dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, cached->bit_clk_div | (cached->pix_clk_div << 4)); - val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); val &= ~0x3; val |= cached->pll_mux; - pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); + dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); if (ret) { @@ -630,7 +630,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); return 0; } From patchwork Wed Mar 24 15:18:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407885 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502506jai; Wed, 24 Mar 2021 08:20:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxIqyXbmqgkv0CFmJr0P0jqxsUTO1EpQVLPsBXMNI1bTalUcVDz6RbEt4cKhTuEBU0n1yEs X-Received: by 2002:a17:90a:ce82:: with SMTP id g2mr4017752pju.193.1616599207443; Wed, 24 Mar 2021 08:20:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599207; cv=none; d=google.com; s=arc-20160816; b=01zVcf2dzBgsOmQ+6j1EswLT83Ejx1qN3w842kZJlBogjhp6r89xAkjpZXE1WD7pf1 ea7Eu8suokP4Qfye33e+UxtVY6enHXEqawpHRHB51f8KH5+Duefd6nPPZ63gGKh/JeoP nJcHZwf1/2VyZUYhRiylHwyWIu5tliEOtFWKI4O1ln3ui6ubVYQ6bcAHSFK42qScnsPc cKfVxs/M1ZHfAuXr8A9FrUgeuzHRJfZrfTrU0Jj/mG2vlteh7Z9efE7aBwyBh/SJt1VF uW8aOXp4QO3ASNiW0JXg9DxPRO6PYHwDXZjkGc/b8gEg7MLt3KW/x+57wsTylvgImF5h 1aKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=tBMh21/hnyjPgl/y7glOOPNrZTIbejl65Vs2nXyDqdM=; b=iV4VMShGX7lEim/CPFmM7VYQPtL09mEdh2iTLeavnePHzDNHsh4hGfeC4vvr07907u J4jLNQe9i+DHb4M4al6J5zRJ7YVGjhJRLre2ZT1WKXgqPLnQn/nVImkZbAlkz2L3T1gO Z34krEw/Z8FvA7+nrM4tGM4A4/5exjh0qC2MbVNlswj4v+LeMk5+SNlJpzXE8YP4J0lJ MawIo5fwQPJZcuYibfXAJ6eI7Q1yyG86+yH1iiBB3a2V5I96iyg0uBwCRE4YIGMnoejK MGSqcrWHrmLMubJdASgwy8eR8u1dQ9Ux7U+b9OJwIX4KFfAsIcbAXMbpmJbgbtdpuxci MMmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=tsyUUfwD; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id x6si2514252pfr.331.2021.03.24.08.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=tsyUUfwD; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C6DB6EC85; Wed, 24 Mar 2021 15:19:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 95A6C6EC95 for ; Wed, 24 Mar 2021 15:19:39 +0000 (UTC) Received: by mail-lj1-x22b.google.com with SMTP id u9so3034246ljd.11 for ; Wed, 24 Mar 2021 08:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2ydSrCF1DxCgEeMGjcLCK72/dx2LVx7YC7t/d5oHwDE=; b=tsyUUfwDal+yB71gZAwh2xLGDGCgu+bcm1e1yVmyZyFbvUBR6GsbZ2WCi+MCNjo7oc r/MeqS4ULh/Z+Ap0IgwDu1Gt37YOYALfNycZlA8CLI/C1lGDSLr3HsqmgLtmsY740Wz5 snUnhOx8jpItEBMhvoKh3oEGxQj+cxTEOGRFQHgRiSLXHBjH75HlwD7q1d8ydNtUFFnn YlXWRrsAF5Izw2O6bi2DvyQsUopYtC+xqTgEYEOq3yhreadh9JUijI3hPwvQcKqk+le9 d6IfAMJHA2U7OqlOZYUJloYxvv4ZkOaexWPsDHIXoQCVNNWjDiRWR1Imvj3ccTlbC8vS u8PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2ydSrCF1DxCgEeMGjcLCK72/dx2LVx7YC7t/d5oHwDE=; b=Ah1oxTTGRx9vomW1qXMTUWBYKL4Q9GSkre2sgr/b9GX9iAIsEpb/c/r4CgJLRWw+TR jDaMAfZMZ3QqFMRqS55NvWcUKQr26Hlg+xqjDwaiOV0hDVV0XvOvYCKYLxhpXAFk72b+ +B/d7+l+shCmm/j0piN9W2TpSW2mJ1MVt22DER8OgziTWjwF5d/Bx97dwwCPqqlWf2B8 2pqVENvyQwaPcyBOVs+NDQFurVFD9AkGTiiMwHDM6ne644lwHdaYWaB2loHUvri6qhav nG2N7Y6XDHm1yCSg/38xgz+dJuVzi1T/1LrxCDXsg/qM6r/r5zeR4kxs+QjZfkVKo/4k jjYw== X-Gm-Message-State: AOAM531tfdUtlXl+XuL8iJAM5FW7KFZa06DbqYNi/aqWSjVX/F381CLA fQViYuZxR4LtlpYvjdaPxONrWw== X-Received: by 2002:a2e:9dd8:: with SMTP id x24mr2372525ljj.173.1616599177875; Wed, 24 Mar 2021 08:19:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:37 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 24/28] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Date: Wed, 24 Mar 2021 18:18:42 +0300 Message-Id: <20210324151846.2774204-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All PHY drivers would map dsi_pll area. Some PHY drivers would also map dsi_phy area again (a leftover from old PHY/PLL separation). Move all ioremaps to the common dsi_phy driver code and drop individual ioremapped areas from PHY drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 7 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 75 +++++++----------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 49 ++++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 33 +++----- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 27 +++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++----------- 7 files changed, 108 insertions(+), 163 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 1a49cb2d1184..4aeedcbbda32 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -682,6 +682,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR(phy->pll_base)) { + DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); + ret = -ENOMEM; + goto fail; + } + if (phy->cfg->has_phy_lane) { phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE"); if (IS_ERR(phy->lane_base)) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index d7031a35e2da..8e828c5ca8f4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -88,6 +88,7 @@ struct msm_dsi_dphy_timing { struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; + void __iomem *pll_base; void __iomem *reg_base; void __iomem *lane_base; int id; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 73afbb597a9f..8a15ae91d44b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -91,9 +91,6 @@ struct dsi_pll_10nm { struct msm_dsi_phy *phy; - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - u64 vco_ref_clk_rate; u64 vco_current_rate; @@ -228,7 +225,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; struct dsi_pll_regs *regs = &pll->reg_setup; if (pll->pll_configuration.enable_ssc) { @@ -253,7 +250,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); @@ -279,7 +276,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) static void dsi_pll_commit(struct dsi_pll_10nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; struct dsi_pll_regs *reg = &pll->reg_setup; dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); @@ -336,7 +333,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) u32 const delay_us = 100; u32 const timeout_us = 5000; - rc = readl_poll_timeout_atomic(pll->mmio + + rc = readl_poll_timeout_atomic(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE, status, ((status & BIT(0)) > 0), @@ -351,21 +348,21 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0, data & ~BIT(5)); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0, data | BIT(5)); - dsi_phy_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); ndelay(250); } @@ -373,8 +370,8 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); } @@ -382,8 +379,8 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, data | BIT(5)); } @@ -404,7 +401,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) } /* Start PLL */ - dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x01); /* @@ -426,10 +423,10 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) if (pll_10nm->slave) dsi_pll_enable_global_clk(pll_10nm->slave); - dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); if (pll_10nm->slave) - dsi_phy_write(pll_10nm->slave->phy_cmn_mmio + + dsi_phy_write(pll_10nm->slave->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); error: @@ -438,7 +435,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) { - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); + dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); dsi_pll_disable_pll_bias(pll); } @@ -452,7 +449,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_10nm); - dsi_phy_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); dsi_pll_disable_sub(pll_10nm); if (pll_10nm->slave) { dsi_pll_disable_global_clk(pll_10nm->slave); @@ -468,7 +465,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); struct dsi_pll_config *config = &pll_10nm->pll_configuration; - void __iomem *base = pll_10nm->mmio; + void __iomem *base = pll_10nm->phy->pll_base; u64 ref_clk = pll_10nm->vco_ref_clk_rate; u64 vco_rate = 0x0; u64 multiplier; @@ -531,10 +528,10 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; - void __iomem *phy_base = pll_10nm->phy_cmn_mmio; + void __iomem *phy_base = pll_10nm->phy->base; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = dsi_phy_read(pll_10nm->mmio + + cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; @@ -554,14 +551,14 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; - void __iomem *phy_base = pll_10nm->phy_cmn_mmio; + void __iomem *phy_base = pll_10nm->phy->base; u32 val; int ret; - val = dsi_phy_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - dsi_phy_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); + dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, cached->bit_clk_div | (cached->pix_clk_div << 4)); @@ -586,7 +583,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw); - void __iomem *base = pll_10nm->phy_cmn_mmio; + void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_10nm->id); @@ -645,7 +642,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, - pll_10nm->mmio + + pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); if (IS_ERR(hw)) { @@ -659,7 +656,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov /* BIT CLK: DIV_CTRL_3_0 */ hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, - pll_10nm->phy_cmn_mmio + + pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, 0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); @@ -710,7 +707,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent, parent2, parent3, parent4 - }), 4, 0, pll_10nm->phy_cmn_mmio + + }), 4, 0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); if (IS_ERR(hw)) { @@ -723,7 +720,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov /* PIX CLK DIV : DIV_CTRL_7_4*/ hw = devm_clk_hw_register_divider(dev, clk_name, parent, - 0, pll_10nm->phy_cmn_mmio + + 0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, 4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); @@ -758,18 +755,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll_10nm->id = id; pll_10nm_list[id] = pll_10nm; - pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return -ENOMEM; - } - - pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_10nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return -ENOMEM; - } - spin_lock_init(&pll_10nm->postdiv_lock); pll_10nm->phy = phy; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 408192ae1456..5a92c2c1e815 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -118,9 +118,6 @@ struct dsi_pll_14nm { int id; struct platform_device *pdev; - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - struct msm_dsi_phy *phy; struct dsi_pll_input in; @@ -167,7 +164,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, u32 nb_tries, u32 timeout_us) { bool pll_locked = false; - void __iomem *base = pll_14nm->mmio; + void __iomem *base = pll_14nm->phy->pll_base; u32 tries, val; tries = nb_tries; @@ -380,7 +377,7 @@ static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; struct dsi_pll_input *pin = &pll->in; struct dsi_pll_output *pout = &pll->out; u8 data; @@ -418,7 +415,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, struct dsi_pll_input *pin, struct dsi_pll_output *pout) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; u8 data; /* confgiure the non frequency dependent pll registers */ @@ -478,7 +475,7 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) { - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + void __iomem *cmn_base = pll_14nm->phy->base; /* de assert pll start and apply pll sw reset */ @@ -497,8 +494,8 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, struct dsi_pll_input *pin, struct dsi_pll_output *pout) { - void __iomem *base = pll->mmio; - void __iomem *cmn_base = pll->phy_cmn_mmio; + void __iomem *base = pll->phy->pll_base; + void __iomem *cmn_base = pll->phy->base; u8 data; DBG("DSI%d PLL", pll->id); @@ -614,7 +611,7 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); - void __iomem *base = pll_14nm->mmio; + void __iomem *base = pll_14nm->phy->pll_base; u64 vco_rate, multiplier = BIT(20); u32 div_frac_start; u32 dec_start; @@ -653,8 +650,8 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); - void __iomem *base = pll_14nm->mmio; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + void __iomem *base = pll_14nm->phy->pll_base; + void __iomem *cmn_base = pll_14nm->phy->base; bool locked; DBG(""); @@ -682,7 +679,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + void __iomem *cmn_base = pll_14nm->phy->base; DBG(""); @@ -724,7 +721,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, { struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); struct dsi_pll_14nm *pll_14nm = postdiv->pll; - void __iomem *base = pll_14nm->phy_cmn_mmio; + void __iomem *base = pll_14nm->phy->base; u8 shift = postdiv->shift; u8 width = postdiv->width; u32 val; @@ -757,7 +754,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, { struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); struct dsi_pll_14nm *pll_14nm = postdiv->pll; - void __iomem *base = pll_14nm->phy_cmn_mmio; + void __iomem *base = pll_14nm->phy->base; spinlock_t *lock = &pll_14nm->postdiv_lock; u8 shift = postdiv->shift; u8 width = postdiv->width; @@ -784,7 +781,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, */ if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; + void __iomem *slave_base = pll_14nm_slave->phy->base; dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); } @@ -808,7 +805,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + void __iomem *cmn_base = pll_14nm->phy->base; u32 data; data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); @@ -826,7 +823,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; - void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; + void __iomem *cmn_base = pll_14nm->phy->base; u32 data; int ret; @@ -848,7 +845,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) /* also restore post-dividers for slave DSI PLL */ if (phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio; + void __iomem *slave_base = pll_14nm_slave->phy->base; dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); } @@ -859,7 +856,7 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); - void __iomem *base = pll_14nm->mmio; + void __iomem *base = phy->pll_base; u32 clkbuflr_en, bandgap = 0; switch (phy->usecase) { @@ -1011,18 +1008,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll_14nm->id = id; pll_14nm_list[id] = pll_14nm; - pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return -ENOMEM; - } - - pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_14nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return -ENOMEM; - } - spin_lock_init(&pll_14nm->postdiv_lock); pll_14nm->phy = phy; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 5705c764c13e..c08a08a50aaa 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -72,8 +72,6 @@ struct dsi_pll_28nm { struct msm_dsi_phy *phy; - void __iomem *mmio; - struct pll_28nm_cached_state cached_state; }; @@ -86,7 +84,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); + val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); if (pll_locked) @@ -101,7 +99,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) { - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; /* * Add HW recommended delays after toggling the software @@ -120,7 +118,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; unsigned long div_fbx1000, gen_vco_clk; u32 refclk_cfg, frac_n_mode, frac_n_value; u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; @@ -244,7 +242,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; u32 ref_clk = VCO_REF_CLK_RATE; @@ -291,7 +289,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) { struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; u32 max_reads = 5, timeout_us = 100; bool locked; u32 val; @@ -385,7 +383,7 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; bool locked; u32 max_reads = 10, timeout_us = 50; u32 val; @@ -439,7 +437,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); + dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); pll_28nm->phy->pll_on = false; } @@ -483,7 +481,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; cached_state->postdiv3 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); @@ -500,7 +498,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; int ret; ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, @@ -551,7 +549,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); hw = devm_clk_hw_register_divider(dev, clk_name, parent1, CLK_SET_RATE_PARENT, - pll_28nm->mmio + + pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, 0, 4, 0, NULL); if (IS_ERR(hw)) @@ -568,7 +566,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); hw = devm_clk_hw_register_divider(dev, clk_name, - parent1, 0, pll_28nm->mmio + + parent1, 0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, 0, 8, 0, NULL); if (IS_ERR(hw)) @@ -581,7 +579,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent1, parent2 - }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + + }), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); @@ -613,13 +611,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) pll_28nm->pdev = pdev; pll_28nm->id = id; - - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_28nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return -ENOMEM; - } - pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index faefae5ec23c..36ee3f15d1e0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -64,8 +64,6 @@ struct dsi_pll_28nm { struct msm_dsi_phy *phy; - void __iomem *mmio; - struct pll_28nm_cached_state cached_state; }; @@ -78,7 +76,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = dsi_phy_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); + val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); if (pll_locked) @@ -98,7 +96,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; u32 val, temp, fb_divider; DBG("rate=%lu, parent's=%lu", rate, parent_rate); @@ -147,7 +145,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; unsigned long vco_rate; u32 status, fb_divider, temp, ref_divider; @@ -181,7 +179,7 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); struct device *dev = &pll_28nm->pdev->dev; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; bool locked; unsigned int bit_div, byte_div; int max_reads = 1000, timeout_us = 100; @@ -234,7 +232,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - dsi_phy_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); + dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); pll_28nm->phy->pll_on = false; } @@ -348,7 +346,7 @@ static void dsi_28nm_save_state(struct msm_dsi_phy *phy) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; cached_state->postdiv3 = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); @@ -364,7 +362,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(phy->vco_hw); struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; - void __iomem *base = pll_28nm->mmio; + void __iomem *base = pll_28nm->phy->pll_base; int ret; ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, @@ -425,7 +423,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov /* prepare and register bytediv */ bytediv->hw.init = &bytediv_init; - bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; + bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id); snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); @@ -445,7 +443,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); /* DIV3 */ hw = devm_clk_hw_register_divider(dev, clk_name, - parent_name, 0, pll_28nm->mmio + + parent_name, 0, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, 0, 8, 0, NULL); if (IS_ERR(hw)) @@ -471,13 +469,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) pll_28nm->pdev = pdev; pll_28nm->id = id + 1; - - pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_28nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - return -ENOMEM; - } - pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index b873b2f67e3a..8e8cf9e63e8f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -91,9 +91,6 @@ struct dsi_pll_7nm { struct msm_dsi_phy *phy; - void __iomem *phy_cmn_mmio; - void __iomem *mmio; - u64 vco_ref_clk_rate; u64 vco_current_rate; @@ -231,7 +228,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; struct dsi_pll_regs *regs = &pll->reg_setup; if (pll->pll_configuration.enable_ssc) { @@ -256,7 +253,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { @@ -298,13 +295,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) - dsi_phy_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); } } static void dsi_pll_commit(struct dsi_pll_7nm *pll) { - void __iomem *base = pll->mmio; + void __iomem *base = pll->phy->pll_base; struct dsi_pll_regs *reg = &pll->reg_setup; dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); @@ -354,7 +351,7 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) u32 const delay_us = 100; u32 const timeout_us = 5000; - rc = readl_poll_timeout_atomic(pll->mmio + + rc = readl_poll_timeout_atomic(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE, status, ((status & BIT(0)) > 0), @@ -369,19 +366,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); + dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); - dsi_phy_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); + dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); ndelay(250); } @@ -389,18 +386,18 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) { u32 data; - data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); + data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); } static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) { u32 data; - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); - data = dsi_phy_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, + data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | BIT(5) | BIT(4)); } @@ -411,9 +408,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) * coming out of a CX or analog rail power collapse while * ensuring that the pads maintain LP00 or LP11 state */ - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); wmb(); /* Ensure that the reset is deasserted */ - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); wmb(); /* Ensure that the reset is deasserted */ } @@ -427,7 +424,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) dsi_pll_enable_pll_bias(pll_7nm->slave); /* Start PLL */ - dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); + dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); /* * ensure all PLL configurations are written prior to checking @@ -463,7 +460,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) { - dsi_phy_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); + dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); dsi_pll_disable_pll_bias(pll); } @@ -477,7 +474,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_7nm); - dsi_phy_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); + dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); dsi_pll_disable_sub(pll_7nm); if (pll_7nm->slave) { dsi_pll_disable_global_clk(pll_7nm->slave); @@ -493,7 +490,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); struct dsi_pll_config *config = &pll_7nm->pll_configuration; - void __iomem *base = pll_7nm->mmio; + void __iomem *base = pll_7nm->phy->pll_base; u64 ref_clk = pll_7nm->vco_ref_clk_rate; u64 vco_rate = 0x0; u64 multiplier; @@ -556,10 +553,10 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; - void __iomem *phy_base = pll_7nm->phy_cmn_mmio; + void __iomem *phy_base = pll_7nm->phy->base; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = dsi_phy_read(pll_7nm->mmio + + cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; @@ -579,14 +576,14 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; - void __iomem *phy_base = pll_7nm->phy_cmn_mmio; + void __iomem *phy_base = pll_7nm->phy->base; u32 val; int ret; - val = dsi_phy_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - dsi_phy_write(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); + dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, cached->bit_clk_div | (cached->pix_clk_div << 4)); @@ -611,7 +608,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); - void __iomem *base = pll_7nm->phy_cmn_mmio; + void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->id); @@ -670,7 +667,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, - pll_7nm->mmio + + pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); if (IS_ERR(hw)) { @@ -684,7 +681,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide /* BIT CLK: DIV_CTRL_3_0 */ hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, - pll_7nm->phy_cmn_mmio + + pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); @@ -735,7 +732,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent, parent2, parent3, parent4 - }), 4, 0, pll_7nm->phy_cmn_mmio + + }), 4, 0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); if (IS_ERR(hw)) { @@ -748,7 +745,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide /* PIX CLK DIV : DIV_CTRL_7_4*/ hw = devm_clk_hw_register_divider(dev, clk_name, parent, - 0, pll_7nm->phy_cmn_mmio + + 0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); @@ -783,18 +780,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll_7nm->id = id; pll_7nm_list[id] = pll_7nm; - pll_7nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(pll_7nm->phy_cmn_mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n"); - return -ENOMEM; - } - - pll_7nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); - if (IS_ERR_OR_NULL(pll_7nm->mmio)) { - DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); - return -ENOMEM; - } - spin_lock_init(&pll_7nm->postdiv_lock); pll_7nm->phy = phy; From patchwork Wed Mar 24 15:18:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407889 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502615jai; Wed, 24 Mar 2021 08:20:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyXuXYQ1XsLn45z3uJBFYOULpw8wJAZjHtBW3PaO+42AQSTjp4DJi7spCGxyQbTLK4FTenC X-Received: by 2002:a17:90a:d3d8:: with SMTP id d24mr3841002pjw.166.1616599214191; Wed, 24 Mar 2021 08:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599214; cv=none; d=google.com; s=arc-20160816; b=ZVcWZgD4wkIst8wrzlic+irazdsiU4fGZUFE8BS4YyXjrhpQsLgpcskBGTWNCKwoWp I2z9O/jz6Faq9MaDG3Ax6XmqLPP+EZ0F8VW4eMRvs38ZewJ+VPsI29QSXkRO/EeiF8bN s1us2xHiOQZ+kjs7zRpr/J0mfDUM9MMT22lMLlhY7mveXanmChHvbwihJdmXDHmia5L6 fKZd/6yOQNSQrEbzEQF8tkuFhxf1HCiBQMzB+Caz/Tx184qyMt4VdyFrjwCI8tSqI7KU rLdx4hw5+imMg7uxVp6QWErtwJTu+kXESifOXL1c+p6Hjn2hjNtvm9W/t4lN5ItLMSZX lKOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=1tDBhLvnQxQc3CN87OrTcC0V/+QuCkhNM8K/f7uCD5Y=; b=fKJ1nSUQqS4jAvNpKMJqkgKhEYap/d8gcWJyUls1YT/6JCUAxq4xZCQlOvfTGB0/Ki /we8uI/YsH3gcr2egiB9RNxuVvuRBbodB5yLFaMUPwL0lIuwJdD2iDBDJ9RxsVswjA3i 1E5DTYEku21msVZelP+OUIBlsyxrl5hNDsV58MWSV11QdQpG0Bym2YpkjgywatvQjpFx PUgEwNz6w2Y8XSvB42bYN0+SsowhAT+sYQcfUMP1cFG7AvANdgb5/w1sgilbJyUTG7Vv cZ3zhEJZra/sZCJxDZDysjthk1PN4vL+fS9Gtbteizl0uiZN807BKlvBG93ztihx2qrl dsjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Er9XQGwr; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id gx7si2328983pjb.22.2021.03.24.08.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Er9XQGwr; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A701B6ECA7; Wed, 24 Mar 2021 15:19:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by gabe.freedesktop.org (Postfix) with ESMTPS id DDAC06EC92 for ; Wed, 24 Mar 2021 15:19:40 +0000 (UTC) Received: by mail-lj1-x231.google.com with SMTP id s17so30687894ljc.5 for ; Wed, 24 Mar 2021 08:19:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e9faweW688cDlQgAKBHXoc/fFh852mH60dUS64owasQ=; b=Er9XQGwrvDgc7Juarx4fOzIqnrXCNyXYRPYZ5IU6ITGq1wLAAF/KiIwqnrhmrB3rIH 9CH4V+rSuiVqGxjfvOybm6mOZ/q0SJz9DssRRxx/p/r1OyzDqE8EbBoJ927GEC7mANM1 wUJY0Su8e3MfDnUoNYRZ1nIpo76u/M7sYdF0ODCGh9zHPvadMYcvSoILZmFGTDp+i9s2 VVrMc3TIWPNMIL8vmy7flizDYkOS0r4E48eN68V4SagBVdangBsZPFuNSc9LQgqra/+D B884p07/yZO6tc1xJOitKQxLBgSFF6gB5o9eLNaL5wcqJuISpg1rp47oWolVclGhETsH jCaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e9faweW688cDlQgAKBHXoc/fFh852mH60dUS64owasQ=; b=Mm50A0IPm8QbZC4Kv5GMJRycgCqAYxHT0fDIrk2MpolTkf28tJexMZ0pP/DgSNLnFZ +app/RrPWg+G9uLNTIUBwTaP5bQRrsHWef7yPIU18YtK9AACHt/m8XaaYh5ItdKuQxuy 0V3A3aN3VE51N6+ML6TvYhPrUorekZI21meu1XwoVnBOK1j6KVzocO7l8XDcQTCYb4uT shc2ya4Ao587emRxRHf7LssKEy/bV8muUXFL0RECERGfL53GHO4rgOt4BF1cHSWiMgzz mqL+8hIibfM6Evm+65YxGwOCd9qvLxSDMjiZDUgSt1CF2H2i9RrU1+DYAHUf39i1Xlli zenw== X-Gm-Message-State: AOAM531X0fgJZ9+KrKUEcOKvBoBJbGgw7sSIuvCiPj6cFqmeElwcI3nE bgTzGLteN3uxvoek9kA8cX7+0Q== X-Received: by 2002:a2e:94c8:: with SMTP id r8mr2470663ljh.332.1616599179136; Wed, 24 Mar 2021 08:19:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 25/28] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Date: Wed, 24 Mar 2021 18:18:43 +0300 Message-Id: <20210324151846.2774204-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse those fields from the provided msm_dsi_phy. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 72 +++++++++---------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 54 +++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 48 ++++++------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 26 +++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 68 ++++++++---------- 5 files changed, 119 insertions(+), 149 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 8a15ae91d44b..b937e77b3c37 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -86,9 +86,6 @@ struct pll_10nm_cached_state { struct dsi_pll_10nm { struct clk_hw clk_hw; - int id; - struct platform_device *pdev; - struct msm_dsi_phy *phy; u64 vco_ref_clk_rate; @@ -301,7 +298,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate, + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate, parent_rate); pll_10nm->vco_current_rate = rate; @@ -327,7 +324,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) { - struct device *dev = &pll->pdev->dev; + struct device *dev = &pll->phy->pdev->dev; int rc; u32 status = 0; u32 const delay_us = 100; @@ -341,7 +338,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) timeout_us); if (rc) DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n", - pll->id, status); + pll->phy->id, status); return rc; } @@ -387,7 +384,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); - struct device *dev = &pll_10nm->pdev->dev; + struct device *dev = &pll_10nm->phy->pdev->dev; int rc; dsi_pll_enable_pll_bias(pll_10nm); @@ -413,7 +410,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) /* Check for PLL lock */ rc = dsi_pll_10nm_lock_status(pll_10nm); if (rc) { - DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id); + DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id); goto error; } @@ -494,7 +491,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, vco_rate = pll_freq; DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", - pll_10nm->id, (unsigned long)vco_rate, dec, frac); + pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac); return (unsigned long)vco_rate; } @@ -543,7 +540,7 @@ static void dsi_10nm_save_state(struct msm_dsi_phy *phy) cached->pll_mux = cmn_clk_cfg1 & 0x3; DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", - pll_10nm->id, cached->pll_out_div, cached->bit_clk_div, + pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div, cached->pix_clk_div, cached->pll_mux); } @@ -570,12 +567,12 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); if (ret) { - DRM_DEV_ERROR(&pll_10nm->pdev->dev, + DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); return ret; } - DBG("DSI PLL%d", pll_10nm->id); + DBG("DSI PLL%d", pll_10nm->phy->id); return 0; } @@ -586,13 +583,13 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ - DBG("DSI PLL%d", pll_10nm->id); + DBG("DSI PLL%d", pll_10nm->phy->id); switch (phy->usecase) { case MSM_DSI_PHY_STANDALONE: break; case MSM_DSI_PHY_MASTER: - pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX]; + pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX]; break; case MSM_DSI_PHY_SLAVE: data = 0x1; /* external PLL */ @@ -624,21 +621,21 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_10nm_vco, }; - struct device *dev = &pll_10nm->pdev->dev; + struct device *dev = &pll_10nm->phy->pdev->dev; struct clk_hw *hw; int ret; - DBG("DSI%d", pll_10nm->id); + DBG("DSI%d", pll_10nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); + snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id); pll_10nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id); hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, @@ -650,8 +647,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); /* BIT CLK: DIV_CTRL_3_0 */ hw = devm_clk_hw_register_divider(dev, clk_name, parent, @@ -665,8 +662,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, @@ -678,8 +675,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); @@ -688,8 +685,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4); @@ -698,11 +695,11 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov goto fail; } - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id); hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ @@ -715,8 +712,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id); + snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ hw = devm_clk_hw_register_divider(dev, clk_name, parent, @@ -741,7 +738,6 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) { struct platform_device *pdev = phy->pdev; - int id = phy->id; struct dsi_pll_10nm *pll_10nm; int ret; @@ -749,11 +745,9 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) if (!pll_10nm) return -ENOMEM; - DBG("DSI PLL%d", id); + DBG("DSI PLL%d", phy->id); - pll_10nm->pdev = pdev; - pll_10nm->id = id; - pll_10nm_list[id] = pll_10nm; + pll_10nm_list[phy->id] = pll_10nm; spin_lock_init(&pll_10nm->postdiv_lock); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 5a92c2c1e815..8b4865c5796d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -115,9 +115,6 @@ struct pll_14nm_cached_state { struct dsi_pll_14nm { struct clk_hw clk_hw; - int id; - struct platform_device *pdev; - struct msm_dsi_phy *phy; struct dsi_pll_input in; @@ -498,7 +495,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, void __iomem *cmn_base = pll->phy->base; u8 data; - DBG("DSI%d PLL", pll->id); + DBG("DSI%d PLL", pll->phy->id); data = pout->cmn_ldo_cntrl; dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); @@ -565,7 +562,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, struct dsi_pll_input *pin = &pll_14nm->in; struct dsi_pll_output *pout = &pll_14nm->out; - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate, + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate, parent_rate); pll_14nm->vco_current_rate = rate; @@ -666,7 +663,7 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) POLL_TIMEOUT_US); if (unlikely(!locked)) { - DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); + DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n"); return -EINVAL; } @@ -726,7 +723,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, u8 width = postdiv->width; u32 val; - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate); + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate); val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; val &= div_mask(width); @@ -742,7 +739,7 @@ static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); struct dsi_pll_14nm *pll_14nm = postdiv->pll; - DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate); + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); return divider_round_rate(hw, rate, prate, NULL, postdiv->width, @@ -762,7 +759,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long flags = 0; u32 val; - DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate, + DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate, parent_rate); value = divider_get_val(rate, parent_rate, NULL, postdiv->width, @@ -813,7 +810,7 @@ static void dsi_14nm_save_state(struct msm_dsi_phy *phy) cached_state->n1postdiv = data & 0xf; cached_state->n2postdiv = (data >> 4) & 0xf; - DBG("DSI%d PLL save state %x %x", pll_14nm->id, + DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id, cached_state->n1postdiv, cached_state->n2postdiv); cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); @@ -830,14 +827,14 @@ static int dsi_14nm_restore_state(struct msm_dsi_phy *phy) ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { - DRM_DEV_ERROR(&pll_14nm->pdev->dev, + DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); return ret; } data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); - DBG("DSI%d PLL restore state %x %x", pll_14nm->id, + DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id, cached_state->n1postdiv, cached_state->n2postdiv); dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); @@ -865,7 +862,7 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: clkbuflr_en = 0x3; - pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX]; + pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX]; break; case MSM_DSI_PHY_SLAVE: clkbuflr_en = 0x0; @@ -889,7 +886,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, u8 shift) { struct dsi_pll_14nm_postdiv *pll_postdiv; - struct device *dev = &pll_14nm->pdev->dev; + struct device *dev = &pll_14nm->phy->pdev->dev; struct clk_init_data postdiv_init = { .parent_names = (const char *[]) { parent_name }, .num_parents = 1, @@ -928,21 +925,21 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_14nm_vco, }; - struct device *dev = &pll_14nm->pdev->dev; + struct device *dev = &pll_14nm->phy->pdev->dev; struct clk_hw *hw; int ret; - DBG("DSI%d", pll_14nm->id); + DBG("DSI%d", pll_14nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id); + snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id); pll_14nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id); + snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id); /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, @@ -950,8 +947,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); + snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id); + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); /* DSI Byte clock = VCO_CLK / N1 / 8 */ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, @@ -961,8 +958,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id); + snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); + snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); /* * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider @@ -972,8 +969,8 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id); - snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id); + snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id); + snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 * This is the output of N2 post-divider, bits 4-7 in @@ -991,7 +988,6 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) { struct platform_device *pdev = phy->pdev; - int id = phy->id; struct dsi_pll_14nm *pll_14nm; int ret; @@ -1002,11 +998,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) if (!pll_14nm) return -ENOMEM; - DBG("PLL%d", id); + DBG("PLL%d", phy->id); - pll_14nm->pdev = pdev; - pll_14nm->id = id; - pll_14nm_list[id] = pll_14nm; + pll_14nm_list[phy->id] = pll_14nm; spin_lock_init(&pll_14nm->postdiv_lock); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index c08a08a50aaa..8c973775cfb0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -67,9 +67,6 @@ struct pll_28nm_cached_state { struct dsi_pll_28nm { struct clk_hw clk_hw; - int id; - struct platform_device *pdev; - struct msm_dsi_phy *phy; struct pll_28nm_cached_state cached_state; @@ -117,7 +114,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; void __iomem *base = pll_28nm->phy->pll_base; unsigned long div_fbx1000, gen_vco_clk; u32 refclk_cfg, frac_n_mode, frac_n_value; @@ -288,14 +285,14 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) { - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; void __iomem *base = pll_28nm->phy->pll_base; u32 max_reads = 5, timeout_us = 100; bool locked; u32 val; int i; - DBG("id=%d", pll_28nm->id); + DBG("id=%d", pll_28nm->phy->id); pll_28nm_software_reset(pll_28nm); @@ -382,13 +379,13 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; void __iomem *base = pll_28nm->phy->pll_base; bool locked; u32 max_reads = 10, timeout_us = 50; u32 val; - DBG("id=%d", pll_28nm->id); + DBG("id=%d", pll_28nm->phy->id); if (unlikely(pll_28nm->phy->pll_on)) return 0; @@ -432,7 +429,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - DBG("id=%d", pll_28nm->id); + DBG("id=%d", pll_28nm->phy->id); if (unlikely(!pll_28nm->phy->pll_on)) return; @@ -504,7 +501,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { - DRM_DEV_ERROR(&pll_28nm->pdev->dev, + DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); return ret; } @@ -528,25 +525,25 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov .name = vco_name, .flags = CLK_IGNORE_UNUSED, }; - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; struct clk_hw *hw; int ret; - DBG("%d", pll_28nm->id); + DBG("%d", pll_28nm->phy->id); if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); pll_28nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); hw = devm_clk_hw_register_divider(dev, clk_name, parent1, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base + @@ -555,16 +552,16 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); - snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); + snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 2); if (IS_ERR(hw)) return PTR_ERR(hw); - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); hw = devm_clk_hw_register_divider(dev, clk_name, parent1, 0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, @@ -573,9 +570,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov return PTR_ERR(hw); provided_clocks[DSI_PIXEL_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->phy->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); + snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ parent1, parent2 @@ -584,8 +581,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (IS_ERR(hw)) return PTR_ERR(hw); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); - snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id); + snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 4); if (IS_ERR(hw)) @@ -598,7 +595,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) { struct platform_device *pdev = phy->pdev; - int id = phy->id; struct dsi_pll_28nm *pll_28nm; int ret; @@ -609,8 +605,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) if (!pll_28nm) return -ENOMEM; - pll_28nm->pdev = pdev; - pll_28nm->id = id; pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 36ee3f15d1e0..9ddd0adccce3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -59,9 +59,6 @@ struct clk_bytediv { struct dsi_pll_28nm { struct clk_hw clk_hw; - int id; - struct platform_device *pdev; - struct msm_dsi_phy *phy; struct pll_28nm_cached_state cached_state; @@ -178,14 +175,14 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; void __iomem *base = pll_28nm->phy->pll_base; bool locked; unsigned int bit_div, byte_div; int max_reads = 1000, timeout_us = 100; u32 val; - DBG("id=%d", pll_28nm->id); + DBG("id=%d", pll_28nm->phy->id); if (unlikely(pll_28nm->phy->pll_on)) return 0; @@ -227,7 +224,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - DBG("id=%d", pll_28nm->id); + DBG("id=%d", pll_28nm->phy->id); if (unlikely(!pll_28nm->phy->pll_on)) return; @@ -368,7 +365,7 @@ static int dsi_28nm_restore_state(struct msm_dsi_phy *phy) ret = dsi_pll_28nm_clk_set_rate(phy->vco_hw, cached_state->vco_rate, 0); if (ret) { - DRM_DEV_ERROR(&pll_28nm->pdev->dev, + DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); return ret; } @@ -392,13 +389,13 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, }; - struct device *dev = &pll_28nm->pdev->dev; + struct device *dev = &pll_28nm->phy->pdev->dev; struct clk_hw *hw; struct clk_bytediv *bytediv; struct clk_init_data bytediv_init = { }; int ret; - DBG("%d", pll_28nm->id); + DBG("%d", pll_28nm->phy->id); bytediv = devm_kzalloc(dev, sizeof(*bytediv), GFP_KERNEL); if (!bytediv) @@ -412,7 +409,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (!clk_name) return -ENOMEM; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); vco_init.name = vco_name; pll_28nm->clk_hw.init = &vco_init; @@ -425,8 +422,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov bytediv->hw.init = &bytediv_init; bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; - snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); + snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id); bytediv_init.name = clk_name; bytediv_init.ops = &clk_bytediv_ops; @@ -440,7 +437,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov return ret; provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw; - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id); /* DIV3 */ hw = devm_clk_hw_register_divider(dev, clk_name, parent_name, 0, pll_28nm->phy->pll_base + @@ -456,7 +453,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) { struct platform_device *pdev = phy->pdev; - int id = phy->id; struct dsi_pll_28nm *pll_28nm; int ret; @@ -467,8 +463,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) if (!pll_28nm) return -ENOMEM; - pll_28nm->pdev = pdev; - pll_28nm->id = id + 1; pll_28nm->phy = phy; ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 8e8cf9e63e8f..4df237ad0eaf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -86,9 +86,6 @@ struct pll_7nm_cached_state { struct dsi_pll_7nm { struct clk_hw clk_hw; - int id; - struct platform_device *pdev; - struct msm_dsi_phy *phy; u64 vco_ref_clk_rate; @@ -320,7 +317,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); - DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate, + DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, parent_rate); pll_7nm->vco_current_rate = rate; @@ -359,7 +356,7 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) timeout_us); if (rc) pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", - pll->id, status); + pll->phy->id, status); return rc; } @@ -435,7 +432,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) /* Check for PLL lock */ rc = dsi_pll_7nm_lock_status(pll_7nm); if (rc) { - pr_err("PLL(%d) lock failed\n", pll_7nm->id); + pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id); goto error; } @@ -519,7 +516,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, vco_rate = pll_freq; DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", - pll_7nm->id, (unsigned long)vco_rate, dec, frac); + pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); return (unsigned long)vco_rate; } @@ -568,7 +565,7 @@ static void dsi_7nm_save_state(struct msm_dsi_phy *phy) cached->pll_mux = cmn_clk_cfg1 & 0x3; DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", - pll_7nm->id, cached->pll_out_div, cached->bit_clk_div, + pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, cached->pix_clk_div, cached->pll_mux); } @@ -595,12 +592,12 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); if (ret) { - DRM_DEV_ERROR(&pll_7nm->pdev->dev, + DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); return ret; } - DBG("DSI PLL%d", pll_7nm->id); + DBG("DSI PLL%d", pll_7nm->phy->id); return 0; } @@ -611,13 +608,13 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ - DBG("DSI PLL%d", pll_7nm->id); + DBG("DSI PLL%d", pll_7nm->phy->id); switch (phy->usecase) { case MSM_DSI_PHY_STANDALONE: break; case MSM_DSI_PHY_MASTER: - pll_7nm->slave = pll_7nm_list[(pll_7nm->id + 1) % DSI_MAX]; + pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; break; case MSM_DSI_PHY_SLAVE: data = 0x1; /* external PLL */ @@ -649,21 +646,21 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_7nm_vco, }; - struct device *dev = &pll_7nm->pdev->dev; + struct device *dev = &pll_7nm->phy->pdev->dev; struct clk_hw *hw; int ret; - DBG("DSI%d", pll_7nm->id); + DBG("DSI%d", pll_7nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id); + snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id); pll_7nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_divider(dev, clk_name, parent, CLK_SET_RATE_PARENT, @@ -675,8 +672,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); /* BIT CLK: DIV_CTRL_3_0 */ hw = devm_clk_hw_register_divider(dev, clk_name, parent, @@ -690,8 +687,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, @@ -703,8 +700,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); @@ -713,8 +710,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4); @@ -723,11 +720,11 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide goto fail; } - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); + snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); + snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); + snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ @@ -740,8 +737,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id); + snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ hw = devm_clk_hw_register_divider(dev, clk_name, parent, @@ -766,7 +763,6 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) { struct platform_device *pdev = phy->pdev; - int id = phy->id; struct dsi_pll_7nm *pll_7nm; int ret; @@ -774,11 +770,9 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) if (!pll_7nm) return -ENOMEM; - DBG("DSI PLL%d", id); + DBG("DSI PLL%d", phy->id); - pll_7nm->pdev = pdev; - pll_7nm->id = id; - pll_7nm_list[id] = pll_7nm; + pll_7nm_list[phy->id] = pll_7nm; spin_lock_init(&pll_7nm->postdiv_lock); From patchwork Wed Mar 24 15:18:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407888 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502627jai; Wed, 24 Mar 2021 08:20:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyo+/5b37KIAhhFHcSzNftzlJctlT5NIk0YDDv+b9GZ+Ssgdh2+DsbbWUEPNraDOvQGGvZO X-Received: by 2002:a17:90a:c257:: with SMTP id d23mr4005350pjx.102.1616599214852; Wed, 24 Mar 2021 08:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599214; cv=none; d=google.com; s=arc-20160816; b=nsdd9+7iHu9TjR/gbUARFHpeTUiAfamjjpDZ2uY0XSLomxF3raq4yrAX9tObfTkFyz V/6OGqG5r6KX9swPufSe/LNpWAwccO1TuEKI+K3322llUtKFonVs6r57XbJxYZleKs28 bwkYla3Toa57P4htN0MRfl7lsWYzXlw65jqIxgnFW2GQExswNlG/AVlYYTU5VDnEo8k6 hiTz8sAFwUKvWEMYToFcpdBFTLfRUKHHNwo/LQgQ6P6zO1BS9ZmvAFzyUKj1OMHHQeeb z54qVFFeKL1iBELTTsh0UXXTh2gAkduOElsCj1aylhP2W0Mq6OXOZrTcTpMZ5jiKNvxQ sLwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=BUpx5IpPm9U97ZQV8AsEzloLMJ2vcDRcGZperQrsSjk=; b=DQPiadA9LLBHjcky7Hjj5z1QHiylMjWIrq6td0QufuHRvSt9PpIqxX2jTD0yUnk0t4 aEhb/N/ipv0Xxw7Cmg3DJyHMSyl4gQh4v4wtB2GASzKS3pi9Shq/GUzauttvXuSvcJ52 vaLJDHRhvTydl+EC0S4Ntb6TgN9BP/oxouW08hNsXPesvCqOCb52W0TaFsoDQTV4K6/i DABr4yJqSXhcayyBzP0FwsdM3zpliPFA5UICyHetOaWGzFuHrgms1mE1GFXLvo5/hHSq 9HRFLbquWnguSqVsL4pTafIoBV12og2yWOLun25rsdOSdf5qDBRVBUYWECtiG/lMmfu/ CRTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=la2rOPJ9; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id g6si2363332pjt.116.2021.03.24.08.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=la2rOPJ9; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 779806EC90; Wed, 24 Mar 2021 15:20:01 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 775596EC99 for ; Wed, 24 Mar 2021 15:19:42 +0000 (UTC) Received: by mail-lj1-x22b.google.com with SMTP id y1so30665285ljm.10 for ; Wed, 24 Mar 2021 08:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mvDwRyrAFXk11XUKvFSTEAxX+9Fv+rhGPpGel9H7AWA=; b=la2rOPJ9FHarTKPRuM8VILRcvwMWKHKYvOvaYzAbKiz6d7VjaCiyBl8x7wOGywqFhZ kC3iuAriPZ4E9ljNsz0ixfjc0vOwgaJs20mPJ7z2gEMfEZjWQuVcX1j4cbcfDueI6NaX Xl4/ppI+4AL1wHxblTQ2aXGoS7UtpYHYJCXzZmXBunrLiThwD0QWS1CKtTU7eII0vpTo qqfkx/mz6NGNqrEX0bAJSLduv/8fa7/+MZCvsalHG3FdmG9dE6rXX+aW67FHYG5XQKiH 8LtkPdG7R4Xit0QY+jsT3oN43qfFNlhBvFmsLZrJHtpBxMzBWH2DtiCg4KBwkLXSvxm3 NUBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mvDwRyrAFXk11XUKvFSTEAxX+9Fv+rhGPpGel9H7AWA=; b=oGLYGbEMFbQ1CGMoRuf9YhbFpnC78YC9wcupABftXRO17I6fqQeK3gMHg4Uri5od2w kyt49C2rhPdudJHesbvf1cBQe0jNiapxj06cpdsgoxCZElxUyik5NTEqSopPxtl8EV3J yPQeiMsn+WLuZw3MtJZ5CdKFOunc59Cz2r2W+0UMAS/dHRExBfke/ya2PxFGpOWWecO9 WXU9dMBsxRS2ch4ynxwoKL2ngGJ36UtazPtqHnMQrCZLVlRxVmHoJyEIQsQhzbq0qmXx Dh4ySlVq3vHBLZCcMmXFL8/lGOO9zCR2Sjb420sL1JE03F/QXt2XEd0smZLgJgN675bE IqsA== X-Gm-Message-State: AOAM5302/6F6UsKRgKWi+RBhkR4KsHUL19zUdwMFKeYDA2IaxS0WM/wr 8BmsyueobBlp7SqAN+v65yr8mQ== X-Received: by 2002:a2e:5159:: with SMTP id b25mr2490107lje.1.1616599180642; Wed, 24 Mar 2021 08:19:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:39 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 26/28] drm/msm/dsi: remove temp data from global pll structure Date: Wed, 24 Mar 2021 18:18:44 +0300 Message-Id: <20210324151846.2774204-27-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The 7nm, 10nm and 14nm drivers would store interim data used during VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data structures to the onstack storage. While we are at it, drop unused/static 'config' data, unused config fields, etc. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 167 ++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 334 +++++++-------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 166 ++++------ 3 files changed, 220 insertions(+), 447 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index b937e77b3c37..1fbb54f4df98 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -36,43 +36,25 @@ */ #define VCO_REF_CLK_RATE 19200000 - -struct dsi_pll_regs { - u32 pll_prop_gain_rate; - u32 pll_lockdet_rate; - u32 decimal_div_start; - u32 frac_div_start_low; - u32 frac_div_start_mid; - u32 frac_div_start_high; - u32 pll_clock_inverters; - u32 ssc_stepsize_low; - u32 ssc_stepsize_high; - u32 ssc_div_per_low; - u32 ssc_div_per_high; - u32 ssc_adjper_low; - u32 ssc_adjper_high; - u32 ssc_control; -}; +#define FRAC_BITS 18 /* v3.0.0 10nm implementation that requires the old timings settings */ #define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0) struct dsi_pll_config { - u32 ref_freq; - bool div_override; - u32 output_div; - bool ignore_frac; - bool disable_prescaler; bool enable_ssc; bool ssc_center; - u32 dec_bits; - u32 frac_bits; - u32 lock_timer; u32 ssc_freq; u32 ssc_offset; u32 ssc_adj_per; - u32 thresh_cycles; - u32 refclk_cycles; + + /* out */ + u32 pll_prop_gain_rate; + u32 decimal_div_start; + u32 frac_div_start; + u32 pll_clock_inverters; + u32 ssc_stepsize; + u32 ssc_div_per; }; struct pll_10nm_cached_state { @@ -88,15 +70,11 @@ struct dsi_pll_10nm { struct msm_dsi_phy *phy; - u64 vco_ref_clk_rate; u64 vco_current_rate; /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - struct dsi_pll_config pll_configuration; - struct dsi_pll_regs reg_setup; - struct pll_10nm_cached_state cached_state; struct dsi_pll_10nm *slave; @@ -110,34 +88,19 @@ struct dsi_pll_10nm { */ static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX]; -static void dsi_pll_setup_config(struct dsi_pll_10nm *pll) +static void dsi_pll_setup_config(struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - - config->ref_freq = pll->vco_ref_clk_rate; - config->output_div = 1; - config->dec_bits = 8; - config->frac_bits = 18; - config->lock_timer = 64; config->ssc_freq = 31500; config->ssc_offset = 5000; config->ssc_adj_per = 2; - config->thresh_cycles = 32; - config->refclk_cycles = 256; - - config->div_override = false; - config->ignore_frac = false; - config->disable_prescaler = false; config->enable_ssc = false; - config->ssc_center = 0; + config->ssc_center = false; } -static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) +static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u64 fref = pll->vco_ref_clk_rate; + u64 fref = VCO_REF_CLK_RATE; u64 pll_freq; u64 divider; u64 dec, dec_multiple; @@ -146,40 +109,32 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) pll_freq = pll->vco_current_rate; - if (config->disable_prescaler) - divider = fref; - else - divider = fref * 2; + divider = fref * 2; - multiplier = 1 << config->frac_bits; + multiplier = 1 << FRAC_BITS; dec_multiple = div_u64(pll_freq * multiplier, divider); dec = div_u64_rem(dec_multiple, multiplier, &frac); if (pll_freq <= 1900000000UL) - regs->pll_prop_gain_rate = 8; + config->pll_prop_gain_rate = 8; else if (pll_freq <= 3000000000UL) - regs->pll_prop_gain_rate = 10; + config->pll_prop_gain_rate = 10; else - regs->pll_prop_gain_rate = 12; + config->pll_prop_gain_rate = 12; if (pll_freq < 1100000000UL) - regs->pll_clock_inverters = 8; + config->pll_clock_inverters = 8; else - regs->pll_clock_inverters = 0; + config->pll_clock_inverters = 0; - regs->pll_lockdet_rate = config->lock_timer; - regs->decimal_div_start = dec; - regs->frac_div_start_low = (frac & 0xff); - regs->frac_div_start_mid = (frac & 0xff00) >> 8; - regs->frac_div_start_high = (frac & 0x30000) >> 16; + config->decimal_div_start = dec; + config->frac_div_start = frac; } #define SSC_CENTER BIT(0) #define SSC_EN BIT(1) -static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) +static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; u32 ssc_per; u32 ssc_mod; u64 ssc_step_size; @@ -190,58 +145,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) return; } - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); ssc_per -= ssc_mod; - frac = regs->frac_div_start_low | - (regs->frac_div_start_mid << 8) | - (regs->frac_div_start_high << 16); - ssc_step_size = regs->decimal_div_start; - ssc_step_size *= (1 << config->frac_bits); + frac = config->frac_div_start; + ssc_step_size = config->decimal_div_start; + ssc_step_size *= (1 << FRAC_BITS); ssc_step_size += frac; ssc_step_size *= config->ssc_offset; ssc_step_size *= (config->ssc_adj_per + 1); ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); - regs->ssc_div_per_low = ssc_per & 0xFF; - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; - - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; + config->ssc_div_per = ssc_per; + config->ssc_stepsize = ssc_step_size; pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", - regs->decimal_div_start, frac, config->frac_bits); + config->decimal_div_start, frac, FRAC_BITS); pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", ssc_per, (u32)ssc_step_size, config->ssc_adj_per); } -static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) +static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) { void __iomem *base = pll->phy->pll_base; - struct dsi_pll_regs *regs = &pll->reg_setup; - if (pll->pll_configuration.enable_ssc) { + if (config->enable_ssc) { pr_debug("SSC is enabled\n"); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - regs->ssc_stepsize_low); + config->ssc_stepsize & 0xff); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - regs->ssc_stepsize_high); + config->ssc_stepsize >> 8); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, - regs->ssc_div_per_low); + config->ssc_div_per & 0xff); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - regs->ssc_div_per_high); + config->ssc_div_per >> 8); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, - regs->ssc_adjper_low); + config->ssc_adj_per & 0xff); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, - regs->ssc_adjper_high); + config->ssc_adj_per >> 8); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, - SSC_EN | regs->ssc_control); + SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); } } @@ -271,50 +217,48 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); } -static void dsi_pll_commit(struct dsi_pll_10nm *pll) +static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) { void __iomem *base = pll->phy->pll_base; - struct dsi_pll_regs *reg = &pll->reg_setup; dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, - reg->decimal_div_start); + config->decimal_div_start); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, - reg->frac_div_start_low); + config->frac_div_start & 0xff); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, - reg->frac_div_start_mid); + (config->frac_div_start & 0xff00) >> 8); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, - reg->frac_div_start_high); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, - reg->pll_lockdet_rate); + (config->frac_div_start & 0x30000) >> 16); + dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, - reg->pll_clock_inverters); + config->pll_clock_inverters); } static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); + struct dsi_pll_config config; DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate, parent_rate); pll_10nm->vco_current_rate = rate; - pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - dsi_pll_setup_config(pll_10nm); + dsi_pll_setup_config(&config); - dsi_pll_calc_dec_frac(pll_10nm); + dsi_pll_calc_dec_frac(pll_10nm, &config); - dsi_pll_calc_ssc(pll_10nm); + dsi_pll_calc_ssc(pll_10nm, &config); - dsi_pll_commit(pll_10nm); + dsi_pll_commit(pll_10nm, &config); dsi_pll_config_hzindep_reg(pll_10nm); - dsi_pll_ssc_commit(pll_10nm); + dsi_pll_ssc_commit(pll_10nm, &config); /* flush, ensure all register writes are done*/ wmb(); @@ -461,9 +405,8 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); - struct dsi_pll_config *config = &pll_10nm->pll_configuration; void __iomem *base = pll_10nm->phy->pll_base; - u64 ref_clk = pll_10nm->vco_ref_clk_rate; + u64 ref_clk = VCO_REF_CLK_RATE; u64 vco_rate = 0x0; u64 multiplier; u32 frac; @@ -483,7 +426,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, * TODO: * 1. Assumes prescaler is disabled */ - multiplier = 1 << config->frac_bits; + multiplier = 1 << FRAC_BITS; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += div_u64(tmp64, multiplier); @@ -565,7 +508,7 @@ static int dsi_10nm_restore_state(struct msm_dsi_phy *phy) val |= cached->pll_mux; dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate); + ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, VCO_REF_CLK_RATE); if (ret) { DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 8b4865c5796d..d08ad0c632b4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -37,51 +37,19 @@ #define VCO_MIN_RATE 1300000000UL #define VCO_MAX_RATE 2600000000UL -#define DSI_PLL_DEFAULT_VCO_POSTDIV 1 +struct dsi_pll_config { + u64 vco_current_rate; -struct dsi_pll_input { - u32 fref; /* reference clk */ - u32 fdata; /* bit clock rate */ - u32 dsiclk_sel; /* Mux configuration (see diagram) */ u32 ssc_en; /* SSC enable/disable */ - u32 ldo_en; /* fixed params */ - u32 refclk_dbler_en; - u32 vco_measure_time; - u32 kvco_measure_time; - u32 bandgap_timer; - u32 pll_wakeup_timer; u32 plllock_cnt; - u32 plllock_rng; u32 ssc_center; u32 ssc_adj_period; u32 ssc_spread; u32 ssc_freq; - u32 pll_ie_trim; - u32 pll_ip_trim; - u32 pll_iptat_trim; - u32 pll_cpcset_cur; - u32 pll_cpmset_cur; - - u32 pll_icpmset; - u32 pll_icpcset; - - u32 pll_icpmset_p; - u32 pll_icpmset_m; - - u32 pll_icpcset_p; - u32 pll_icpcset_m; - - u32 pll_lpf_res1; - u32 pll_lpf_cap1; - u32 pll_lpf_cap2; - u32 pll_c3ctrl; - u32 pll_r3ctrl; -}; -struct dsi_pll_output { - u32 pll_txclk_en; + /* calculated */ u32 dec_start; u32 div_frac_start; u32 ssc_period; @@ -91,19 +59,6 @@ struct dsi_pll_output { u32 pll_vco_count; u32 pll_kvco_div_ref; u32 pll_kvco_count; - u32 pll_misc1; - u32 pll_lpf2_postdiv; - u32 pll_resetsm_cntrl; - u32 pll_resetsm_cntrl2; - u32 pll_resetsm_cntrl5; - u32 pll_kvco_code; - - u32 cmn_clk_cfg0; - u32 cmn_clk_cfg1; - u32 cmn_ldo_cntrl; - - u32 pll_postdiv; - u32 fcvo; }; struct pll_14nm_cached_state { @@ -117,15 +72,9 @@ struct dsi_pll_14nm { struct msm_dsi_phy *phy; - struct dsi_pll_input in; - struct dsi_pll_output out; - /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - u64 vco_current_rate; - u64 vco_ref_clk_rate; - struct pll_14nm_cached_state cached_state; struct dsi_pll_14nm *slave; @@ -195,78 +144,50 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, return pll_locked; } -static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) +static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf) { - pll->in.fref = pll->vco_ref_clk_rate; - pll->in.fdata = 0; - pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ - pll->in.ldo_en = 0; /* disabled for now */ - /* fixed input */ - pll->in.refclk_dbler_en = 0; - pll->in.vco_measure_time = 5; - pll->in.kvco_measure_time = 5; - pll->in.bandgap_timer = 4; - pll->in.pll_wakeup_timer = 5; - pll->in.plllock_cnt = 1; - pll->in.plllock_rng = 0; + pconf->plllock_cnt = 1; /* * SSC is enabled by default. We might need DT props for configuring * some SSC params like PPM and center/down spread etc. */ - pll->in.ssc_en = 1; - pll->in.ssc_center = 0; /* down spread by default */ - pll->in.ssc_spread = 5; /* PPM / 1000 */ - pll->in.ssc_freq = 31500; /* default recommended */ - pll->in.ssc_adj_period = 37; - - pll->in.pll_ie_trim = 4; - pll->in.pll_ip_trim = 4; - pll->in.pll_cpcset_cur = 1; - pll->in.pll_cpmset_cur = 1; - pll->in.pll_icpmset = 4; - pll->in.pll_icpcset = 4; - pll->in.pll_icpmset_p = 0; - pll->in.pll_icpmset_m = 0; - pll->in.pll_icpcset_p = 0; - pll->in.pll_icpcset_m = 0; - pll->in.pll_lpf_res1 = 3; - pll->in.pll_lpf_cap1 = 11; - pll->in.pll_lpf_cap2 = 1; - pll->in.pll_iptat_trim = 7; - pll->in.pll_c3ctrl = 2; - pll->in.pll_r3ctrl = 1; + pconf->ssc_en = 1; + pconf->ssc_center = 0; /* down spread by default */ + pconf->ssc_spread = 5; /* PPM / 1000 */ + pconf->ssc_freq = 31500; /* default recommended */ + pconf->ssc_adj_period = 37; } #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) -static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) +static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) { u32 period, ssc_period; u32 ref, rem; u64 step_size; - DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate); + DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); - ssc_period = pll->in.ssc_freq / 500; - period = (u32)pll->vco_ref_clk_rate / 1000; + ssc_period = pconf->ssc_freq / 500; + period = (u32)VCO_REF_CLK_RATE / 1000; ssc_period = CEIL(period, ssc_period); ssc_period -= 1; - pll->out.ssc_period = ssc_period; + pconf->ssc_period = ssc_period; - DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq, - pll->in.ssc_spread, pll->out.ssc_period); + DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq, + pconf->ssc_spread, pconf->ssc_period); - step_size = (u32)pll->vco_current_rate; - ref = pll->vco_ref_clk_rate; + step_size = (u32)pconf->vco_current_rate; + ref = VCO_REF_CLK_RATE; ref /= 1000; step_size = div_u64(step_size, ref); step_size <<= 20; step_size = div_u64(step_size, 1000); - step_size *= pll->in.ssc_spread; + step_size *= pconf->ssc_spread; step_size = div_u64(step_size, 1000); - step_size *= (pll->in.ssc_adj_period + 1); + step_size *= (pconf->ssc_adj_period + 1); rem = 0; step_size = div_u64_rem(step_size, ssc_period + 1, &rem); @@ -277,18 +198,16 @@ static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) step_size &= 0x0ffff; /* take lower 16 bits */ - pll->out.ssc_step_size = step_size; + pconf->ssc_step_size = step_size; } -static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) +static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) { - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; u64 multiplier = BIT(20); u64 dec_start_multiple, dec_start, pll_comp_val; u32 duration, div_frac_start; - u64 vco_clk_rate = pll->vco_current_rate; - u64 fref = pll->vco_ref_clk_rate; + u64 vco_clk_rate = pconf->vco_current_rate; + u64 fref = VCO_REF_CLK_RATE; DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); @@ -297,14 +216,14 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) dec_start = div_u64(dec_start_multiple, multiplier); - pout->dec_start = (u32)dec_start; - pout->div_frac_start = div_frac_start; + pconf->dec_start = (u32)dec_start; + pconf->div_frac_start = div_frac_start; - if (pin->plllock_cnt == 0) + if (pconf->plllock_cnt == 0) duration = 1024; - else if (pin->plllock_cnt == 1) + else if (pconf->plllock_cnt == 1) duration = 256; - else if (pin->plllock_cnt == 2) + else if (pconf->plllock_cnt == 2) duration = 128; else duration = 32; @@ -313,10 +232,7 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) pll_comp_val = div_u64(pll_comp_val, multiplier); do_div(pll_comp_val, 10); - pout->plllock_cmp = (u32)pll_comp_val; - - pout->pll_txclk_en = 1; - pout->cmn_ldo_cntrl = 0x3c; + pconf->plllock_cmp = (u32)pll_comp_val; } static u32 pll_14nm_kvco_slop(u32 vrate) @@ -333,74 +249,66 @@ static u32 pll_14nm_kvco_slop(u32 vrate) return slop; } -static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) +static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) { - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; - u64 vco_clk_rate = pll->vco_current_rate; - u64 fref = pll->vco_ref_clk_rate; + u64 vco_clk_rate = pconf->vco_current_rate; + u64 fref = VCO_REF_CLK_RATE; + u32 vco_measure_time = 5; + u32 kvco_measure_time = 5; u64 data; u32 cnt; - data = fref * pin->vco_measure_time; + data = fref * vco_measure_time; do_div(data, 1000000); data &= 0x03ff; /* 10 bits */ data -= 2; - pout->pll_vco_div_ref = data; + pconf->pll_vco_div_ref = data; data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ - data *= pin->vco_measure_time; + data *= vco_measure_time; do_div(data, 10); - pout->pll_vco_count = data; + pconf->pll_vco_count = data; - data = fref * pin->kvco_measure_time; + data = fref * kvco_measure_time; do_div(data, 1000000); data &= 0x03ff; /* 10 bits */ data -= 1; - pout->pll_kvco_div_ref = data; + pconf->pll_kvco_div_ref = data; cnt = pll_14nm_kvco_slop(vco_clk_rate); cnt *= 2; cnt /= 100; - cnt *= pin->kvco_measure_time; - pout->pll_kvco_count = cnt; - - pout->pll_misc1 = 16; - pout->pll_resetsm_cntrl = 48; - pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3; - pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer; - pout->pll_kvco_code = 0; + cnt *= kvco_measure_time; + pconf->pll_kvco_count = cnt; } -static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) +static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) { void __iomem *base = pll->phy->pll_base; - struct dsi_pll_input *pin = &pll->in; - struct dsi_pll_output *pout = &pll->out; u8 data; - data = pin->ssc_adj_period; + data = pconf->ssc_adj_period; data &= 0x0ff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); - data = (pin->ssc_adj_period >> 8); + data = (pconf->ssc_adj_period >> 8); data &= 0x03; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); - data = pout->ssc_period; + data = pconf->ssc_period; data &= 0x0ff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); - data = (pout->ssc_period >> 8); + data = (pconf->ssc_period >> 8); data &= 0x0ff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); - data = pout->ssc_step_size; + data = pconf->ssc_step_size; data &= 0x0ff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); - data = (pout->ssc_step_size >> 8); + data = (pconf->ssc_step_size >> 8); data &= 0x0ff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); - data = (pin->ssc_center & 0x01); + data = (pconf->ssc_center & 0x01); data <<= 1; data |= 0x01; /* enable */ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); @@ -409,8 +317,7 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) } static void pll_db_commit_common(struct dsi_pll_14nm *pll, - struct dsi_pll_input *pin, - struct dsi_pll_output *pout) + struct dsi_pll_config *pconf) { void __iomem *base = pll->phy->pll_base; u8 data; @@ -419,55 +326,41 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, data = 0; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); - data = pout->pll_txclk_en; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1); - data = pout->pll_resetsm_cntrl; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); - data = pout->pll_resetsm_cntrl2; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); - data = pout->pll_resetsm_cntrl5; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */ + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */ - data = pout->pll_vco_div_ref & 0xff; + data = pconf->pll_vco_div_ref & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); - data = (pout->pll_vco_div_ref >> 8) & 0x3; + data = (pconf->pll_vco_div_ref >> 8) & 0x3; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); - data = pout->pll_kvco_div_ref & 0xff; + data = pconf->pll_kvco_div_ref & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); - data = (pout->pll_kvco_div_ref >> 8) & 0x3; + data = (pconf->pll_kvco_div_ref >> 8) & 0x3; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); - data = pout->pll_misc1; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16); - data = pin->pll_ie_trim; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4); - data = pin->pll_ip_trim; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4); - data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1); - data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0); - data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0); - data = pin->pll_icpmset << 3 | pin->pll_icpcset; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4); - data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11); - data = pin->pll_iptat_trim; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7); - data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2); } static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) @@ -488,8 +381,7 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) } static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, - struct dsi_pll_input *pin, - struct dsi_pll_output *pout) + struct dsi_pll_config *pconf) { void __iomem *base = pll->phy->pll_base; void __iomem *cmn_base = pll->phy->base; @@ -497,57 +389,64 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, DBG("DSI%d PLL", pll->phy->id); - data = pout->cmn_ldo_cntrl; - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c); - pll_db_commit_common(pll, pin, pout); + pll_db_commit_common(pll, pconf); pll_14nm_software_reset(pll); - data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */ - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); + /* Use the /2 path in Mux */ + dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1); data = 0xff; /* data, clk, pll normal operation */ dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); /* configure the frequency dependent pll registers */ - data = pout->dec_start; + data = pconf->dec_start; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); - data = pout->div_frac_start & 0xff; + data = pconf->div_frac_start & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); - data = (pout->div_frac_start >> 8) & 0xff; + data = (pconf->div_frac_start >> 8) & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); - data = (pout->div_frac_start >> 16) & 0xf; + data = (pconf->div_frac_start >> 16) & 0xf; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); - data = pout->plllock_cmp & 0xff; + data = pconf->plllock_cmp & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); - data = (pout->plllock_cmp >> 8) & 0xff; + data = (pconf->plllock_cmp >> 8) & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); - data = (pout->plllock_cmp >> 16) & 0x3; + data = (pconf->plllock_cmp >> 16) & 0x3; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); - data = pin->plllock_cnt << 1 | pin->plllock_rng << 3; + data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */ dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); - data = pout->pll_vco_count & 0xff; + data = pconf->pll_vco_count & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); - data = (pout->pll_vco_count >> 8) & 0xff; + data = (pconf->pll_vco_count >> 8) & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); - data = pout->pll_kvco_count & 0xff; + data = pconf->pll_kvco_count & 0xff; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); - data = (pout->pll_kvco_count >> 8) & 0x3; + data = (pconf->pll_kvco_count >> 8) & 0x3; dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); - data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); + /* + * High nibble configures the post divider internal to the VCO. It's + * fixed to divide by 1 for now. + * + * 0: divided by 1 + * 1: divided by 2 + * 2: divided by 4 + * 3: divided by 8 + */ + dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3); - if (pin->ssc_en) - pll_db_commit_ssc(pll); + if (pconf->ssc_en) + pll_db_commit_ssc(pll, pconf); wmb(); /* make sure register committed */ } @@ -559,35 +458,20 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); - struct dsi_pll_input *pin = &pll_14nm->in; - struct dsi_pll_output *pout = &pll_14nm->out; + struct dsi_pll_config conf; DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate, parent_rate); - pll_14nm->vco_current_rate = rate; - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - - dsi_pll_14nm_input_init(pll_14nm); - - /* - * This configures the post divider internal to the VCO. It's - * fixed to divide by 1 for now. - * - * tx_band = pll_postdiv. - * 0: divided by 1 - * 1: divided by 2 - * 2: divided by 4 - * 3: divided by 8 - */ - pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV; + dsi_pll_14nm_config_init(&conf); + conf.vco_current_rate = rate; - pll_14nm_dec_frac_calc(pll_14nm); + pll_14nm_dec_frac_calc(pll_14nm, &conf); - if (pin->ssc_en) - pll_14nm_ssc_calc(pll_14nm); + if (conf.ssc_en) + pll_14nm_ssc_calc(pll_14nm, &conf); - pll_14nm_calc_vco_count(pll_14nm); + pll_14nm_calc_vco_count(pll_14nm, &conf); /* commit the slave DSI PLL registers if we're master. Note that we * don't lock the slave PLL. We just ensure that the PLL/PHY registers @@ -596,10 +480,10 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; - pll_db_commit_14nm(pll_14nm_slave, pin, pout); + pll_db_commit_14nm(pll_14nm_slave, &conf); } - pll_db_commit_14nm(pll_14nm, pin, pout); + pll_db_commit_14nm(pll_14nm, &conf); return 0; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 4df237ad0eaf..ce6ae2fba993 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -36,43 +36,24 @@ */ #define VCO_REF_CLK_RATE 19200000 - -struct dsi_pll_regs { - u32 pll_prop_gain_rate; - u32 pll_lockdet_rate; - u32 decimal_div_start; - u32 frac_div_start_low; - u32 frac_div_start_mid; - u32 frac_div_start_high; - u32 pll_clock_inverters; - u32 ssc_stepsize_low; - u32 ssc_stepsize_high; - u32 ssc_div_per_low; - u32 ssc_div_per_high; - u32 ssc_adjper_low; - u32 ssc_adjper_high; - u32 ssc_control; -}; +#define FRAC_BITS 18 /* Hardware is V4.1 */ #define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) struct dsi_pll_config { - u32 ref_freq; - bool div_override; - u32 output_div; - bool ignore_frac; - bool disable_prescaler; bool enable_ssc; bool ssc_center; - u32 dec_bits; - u32 frac_bits; - u32 lock_timer; u32 ssc_freq; u32 ssc_offset; u32 ssc_adj_per; - u32 thresh_cycles; - u32 refclk_cycles; + + /* out */ + u32 decimal_div_start; + u32 frac_div_start; + u32 pll_clock_inverters; + u32 ssc_stepsize; + u32 ssc_div_per; }; struct pll_7nm_cached_state { @@ -88,15 +69,11 @@ struct dsi_pll_7nm { struct msm_dsi_phy *phy; - u64 vco_ref_clk_rate; u64 vco_current_rate; /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - struct dsi_pll_config pll_configuration; - struct dsi_pll_regs reg_setup; - struct pll_7nm_cached_state cached_state; struct dsi_pll_7nm *slave; @@ -110,35 +87,20 @@ struct dsi_pll_7nm { */ static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; -static void dsi_pll_setup_config(struct dsi_pll_7nm *pll) +static void dsi_pll_setup_config(struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - - config->ref_freq = pll->vco_ref_clk_rate; - config->output_div = 1; - config->dec_bits = 8; - config->frac_bits = 18; - config->lock_timer = 64; config->ssc_freq = 31500; config->ssc_offset = 4800; config->ssc_adj_per = 2; - config->thresh_cycles = 32; - config->refclk_cycles = 256; - - config->div_override = false; - config->ignore_frac = false; - config->disable_prescaler = false; /* TODO: ssc enable */ config->enable_ssc = false; config->ssc_center = 0; } -static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) +static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; - u64 fref = pll->vco_ref_clk_rate; + u64 fref = VCO_REF_CLK_RATE; u64 pll_freq; u64 divider; u64 dec, dec_multiple; @@ -147,42 +109,34 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) pll_freq = pll->vco_current_rate; - if (config->disable_prescaler) - divider = fref; - else - divider = fref * 2; + divider = fref * 2; - multiplier = 1 << config->frac_bits; + multiplier = 1 << FRAC_BITS; dec_multiple = div_u64(pll_freq * multiplier, divider); div_u64_rem(dec_multiple, multiplier, &frac); dec = div_u64(dec_multiple, multiplier); if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) - regs->pll_clock_inverters = 0x28; + config->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) - regs->pll_clock_inverters = 0xa0; + config->pll_clock_inverters = 0xa0; else if (pll_freq <= 2500000000ULL) - regs->pll_clock_inverters = 0x20; + config->pll_clock_inverters = 0x20; else if (pll_freq <= 3020000000ULL) - regs->pll_clock_inverters = 0x00; + config->pll_clock_inverters = 0x00; else - regs->pll_clock_inverters = 0x40; + config->pll_clock_inverters = 0x40; - regs->pll_lockdet_rate = config->lock_timer; - regs->decimal_div_start = dec; - regs->frac_div_start_low = (frac & 0xff); - regs->frac_div_start_mid = (frac & 0xff00) >> 8; - regs->frac_div_start_high = (frac & 0x30000) >> 16; + config->decimal_div_start = dec; + config->frac_div_start = frac; } #define SSC_CENTER BIT(0) #define SSC_EN BIT(1) -static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) +static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { - struct dsi_pll_config *config = &pll->pll_configuration; - struct dsi_pll_regs *regs = &pll->reg_setup; u32 ssc_per; u32 ssc_mod; u64 ssc_step_size; @@ -193,58 +147,49 @@ static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) return; } - ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; + ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); ssc_per -= ssc_mod; - frac = regs->frac_div_start_low | - (regs->frac_div_start_mid << 8) | - (regs->frac_div_start_high << 16); - ssc_step_size = regs->decimal_div_start; - ssc_step_size *= (1 << config->frac_bits); + frac = config->frac_div_start; + ssc_step_size = config->decimal_div_start; + ssc_step_size *= (1 << FRAC_BITS); ssc_step_size += frac; ssc_step_size *= config->ssc_offset; ssc_step_size *= (config->ssc_adj_per + 1); ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); - regs->ssc_div_per_low = ssc_per & 0xFF; - regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; - regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); - regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); - regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; - regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; - - regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; + config->ssc_div_per = ssc_per; + config->ssc_stepsize = ssc_step_size; pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", - regs->decimal_div_start, frac, config->frac_bits); + config->decimal_div_start, frac, FRAC_BITS); pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", ssc_per, (u32)ssc_step_size, config->ssc_adj_per); } -static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) +static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { void __iomem *base = pll->phy->pll_base; - struct dsi_pll_regs *regs = &pll->reg_setup; - if (pll->pll_configuration.enable_ssc) { + if (config->enable_ssc) { pr_debug("SSC is enabled\n"); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - regs->ssc_stepsize_low); + config->ssc_stepsize & 0xff); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - regs->ssc_stepsize_high); + config->ssc_stepsize >> 8); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, - regs->ssc_div_per_low); + config->ssc_div_per & 0xff); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - regs->ssc_div_per_high); + config->ssc_div_per >> 8); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, - regs->ssc_adjper_low); + config->ssc_adj_per & 0xff); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, - regs->ssc_adjper_high); + config->ssc_adj_per >> 8); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, - SSC_EN | regs->ssc_control); + SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); } } @@ -296,44 +241,46 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) } } -static void dsi_pll_commit(struct dsi_pll_7nm *pll) +static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { void __iomem *base = pll->phy->pll_base; - struct dsi_pll_regs *reg = &pll->reg_setup; dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, + config->frac_div_start & 0xff); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, + (config->frac_div_start & 0xff00) >> 8); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, + (config->frac_div_start & 0x30000) >> 16); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters); } static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); + struct dsi_pll_config config; DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, parent_rate); pll_7nm->vco_current_rate = rate; - pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; - dsi_pll_setup_config(pll_7nm); + dsi_pll_setup_config(&config); - dsi_pll_calc_dec_frac(pll_7nm); + dsi_pll_calc_dec_frac(pll_7nm, &config); - dsi_pll_calc_ssc(pll_7nm); + dsi_pll_calc_ssc(pll_7nm, &config); - dsi_pll_commit(pll_7nm); + dsi_pll_commit(pll_7nm, &config); dsi_pll_config_hzindep_reg(pll_7nm); - dsi_pll_ssc_commit(pll_7nm); + dsi_pll_ssc_commit(pll_7nm, &config); /* flush, ensure all register writes are done*/ wmb(); @@ -486,9 +433,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); - struct dsi_pll_config *config = &pll_7nm->pll_configuration; void __iomem *base = pll_7nm->phy->pll_base; - u64 ref_clk = pll_7nm->vco_ref_clk_rate; + u64 ref_clk = VCO_REF_CLK_RATE; u64 vco_rate = 0x0; u64 multiplier; u32 frac; @@ -508,7 +454,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, * TODO: * 1. Assumes prescaler is disabled */ - multiplier = 1 << config->frac_bits; + multiplier = 1 << FRAC_BITS; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += div_u64(tmp64, multiplier); @@ -590,7 +536,7 @@ static int dsi_7nm_restore_state(struct msm_dsi_phy *phy) val |= cached->pll_mux; dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); - ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate); + ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, VCO_REF_CLK_RATE); if (ret) { DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev, "restore vco rate failed. ret=%d\n", ret); From patchwork Wed Mar 24 15:18:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407886 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502537jai; Wed, 24 Mar 2021 08:20:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwcW0etopMOdhlg1mwcgsg/alHqEYA2F4xqGMsHu0KJ0ypo7PGqoQYCsmOm3WvKn190+98 X-Received: by 2002:a17:90a:be0e:: with SMTP id a14mr3791313pjs.131.1616599209419; Wed, 24 Mar 2021 08:20:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599209; cv=none; d=google.com; s=arc-20160816; b=f94MRmbtYFKhqAPeBe4xrlkxnQFrCXrZINHlK5DULIAQOiGlaDB0BEf+dAD7lkDjRR wC2M1/K3TLsdAcuWx8FMTb+QLmO/aoRyUvF5mQ0tnkSjMyaRw657ut+mcSU/hO/aEjPZ N5JepQFFlEJ8X452R7qAQPivtvUJph2UUKTQASp4Mfd38/sFgqj1OPZGUVAxNSr3FX1F GUtbMQIQvA+A9MItKOguQUMWTvH4exIbqJgxYgjdJH7xWcLammtl8ONZK8VuBUqVXE06 yXIILGwEVF8mP7nmnqw1NvZLEz6DT3PkEs+bTfW5pRC1qVgbdZ1w4w+Nhw0Lkq0mizu5 oGFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=0ABjQ4fkaTusvneRnRNuG6+3DLa3AGubIpX0vU3mj9o=; b=FiLUkydcAoAFQ02UwC2bTvoxV6pRsqyz1XnsrcvsgaUe7F3M2BsWLEUp1UCiBorR7a yGndPxoIAOwHKGrQVuGCiOg/KKIwRYdLq+0wYzYYBPfrG6iEDPJ8hurO2AhfiBhpTaA8 dBxeyl1KX5cRpkt8y3LOFT4czakcgNswln1tx/M7CyfKiFovqbqHQerlCz0ssI0U7ZJ+ REKsUPQivhPDPvLDUXyHLrfdDFyV7lJrhY9TwiEGpkpCJVB/PWyTyl+O3kmXcLD49hkg Ii/Lg7bC3mUi1mDLAn1Lc/A1feeQ0Yexd366QGgoKvnuUwMvgyVG36ElYN2y1Mp6MRZ1 1UEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cHM6frft; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id x11si2506395pgj.559.2021.03.24.08.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cHM6frft; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD1986EC99; Wed, 24 Mar 2021 15:19:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by gabe.freedesktop.org (Postfix) with ESMTPS id 674BD6EC6F for ; Wed, 24 Mar 2021 15:19:43 +0000 (UTC) Received: by mail-lf1-x130.google.com with SMTP id q29so32368988lfb.4 for ; Wed, 24 Mar 2021 08:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OoyKU1h/oJDC00eudzBASZPAkR4D3lrK9KAbb6lplKk=; b=cHM6frftyuBwYpTJSGuZP7c26UtCzMSfFvwRCp7/SrfuqZmjcggjZ9qJPJuaJA6egA Tp99G38yvdjKsoMKCshAz4dTTOneqrD1durNaD0nswm8SAe0ElSeBDgmVc/3U/kBuUd2 Ozd9g2Qu9acq6vF1bUbp93f6ROhj/uRbAQYIu4MqRzzOBCqIYGFO3DUQH0zGEFuxV5kM iXt8qJ19gQg9yuccciYLcR0BU8k7UR0Y8nxB7gGOnSDOSIvI+NeZ+8QhX+Jb0IazVAZb sN8JlpS03/zz9pMw40tflg9Hre49ZafXZRNljB334aoJpLXsof+ZWfUvf25xE2sPNTRG L5cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OoyKU1h/oJDC00eudzBASZPAkR4D3lrK9KAbb6lplKk=; b=VtUndM8PTY692kWxlQdkVjqHRqB80Dt8KcM50GorvrCgXkxL241f7m2jLyi6YkH/YA YKFy5FRtwc2q9YDXb1rYLjDRUf9yOYZZAESTjddkLkojjWrD68iNlmqXp1aGFUkuy8uz W3MoZbzfPk8O500tizPgHHp5MAOFrUjmlcr29x8TFrrVoZhHVPO9mhrvyGXFAZvd8kHD +qnI0q1gNMRy8XAm/ISyKegCvb1pDAxOnpdgAx1g2LTcn4063/leT0ggVrsSTwzPabAB r6BPkg321iJDZgtRq/w5d92Hc9YjDrr3RocnxGsL3pIJAMaeNmJojTMDLkNfn8/cuNj7 3rvQ== X-Gm-Message-State: AOAM533FeXBPPPf5cgcJFnWMC3h+gPk/EsgL1DsaGVqHWcMzvQ9ucdZo aQH01/+JSBMSHXYurlbcsiZUTg== X-Received: by 2002:a05:6512:2097:: with SMTP id t23mr2109899lfr.21.1616599181748; Wed, 24 Mar 2021 08:19:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:41 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 27/28] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Date: Wed, 24 Mar 2021 18:18:45 +0300 Message-Id: <20210324151846.2774204-28-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17 ----------------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 -------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 13 +++++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 +++++++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 13 +++++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 -- 8 files changed, 21 insertions(+), 46 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 4aeedcbbda32..8f7726bb598c 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -461,23 +461,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, return 0; } -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, - u32 bit_mask) -{ - int phy_id = phy->id; - u32 val; - - if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX)) - return; - - val = dsi_phy_read(phy->base + reg); - - if (phy->cfg->src_pll_truthtable[phy_id][pll_id]) - dsi_phy_write(phy->base + reg, val | bit_mask); - else - dsi_phy_write(phy->base + reg, val & (~bit_mask)); -} - static int dsi_phy_regulator_init(struct msm_dsi_phy *phy) { struct regulator_bulk_data *s = phy->supplies; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8e828c5ca8f4..3b207cf9f6b4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg { unsigned long min_pll_rate; unsigned long max_pll_rate; - /* - * Each cell {phy_id, pll_id} of the truth table indicates - * if the source PLL selection bit should be set for each PHY. - * Fill default H/W values in illegal cells, eg. cell {0, 1}. - */ - bool src_pll_truthtable[DSI_MAX][DSI_MAX]; const resource_size_t io_start[DSI_MAX]; const int num_dsi_phy; const int quirks; @@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, - u32 bit_mask); #endif /* __DSI_PHY_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 1fbb54f4df98..04535ccd11ef 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -919,7 +919,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, @@ -941,7 +940,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index d08ad0c632b4..7a87bed71e36 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -947,6 +947,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, int ret; void __iomem *base = phy->base; void __iomem *lane_base = phy->lane_base; + u32 glbl_test_ctrl; if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { DRM_DEV_ERROR(&phy->pdev->dev, @@ -994,10 +995,12 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, udelay(100); dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); - msm_dsi_phy_set_src_pll(phy, src_pll_id, - REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, - DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL); - + glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); + if (phy->id == DSI_1 && src_pll_id == DSI_0) + glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; + else + glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; + dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl); ret = dsi_14nm_set_usecase(phy); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", @@ -1021,7 +1024,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, @@ -1043,7 +1045,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index 5e73f811d645..f5b88c85a8fc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, int i; void __iomem *base = phy->base; u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00}; + u32 val; DBG(""); @@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); - msm_dsi_phy_set_src_pll(phy, src_pll_id, - REG_DSI_20nm_PHY_GLBL_TEST_CTRL, - DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL); + val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); + if (src_pll_id == DSI_1) + val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + else + val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val); for (i = 0; i < 4; i++) { dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), @@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { - .src_pll_truthtable = { {false, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 8c973775cfb0..4aa100bb1659 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -704,6 +704,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, struct msm_dsi_dphy_timing *timing = &phy->timing; int i; void __iomem *base = phy->base; + u32 val; DBG(""); @@ -743,9 +744,12 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); - msm_dsi_phy_set_src_pll(phy, src_pll_id, - REG_DSI_28nm_PHY_GLBL_TEST_CTRL, - DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL); + val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL); + if (phy->id == DSI_1 && src_pll_id == DSI_0) + val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + else + val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val); return 0; } @@ -763,7 +767,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { - .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 1, @@ -785,7 +788,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { - .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 1, @@ -807,7 +809,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { - .src_pll_truthtable = { {true, true}, {true, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 9ddd0adccce3..d2bfe43c9ef1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -642,7 +642,6 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { - .src_pll_truthtable = { {true, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index ce6ae2fba993..619998506b78 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -955,7 +955,6 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, @@ -978,7 +977,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { }; const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { - .src_pll_truthtable = { {false, false}, {true, false} }, .has_phy_lane = true, .reg_cfg = { .num = 1, From patchwork Wed Mar 24 15:18:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 407887 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp502616jai; Wed, 24 Mar 2021 08:20:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHnaQA05AsgCaRE+qk4LtECnlPCDAW0s3aLfLwhXyJ2hHLm1HJPU7+fxLk3F4z/JGs6NT0 X-Received: by 2002:a17:90a:1708:: with SMTP id z8mr3929418pjd.49.1616599214187; Wed, 24 Mar 2021 08:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616599214; cv=none; d=google.com; s=arc-20160816; b=PxZVImyZCE4fz1Ze0qzmywP8nG9s+L08qDk+sdffVK7hRO3Jo+FZfJYnVTAl8x36cX mhcykt7egWWrYooGELPnTSCDQgchUJHxtcf0RmW1fdmX7CRLBfou2j8Ahy/tMzsmrFTm ovsYzrKMonEgza3Qo6cFayGyaNlypoTcYcOdxQWovxSc1j0ygFfiq0YJwiQocnoIthsP 8z4lM4VCvCPqYqR4ZP+7MHPQD7DvEYCj5lK1mCJBHWeILSfFbyUUg6PgVxkG6qeCQ8Wj eA4/BxrbKcm1iBwetEgVmsbmy3oDvnk17eOwRJB4Wlwc+60yRnmSVKlHdogvsO6QC5FK 1J7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to; bh=zUR8b3Ftg76zh57gVci7fjZKfzI2P8P0hfBlI1Dck1M=; b=U4pNPAT6/Pr6RfKHEuM7XsYtwzrdFh6vMxssorPQJgzQKfuuRWSjPiTlHzJExK2cYP akovyR00szLmfCgvx+7KQ2N6h0tYeGZzkaLQ4VsASergP/54D7TvUNPqNsXGJlNQmLPa e95Av9x4oIjeyw+cXRFhiqNkGyyt/c2fOB6FAC4x6ALtEVSRqDikBOgllg7pTBTfQvPs NPruUGooFATQdf/K2IQh0ca74Iptzgg//Od84y1PKPDlSngglV9XrIMQYYpU/JoeF2W/ Rbnc4c8IImjvu3iz3E64kX6hcDY4SemuI2AYZfC2YnGTMIvJy48ATGhZ/netKIL7qzHG Ipow== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HjnW7Pbp; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id s12si2425838pgn.550.2021.03.24.08.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:20:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HjnW7Pbp; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A71246ECA8; Wed, 24 Mar 2021 15:19:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 060DB6ECA6 for ; Wed, 24 Mar 2021 15:19:46 +0000 (UTC) Received: by mail-lf1-x12c.google.com with SMTP id b4so8597447lfi.6 for ; Wed, 24 Mar 2021 08:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l3MWO0BD1Z0aMlUAjIGFvrvtw8qtZfe0+ZohERMoQm8=; b=HjnW7PbpZcp1BtXkXSp1nt1TjmvZ3F4Yv2xlbVmU1BNQllij4BAMb8rq0v0JHPySUM B3XyRHOYXXt+IOiBIH1XoB/qdDoIZNq3A993J5arKHdrLU2UMUnyTtE3ozD4bn0NtRvy v05OPA3fT6dfKbDM5tjGMOv+ISKgFFZZ+7mvJsvPGeHZ4UXenw4O4Psm2OKpiJFlZ3Fo Xa1DdKugRu0kHyJ/SdjgaSHHBtG4QPvcFnb2dqYvebPtBC7MQdtb7pCupY5AovrVfzjV EgeGeB2FeTcaLyyFl8NNJVDt25KMG5cmmvY/U0fJEV2u3EXBDZ8s7GDA4reFxMEZke3i g3fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l3MWO0BD1Z0aMlUAjIGFvrvtw8qtZfe0+ZohERMoQm8=; b=H5zLFOS1SMUUsvEFFVBrvAW5/OU5SuUAOADt1zREC9+1B7Ff1PImGCibjah7XtYNYi V0ACwwvhfKVVbqKOJpG6m67a/RxnmASqha2M1A0/6GHtk3Qt5+R8JgWbKFQQUskOQCIG Rv1PGgX5xCYYv2Wnw1XzdXIUDrGCw9dHGiZPMy0VTDuIIu6Ndi2Pde5zehl/ItKVfKwD Qqq76b8Qa8pnmRN9WBcADlIG+DNw69WdHne2UtrKLr7Gw8ctoetkkjwkxbp3BdlHjd0R 54MReFqPdFdxlh3SBfBD5od3+Yi7+4zgHWMFv4H6jHj6/D/B2IBYT8CJKqBhyBIjci/+ e9xQ== X-Gm-Message-State: AOAM532Amn+SXGWAWC0oA3IdnLW4WTSIEAIYMCxmzRB2nIN1JRfZJ4uT b9M2/hlj9tUhzhQYrrrw52DQ6Q== X-Received: by 2002:a05:6512:c1a:: with SMTP id z26mr2108841lfu.360.1616599183540; Wed, 24 Mar 2021 08:19:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d22sm255199lfm.267.2021.03.24.08.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:19:43 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette Subject: [PATCH v2 28/28] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Date: Wed, 24 Mar 2021 18:18:46 +0300 Message-Id: <20210324151846.2774204-29-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI 1 too unless DSI 1 is used in the standalone mode. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 2 +- drivers/gpu/drm/msm/dsi/dsi_manager.c | 11 +++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 4 ++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 2 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +- 10 files changed, 18 insertions(+), 19 deletions(-) -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 5c32ee2b3605..c422c8690ab3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -160,7 +160,7 @@ struct msm_dsi_phy_clk_request { void msm_dsi_phy_driver_register(void); void msm_dsi_phy_driver_unregister(void); -int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +int msm_dsi_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req); void msm_dsi_phy_disable(struct msm_dsi_phy *phy); void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 2976b09a881d..20bcb6afb52e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -109,7 +109,7 @@ static int dsi_mgr_setup_components(int id) return ret; } -static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id, +static int enable_phy(struct msm_dsi *msm_dsi, struct msm_dsi_phy_shared_timings *shared_timings) { struct msm_dsi_phy_clk_request clk_req; @@ -118,7 +118,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id, msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi); - ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req); + ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req); msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings); return ret; @@ -131,7 +131,6 @@ dsi_mgr_phy_enable(int id, struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER); struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); - int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id; int ret; /* In case of dual DSI, some registers in PHY1 have been programmed @@ -144,11 +143,11 @@ dsi_mgr_phy_enable(int id, msm_dsi_host_reset_phy(mdsi->host); msm_dsi_host_reset_phy(sdsi->host); - ret = enable_phy(mdsi, src_pll_id, + ret = enable_phy(mdsi, &shared_timings[DSI_CLOCK_MASTER]); if (ret) return ret; - ret = enable_phy(sdsi, src_pll_id, + ret = enable_phy(sdsi, &shared_timings[DSI_CLOCK_SLAVE]); if (ret) { msm_dsi_phy_disable(mdsi->phy); @@ -157,7 +156,7 @@ dsi_mgr_phy_enable(int id, } } else { msm_dsi_host_reset_phy(msm_dsi->host); - ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]); + ret = enable_phy(msm_dsi, &shared_timings[id]); if (ret) return ret; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 8f7726bb598c..851842a26872 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -753,7 +753,7 @@ void __exit msm_dsi_phy_driver_unregister(void) platform_driver_unregister(&dsi_phy_platform_driver); } -int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +int msm_dsi_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct device *dev = &phy->pdev->dev; @@ -776,7 +776,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, goto reg_en_fail; } - ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req); + ret = phy->cfg->ops.enable(phy, clk_req); if (ret) { DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret); goto phy_en_fail; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 3b207cf9f6b4..74fffcae0f10 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -19,7 +19,7 @@ struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); - int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, + int (*enable)(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req); void (*disable)(struct msm_dsi_phy *phy); void (*save_state)(struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 04535ccd11ef..bea68154ef87 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -786,7 +786,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) } } -static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { int ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 7a87bed71e36..c9afa6c461ee 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -938,7 +938,7 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0)); } -static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct msm_dsi_dphy_timing *timing = &phy->timing; @@ -996,7 +996,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); - if (phy->id == DSI_1 && src_pll_id == DSI_0) + if (phy->usecase == MSM_DSI_PHY_SLAVE) glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; else glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index f5b88c85a8fc..e96d789aea18 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -63,7 +63,7 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); } -static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct msm_dsi_dphy_timing *timing = &phy->timing; @@ -85,7 +85,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); - if (src_pll_id == DSI_1) + if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE) val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; else val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 4aa100bb1659..137e7fdfe2ef 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -698,7 +698,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) dsi_28nm_phy_regulator_enable_dcdc(phy); } -static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct msm_dsi_dphy_timing *timing = &phy->timing; @@ -745,7 +745,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL); - if (phy->id == DSI_1 && src_pll_id == DSI_0) + if (phy->usecase == MSM_DSI_PHY_SLAVE) val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; else val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index d2bfe43c9ef1..104446450f7c 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -585,7 +585,7 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy) dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88); } -static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct msm_dsi_dphy_timing *timing = &phy->timing; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 619998506b78..badc76a8d425 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -799,7 +799,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) } } -static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { int ret;