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Miller" , Jakub Kicinski , Andrew Lunn , Adrian Pop , "Michal Kubecek" , Don Bollinger , CC: Vladyslav Tarasiuk , Moshe Shemesh Subject: [RFC PATCH V5 net-next 3/5] net/mlx5: Implement get_module_eeprom_by_page() Date: Thu, 25 Mar 2021 16:56:53 +0200 Message-ID: <1616684215-4701-4-git-send-email-moshe@nvidia.com> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1616684215-4701-1-git-send-email-moshe@nvidia.com> References: <1616684215-4701-1-git-send-email-moshe@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb1f8a53-243f-4629-9997-08d8ef9e495b X-MS-TrafficTypeDiagnostic: CH2PR12MB3991: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mP0PFe+6RauRSEe1cy3JKaUNgnOKaW7GrWMZL7pzzT00x+YPJvb5B7lL2bNgQe4UmIArEupUjL4tfVDZ0ZYV+i4w0bcip95LtME0YBZJ+omr2KROJVsJE56XruBu+i9ZOXMhd8TOf0miw0UaUc2ZKqXVTAKrnu0o6j2bySbDx1fS/PxNEuNWgksbrFX01r7My/3EFCff5hvIPn4rx6jFCB0nUQtwMk5u7TO8sRpGrIzYmXyKxHe2GXQelemlhjP5SN5fDVHEK1Gd7nPDlaBYyLHC9YRxSSL+2iaik1k5R9GzRRNhKjXE3U/3ge7WTR1HGPrNciV7rhEqmiXCPKxr6oM39VymtX/LEvZoX5hpWopRwAcXMaP5BGUHb4/p0z32l+7Ft7yzn/NLdrhINYG6IgXvfeEKe4JL6gfnj83TG1ugTK1k3TIslUMBG+oHgiCYVdxAfR0iz8M8oJdtHWPZEN2Aq1LcxgySwBTCOhLycCCRtTIlSoqTfqKf2IyBB/AbpHL0S201aFtN/iDHFOBvMuf3sfWbIjXiEH9bmIcMC1dg8PmISfRP8o3pz+Ru6gccNQ5MTQ67jRlhRc+jUyzgGWwSfMGN9aIDIhjXkhMeRFa3GBlWbA5pYDqbf+YxdKcZSVSCjrxMmqWDr282rG8wrEUR8K8A9sxh4Hv9D47nM2Y= X-Forefront-Antispam-Report: CIP:216.228.112.35; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid02.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(136003)(346002)(376002)(39860400002)(36840700001)(46966006)(70586007)(70206006)(8676002)(4326008)(6666004)(8936002)(107886003)(86362001)(82310400003)(426003)(336012)(5660300002)(36756003)(2616005)(7636003)(7696005)(26005)(36860700001)(186003)(83380400001)(82740400003)(478600001)(2906002)(110136005)(54906003)(47076005)(36906005)(316002)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2021 14:57:18.5957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb1f8a53-243f-4629-9997-08d8ef9e495b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3991 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladyslav Tarasiuk Implement ethtool_ops::get_module_eeprom_by_page() to enable support of new SFP standards. Signed-off-by: Vladyslav Tarasiuk --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 44 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/port.c | 33 ++++++++++++++ include/linux/mlx5/port.h | 2 + 3 files changed, 79 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index abdf721bb264..7f413f7bd1d3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1769,6 +1769,49 @@ static int mlx5e_get_module_eeprom(struct net_device *netdev, return 0; } +static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev, + const struct ethtool_module_eeprom *page_data, + struct netlink_ext_ack *extack) +{ + struct mlx5e_priv *priv = netdev_priv(netdev); + struct mlx5_module_eeprom_query_params query; + struct mlx5_core_dev *mdev = priv->mdev; + u8 *data = page_data->data; + int size_read; + int i = 0; + + if (!page_data->length) + return -EINVAL; + + memset(data, 0, page_data->length); + + query.offset = page_data->offset; + query.i2c_address = page_data->i2c_address; + query.bank = page_data->bank; + query.page = page_data->page; + while (i < page_data->length) { + query.size = page_data->length - i; + size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i); + + /* Done reading, return how many bytes was read */ + if (!size_read) + return i; + + if (size_read == -EINVAL) + return -EINVAL; + if (size_read < 0) { + netdev_err(priv->netdev, "%s: mlx5_query_module_eeprom_by_page failed:0x%x\n", + __func__, size_read); + return i; + } + + i += size_read; + query.offset += size_read; + } + + return i; +} + int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, struct ethtool_flash *flash) { @@ -2148,6 +2191,7 @@ const struct ethtool_ops mlx5e_ethtool_ops = { .set_wol = mlx5e_set_wol, .get_module_info = mlx5e_get_module_info, .get_module_eeprom = mlx5e_get_module_eeprom, + .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page, .flash_device = mlx5e_flash_device, .get_priv_flags = mlx5e_get_priv_flags, .set_priv_flags = mlx5e_set_priv_flags, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index 9b9f870d67a4..114214728e32 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -428,6 +428,39 @@ int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, } EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom); +int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, + struct mlx5_module_eeprom_query_params *params, + u8 *data) +{ + u8 module_id; + int err; + + err = mlx5_query_module_num(dev, ¶ms->module_number); + if (err) + return err; + + err = mlx5_query_module_id(dev, params->module_number, &module_id); + if (err) + return err; + + if (module_id != MLX5_MODULE_ID_SFP && + module_id != MLX5_MODULE_ID_QSFP && + module_id != MLX5_MODULE_ID_QSFP28 && + module_id != MLX5_MODULE_ID_QSFP_PLUS) { + mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id); + return -EINVAL; + } + + if (params->i2c_address != MLX5_I2C_ADDR_HIGH && + params->i2c_address != MLX5_I2C_ADDR_LOW) { + mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address); + return -EINVAL; + } + + return mlx5_query_mcia(dev, params, data); +} +EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page); + static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, int pvlc_size, u8 local_port) { diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index 90b87aa82db3..58d56adb9842 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -209,6 +209,8 @@ void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, bool *enabled); int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, u16 offset, u16 size, u8 *data); +int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, + struct mlx5_module_eeprom_query_params *params, u8 *data); int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); From patchwork Thu Mar 25 14:56:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moshe Shemesh X-Patchwork-Id: 409317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC903C433E4 for ; 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Miller" , Jakub Kicinski , Andrew Lunn , Adrian Pop , "Michal Kubecek" , Don Bollinger , CC: Vladyslav Tarasiuk , Moshe Shemesh Subject: [RFC PATCH V5 net-next 4/5] net/mlx5: Add support for DSFP module EEPROM dumps Date: Thu, 25 Mar 2021 16:56:54 +0200 Message-ID: <1616684215-4701-5-git-send-email-moshe@nvidia.com> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1616684215-4701-1-git-send-email-moshe@nvidia.com> References: <1616684215-4701-1-git-send-email-moshe@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 590be90e-e8d9-4e42-cdf1-08d8ef9e4ad1 X-MS-TrafficTypeDiagnostic: BN8PR12MB3041: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1201; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lDK/kGRoQzzNprnLYjCunrajNeMOv67XoW+hSmZCVJHzVhFmMunLj0wHBoX4+MG5MDxgQlqicQq8Yd4Hmucg/59npMExjFOLL87PeY6Jl8vtnnN5evT1cSqeuiNiJjXgGkeO28pnAK+GsV/GHE7wC+I28bQt40pCTOrp1dBImnT24KFxhHUNCylakKX8fSnqZyR6Gzhv08niab2FZVxzcr4bNFUJpmrvLAw1TzmHWXPZOTK6FpLGNc8XIOwXXwo36DyD6inUCNtyvqTdwaROEgI4CfvQIKF0JppmW8Bpf6j3I+4B0n9Wf2FureVLzoJFl6p+sL5HiiqeoL5rzpu9V69b26d+LNXgpVmSbr7XLTjzzW1yOvEpLa782K3NW33PzTiNANMXtnRkkSKG1KC6V2fNexo1ORjpIy/hckTK3Fb4p/E+zbI3rOHskoNrW5aYnwXNensfgty2RdRYCjZlxHHWDHKyuS9pItiQ7aLtAazyAJO9nr1Qmcqd4olKGqD2dqXwFf7rR7lyBDcLI0deJ3/K+A/7WPHG9ndX9skY07BVlQa4KlDN33DS6n3USE1//mQ6yiDd9baiJFdzmk4PzCS/5z/mBZxWMp7FKlVLa50dAOg+V/P/68mXsv60oEwktQrJDbEsEDuZef1bRLwjEN6MAYm6G6S7d90xonceCEc= X-Forefront-Antispam-Report: CIP:216.228.112.36; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid05.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(136003)(396003)(376002)(39860400002)(46966006)(36840700001)(8676002)(70206006)(6666004)(4326008)(86362001)(8936002)(82310400003)(107886003)(426003)(70586007)(5660300002)(36756003)(336012)(2616005)(478600001)(36860700001)(26005)(36906005)(110136005)(186003)(356005)(83380400001)(2906002)(82740400003)(7696005)(47076005)(7636003)(316002)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2021 14:57:21.0940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 590be90e-e8d9-4e42-cdf1-08d8ef9e4ad1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3041 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vladyslav Tarasiuk Allow the driver to recognise DSFP transceiver module ID and therefore allow its EEPROM dumps using ethtool. Signed-off-by: Vladyslav Tarasiuk --- drivers/net/ethernet/mellanox/mlx5/core/port.c | 3 ++- include/linux/mlx5/port.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index 114214728e32..5008d6d30899 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -446,7 +446,8 @@ int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, if (module_id != MLX5_MODULE_ID_SFP && module_id != MLX5_MODULE_ID_QSFP && module_id != MLX5_MODULE_ID_QSFP28 && - module_id != MLX5_MODULE_ID_QSFP_PLUS) { + module_id != MLX5_MODULE_ID_QSFP_PLUS && + module_id != MLX5_MODULE_ID_DSFP) { mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id); return -EINVAL; } diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index 58d56adb9842..77ea4f9c5265 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -45,6 +45,7 @@ enum mlx5_module_id { MLX5_MODULE_ID_QSFP = 0xC, MLX5_MODULE_ID_QSFP_PLUS = 0xD, MLX5_MODULE_ID_QSFP28 = 0x11, + MLX5_MODULE_ID_DSFP = 0x1B, }; enum mlx5_an_status {