From patchwork Tue Mar 30 15:53:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 411850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7365DC433E2 for ; Tue, 30 Mar 2021 15:54:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 49FDE619D0 for ; Tue, 30 Mar 2021 15:54:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232038AbhC3Px6 (ORCPT ); Tue, 30 Mar 2021 11:53:58 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:33515 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231928AbhC3Pxv (ORCPT ); Tue, 30 Mar 2021 11:53:51 -0400 X-UUID: cdfcb64d03e249b68ac9cf69be0be67d-20210330 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Wr7OqfMZ053MusTJu/z+VocLvngnE0TDREtT13ee894=; b=P6AF6UVnsg5ccVpaHqw+Mv/WrX1xihFP/yybTX4o9QcJCjy9Xh/CJRK6Duuso6slZMXPuEOzaNgdhKONRk6zxU9bd7wErdsWaHUv8q0u6OU3f10FMydKKNbCsjqteZZbO3EvYtE9EG+tN6EPjBQ+UPrT4pL63ndwXRue1uIDCpQ=; X-UUID: cdfcb64d03e249b68ac9cf69be0be67d-20210330 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1627379242; Tue, 30 Mar 2021 23:53:44 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Mar 2021 23:53:34 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Mar 2021 23:53:34 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 1/3] drm/mediatek: dpi dual edge sample mode support Date: Tue, 30 Mar 2021 23:53:28 +0800 Message-ID: <20210330155330.28759-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20210330155330.28759-1-jitao.shi@mediatek.com> References: <20210330155330.28759-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4E04AEDD8294558B6CA67C7A5725B4939BD2C14C727429A5AA679777471F38242000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DPI can sample on falling, rising or both edge. When DPI sample the data both rising and falling edge. It can reduce half data io pins. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.12.5 diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..ccd681a2a4c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -81,6 +81,7 @@ struct mtk_dpi { struct pinctrl *pinctrl; struct pinctrl_state *pins_gpio; struct pinctrl_state *pins_dpi; + bool ddr_edge_sel; int refcount; }; @@ -119,6 +120,7 @@ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; bool edge_sel_en; + bool dual_edge; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -378,6 +380,15 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, } } +static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) +{ + if (dpi->conf->dual_edge) { + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, + DDR_EN | DDR_4PHASE); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->ddr_edge_sel ? EDGE_SEL : 0, EDGE_SEL); + } +} + static void mtk_dpi_power_off(struct mtk_dpi *dpi) { if (WARN_ON(dpi->refcount == 0)) @@ -516,6 +527,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); mtk_dpi_sw_reset(dpi, false); From patchwork Tue Mar 30 15:53:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 411851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E167AC433DB for ; Tue, 30 Mar 2021 15:54:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 88EAA619C1 for ; Tue, 30 Mar 2021 15:54:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231627AbhC3Px5 (ORCPT ); Tue, 30 Mar 2021 11:53:57 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:24273 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232010AbhC3Pxp (ORCPT ); Tue, 30 Mar 2021 11:53:45 -0400 X-UUID: e92ab97509cd46d5b9cb9cf84a98eca6-20210330 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=l43RF5d75CbzhSmjnnJywgmGdgh/n0rM1Sm0c+0swbU=; b=j1mdZbibwWyji8+KTEATccww4TWCrdwiT9T5JD2rE47JkDEtmWUIOudP3fLyHbZ1AsZsj7PTgxc03MEj41Y+qouflcBCxDIp6tyFA7S+mCsddoBCvpJEiHWoYEND8HdFQk3Wuh0Pl7MNkeVmgsV74DN1sl9fOAlkOlM3ZKrLFjY=; X-UUID: e92ab97509cd46d5b9cb9cf84a98eca6-20210330 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1695908553; Tue, 30 Mar 2021 23:53:38 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Mar 2021 23:53:36 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Mar 2021 23:53:35 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 2/3] drm/mediatek: config mt8183 driver data to support dual edge sample Date: Tue, 30 Mar 2021 23:53:29 +0800 Message-ID: <20210330155330.28759-3-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20210330155330.28759-1-jitao.shi@mediatek.com> References: <20210330155330.28759-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 23E89B638CF9D689B22C63EDCEFA005AD9C41F3FC233A26809757DA39A64B9BB2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 1 + 1 file changed, 1 insertion(+) -- 2.12.5 diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index ccd681a2a4c2..87bb27649c4c 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -696,6 +696,7 @@ static const struct mtk_dpi_conf mt2701_conf = { static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .dual_edge = true, }; static int mtk_dpi_probe(struct platform_device *pdev) From patchwork Tue Mar 30 15:53:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 413094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16254C433C1 for ; Tue, 30 Mar 2021 15:54:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9AA9619C1 for ; Tue, 30 Mar 2021 15:54:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231636AbhC3Px4 (ORCPT ); Tue, 30 Mar 2021 11:53:56 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:26439 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232019AbhC3Pxn (ORCPT ); Tue, 30 Mar 2021 11:53:43 -0400 X-UUID: e5880d103ace46bf9422aabf77eb5f49-20210330 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Ra2tQWislgrrvR/NNOOoxRe0xoVjwCWjHOtfv1mHfLs=; b=D6hOLsg/MHGNArJKE1W6jM63Zkti4CNPCCwZfHQRFqf65/AvqS737uKFbf17+kj7QOnjwhiV8rG18O4akuQFqMILdMZUrEwMcTDiFHCtZ7+/9s/k4nUXoPMFFhTMVwuQrZtXmficshBrC7Tpx0NoE+96ptVSQgZfYJ4aEN0ygvM=; X-UUID: e5880d103ace46bf9422aabf77eb5f49-20210330 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1995736300; Tue, 30 Mar 2021 23:53:39 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Mar 2021 23:53:37 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Mar 2021 23:53:36 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 3/3] drm/mediatek: dpi: add bus format negociation Date: Tue, 30 Mar 2021 23:53:30 +0800 Message-ID: <20210330155330.28759-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20210330155330.28759-1-jitao.shi@mediatek.com> References: <20210330155330.28759-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: C82F1249AC34DA01D8B6F8A0C1B09D132640BF19AE22DA65BDDE8C39F907EC832000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate the possible output and input formats for the current mode and monitor, and use the negotiated formats in a basic atomic_check callback. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 96 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 91 insertions(+), 5 deletions(-) -- 2.12.5 diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 87bb27649c4c..4e45d1b01b0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -81,6 +81,8 @@ struct mtk_dpi { struct pinctrl *pinctrl; struct pinctrl_state *pins_gpio; struct pinctrl_state *pins_dpi; + unsigned int in_bus_format; + unsigned int out_bus_format; bool ddr_edge_sel; int refcount; }; @@ -534,6 +536,92 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, return 0; } +#define MAX_OUTPUT_SEL_FORMATS 2 + +static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + struct drm_display_mode *mode = &crtc_state->mode; + u32 *output_fmts; + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + *num_output_fmts = 0; + + output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), + GFP_KERNEL); + if (!output_fmts) + return NULL; + + /* Default 8bit RGB fallback */ + if (dpi->conf->dual_edge) { + output_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; + output_fmts[1] = MEDIA_BUS_FMT_RGB888_2X12_BE; + *num_output_fmts = 2; + } else { + output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + *num_output_fmts = 1; + } + + return output_fmts; +} + +#define MAX_INPUT_SEL_FORMATS 1 + +static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + *num_input_fmts = 0; + + input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), + GFP_KERNEL); + if (!input_fmts) + return NULL; + + *num_input_fmts = 1; + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + + return input_fmts; +} + +static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct mtk_dpi *dpi = bridge->driver_private; + + dpi->out_bus_format = bridge_state->output_bus_cfg.format; + + dpi->in_bus_format = bridge_state->input_bus_cfg.format; + + dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); + + if (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE || + dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_BE) { + dpi->ddr_edge_sel = + (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ? + true : false; + } + + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; + dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; + dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + + return 0; +} + static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { @@ -572,6 +660,9 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .mode_set = mtk_dpi_bridge_mode_set, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, + .atomic_check = mtk_dpi_bridge_atomic_check, + .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, + .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, }; static void mtk_dpi_start(struct mtk_ddp_comp *comp) @@ -621,11 +712,6 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) goto err_cleanup; } - dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; - dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; - dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; - return 0; err_cleanup: